From cc888b2ccaa7286fd3c227c94a06997d11a3f32b Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 17 Mar 2026 14:32:15 -0700 Subject: [PATCH] cndm: Add support to core logic for board control logic Signed-off-by: Alex Forencich --- src/cndm/rtl/cndm_lite_core.sv | 29 ++++- src/cndm/rtl/cndm_lite_pcie_us.sv | 14 ++ src/cndm/rtl/cndm_micro_core.sv | 29 ++++- src/cndm/rtl/cndm_micro_dp_mgr.sv | 123 +++++++++++++++++- src/cndm/rtl/cndm_micro_pcie_us.sv | 14 ++ src/cndm/tb/cndm.py | 30 +++++ src/cndm/tb/cndm_lite_pcie_us/Makefile | 1 + .../test_cndm_lite_pcie_us.py | 7 +- .../test_cndm_lite_pcie_us.sv | 17 +++ src/cndm/tb/cndm_micro_pcie_us/Makefile | 1 + .../test_cndm_micro_pcie_us.py | 7 +- .../test_cndm_micro_pcie_us.sv | 17 +++ 12 files changed, 270 insertions(+), 19 deletions(-) diff --git a/src/cndm/rtl/cndm_lite_core.sv b/src/cndm/rtl/cndm_lite_core.sv index ac1a55b..c04e43b 100644 --- a/src/cndm/rtl/cndm_lite_core.sv +++ b/src/cndm/rtl/cndm_lite_core.sv @@ -35,6 +35,7 @@ module cndm_lite_core #( // Structural configuration parameter PORTS = 2, + parameter logic BRD_CTRL_EN = 1'b0, parameter SYS_CLK_PER_NS_NUM = 4, parameter SYS_CLK_PER_NS_DEN = 1, @@ -73,6 +74,12 @@ module cndm_lite_core #( */ taxi_axis_if.src m_axis_irq, + /* + * Board control + */ + taxi_axis_if.src m_axis_brd_ctrl_cmd, + taxi_axis_if.snk s_axis_brd_ctrl_rsp, + /* * PTP */ @@ -115,10 +122,13 @@ localparam RAM_SEG_DATA_W = dma_ram_wr.SEG_DATA_W; localparam RAM_SEG_BE_W = dma_ram_wr.SEG_BE_W; localparam RAM_SEL_W = dma_ram_wr.SEL_W; -localparam PORT_OFFSET_DP = PTP_TS_EN ? 1 : 0; +localparam PTP_OFFSET_DP = 0; +localparam PORT_OFFSET_DP = PTP_OFFSET_DP + (PTP_TS_EN ? 1 : 0); localparam PORT_OFFSET_HOST = 2; -localparam PORT_BASE_ADDR_DP = PTP_TS_EN ? 32'h00010000 : 32'h00000000; -localparam PORT_BASE_ADDR_HOST = 32'h00020000; + +localparam PTP_BASE_ADDR_DP = PTP_OFFSET_DP * 32'h00010000; +localparam PORT_BASE_ADDR_DP = PORT_OFFSET_DP * 32'h00010000; +localparam PORT_BASE_ADDR_HOST = PORT_OFFSET_HOST * 32'h00010000; localparam SYS_CLK_CYC_PER_US = (1000*SYS_CLK_PER_NS_DEN+SYS_CLK_PER_NS_NUM-1)/SYS_CLK_PER_NS_NUM; @@ -331,6 +341,7 @@ cndm_micro_dp_mgr #( // Structural configuration .PORTS(PORTS), + .BRD_CTRL_EN(BRD_CTRL_EN), .SYS_CLK_PER_NS_NUM(SYS_CLK_PER_NS_NUM), .SYS_CLK_PER_NS_DEN(SYS_CLK_PER_NS_DEN), @@ -346,7 +357,7 @@ cndm_micro_dp_mgr #( .PTP_CLK_PER_NS_DEN(PTP_CLK_PER_NS_DEN), // Addressing - .PTP_BASE_ADDR_DP(0), + .PTP_BASE_ADDR_DP(PTP_BASE_ADDR_DP), .PORT_BASE_ADDR_DP(PORT_BASE_ADDR_DP), .PORT_BASE_ADDR_HOST(PORT_BASE_ADDR_HOST) ) @@ -363,7 +374,13 @@ dp_mgr_inst ( /* * APB master interface (datapath control) */ - .m_apb_dp_ctrl(apb_dp_ctrl) + .m_apb_dp_ctrl(apb_dp_ctrl), + + /* + * Board control + */ + .m_axis_brd_ctrl_cmd(m_axis_brd_ctrl_cmd), + .s_axis_brd_ctrl_rsp(s_axis_brd_ctrl_rsp) ); taxi_apb_if #( @@ -408,7 +425,7 @@ if (PTP_TS_EN) begin : ptp /* * Control register interface */ - .s_apb(apb_port_dp_ctrl[0]), + .s_apb(apb_port_dp_ctrl[PTP_OFFSET_DP]), /* * PTP diff --git a/src/cndm/rtl/cndm_lite_pcie_us.sv b/src/cndm/rtl/cndm_lite_pcie_us.sv index f5c0922..d1e286c 100644 --- a/src/cndm/rtl/cndm_lite_pcie_us.sv +++ b/src/cndm/rtl/cndm_lite_pcie_us.sv @@ -35,6 +35,7 @@ module cndm_lite_pcie_us #( // Structural configuration parameter PORTS = 2, + parameter logic BRD_CTRL_EN = 1'b0, parameter SYS_CLK_PER_NS_NUM = 4, parameter SYS_CLK_PER_NS_DEN = 1, @@ -109,6 +110,12 @@ module cndm_lite_pcie_us #( output wire logic [7:0] cfg_interrupt_msi_tph_st_tag, output wire logic [7:0] cfg_interrupt_msi_function_number, + /* + * Board control + */ + taxi_axis_if.src m_axis_brd_ctrl_cmd, + taxi_axis_if.snk s_axis_brd_ctrl_rsp, + /* * PTP */ @@ -561,6 +568,7 @@ cndm_lite_core #( // Structural configuration .PORTS(PORTS), + .BRD_CTRL_EN(BRD_CTRL_EN), .SYS_CLK_PER_NS_NUM(SYS_CLK_PER_NS_NUM), .SYS_CLK_PER_NS_DEN(SYS_CLK_PER_NS_DEN), @@ -599,6 +607,12 @@ core_inst ( */ .m_axis_irq(axis_irq), + /* + * Board control + */ + .m_axis_brd_ctrl_cmd(m_axis_brd_ctrl_cmd), + .s_axis_brd_ctrl_rsp(s_axis_brd_ctrl_rsp), + /* * PTP */ diff --git a/src/cndm/rtl/cndm_micro_core.sv b/src/cndm/rtl/cndm_micro_core.sv index a3c4a04..827a6c5 100644 --- a/src/cndm/rtl/cndm_micro_core.sv +++ b/src/cndm/rtl/cndm_micro_core.sv @@ -35,6 +35,7 @@ module cndm_micro_core #( // Structural configuration parameter PORTS = 2, + parameter logic BRD_CTRL_EN = 1'b0, parameter SYS_CLK_PER_NS_NUM = 4, parameter SYS_CLK_PER_NS_DEN = 1, @@ -73,6 +74,12 @@ module cndm_micro_core #( */ taxi_axis_if.src m_axis_irq, + /* + * Board control + */ + taxi_axis_if.src m_axis_brd_ctrl_cmd, + taxi_axis_if.snk s_axis_brd_ctrl_rsp, + /* * PTP */ @@ -115,10 +122,13 @@ localparam RAM_SEG_DATA_W = dma_ram_wr.SEG_DATA_W; localparam RAM_SEG_BE_W = dma_ram_wr.SEG_BE_W; localparam RAM_SEL_W = dma_ram_wr.SEL_W; -localparam PORT_OFFSET_DP = PTP_TS_EN ? 1 : 0; +localparam PTP_OFFSET_DP = 0; +localparam PORT_OFFSET_DP = PTP_OFFSET_DP + (PTP_TS_EN ? 1 : 0); localparam PORT_OFFSET_HOST = 2; -localparam PORT_BASE_ADDR_DP = PTP_TS_EN ? 32'h00010000 : 32'h00000000; -localparam PORT_BASE_ADDR_HOST = 32'h00020000; + +localparam PTP_BASE_ADDR_DP = PTP_OFFSET_DP * 32'h00010000; +localparam PORT_BASE_ADDR_DP = PORT_OFFSET_DP * 32'h00010000; +localparam PORT_BASE_ADDR_HOST = PORT_OFFSET_HOST * 32'h00010000; localparam SYS_CLK_CYC_PER_US = (1000*SYS_CLK_PER_NS_DEN+SYS_CLK_PER_NS_NUM-1)/SYS_CLK_PER_NS_NUM; @@ -331,6 +341,7 @@ cndm_micro_dp_mgr #( // Structural configuration .PORTS(PORTS), + .BRD_CTRL_EN(BRD_CTRL_EN), .SYS_CLK_PER_NS_NUM(SYS_CLK_PER_NS_NUM), .SYS_CLK_PER_NS_DEN(SYS_CLK_PER_NS_DEN), @@ -346,7 +357,7 @@ cndm_micro_dp_mgr #( .PTP_CLK_PER_NS_DEN(PTP_CLK_PER_NS_DEN), // Addressing - .PTP_BASE_ADDR_DP(0), + .PTP_BASE_ADDR_DP(PTP_BASE_ADDR_DP), .PORT_BASE_ADDR_DP(PORT_BASE_ADDR_DP), .PORT_BASE_ADDR_HOST(PORT_BASE_ADDR_HOST) ) @@ -363,7 +374,13 @@ dp_mgr_inst ( /* * APB master interface (datapath control) */ - .m_apb_dp_ctrl(apb_dp_ctrl) + .m_apb_dp_ctrl(apb_dp_ctrl), + + /* + * Board control + */ + .m_axis_brd_ctrl_cmd(m_axis_brd_ctrl_cmd), + .s_axis_brd_ctrl_rsp(s_axis_brd_ctrl_rsp) ); taxi_apb_if #( @@ -408,7 +425,7 @@ if (PTP_TS_EN) begin : ptp /* * Control register interface */ - .s_apb(apb_port_dp_ctrl[0]), + .s_apb(apb_port_dp_ctrl[PTP_OFFSET_DP]), /* * PTP diff --git a/src/cndm/rtl/cndm_micro_dp_mgr.sv b/src/cndm/rtl/cndm_micro_dp_mgr.sv index b7854ff..0a3b0c5 100644 --- a/src/cndm/rtl/cndm_micro_dp_mgr.sv +++ b/src/cndm/rtl/cndm_micro_dp_mgr.sv @@ -29,6 +29,7 @@ module cndm_micro_dp_mgr # // Structural configuration parameter PORTS = 2, + parameter logic BRD_CTRL_EN = 1'b0, parameter SYS_CLK_PER_NS_NUM = 4, parameter SYS_CLK_PER_NS_DEN = 1, @@ -73,14 +74,24 @@ module cndm_micro_dp_mgr # /* * APB master interface (datapath control) */ - taxi_apb_if.mst m_apb_dp_ctrl + taxi_apb_if.mst m_apb_dp_ctrl, + + /* + * Board control + */ + taxi_axis_if.src m_axis_brd_ctrl_cmd, + taxi_axis_if.snk s_axis_brd_ctrl_rsp ); // extract parameters +localparam CMD_ID_W = s_axis_cmd.ID_W; + localparam DP_APB_ADDR_W = m_apb_dp_ctrl.ADDR_W; localparam DP_APB_DATA_W = m_apb_dp_ctrl.DATA_W; localparam DP_APB_STRB_W = m_apb_dp_ctrl.STRB_W; +localparam BRD_CMD_ID_W = m_axis_brd_ctrl_cmd.ID_W; + typedef enum logic [15:0] { CMD_OP_NOP = 16'h0000, @@ -88,6 +99,9 @@ typedef enum logic [15:0] { CMD_OP_ACCESS_REG = 16'h0180, CMD_OP_PTP = 16'h0190, + CMD_OP_HWID = 16'h01A0, + CMD_OP_HWMON = 16'h01B0, + CMD_OP_PLL = 16'h01C0, CMD_OP_CREATE_EQ = 16'h0200, CMD_OP_MODIFY_EQ = 16'h0201, @@ -143,6 +157,8 @@ typedef enum logic [4:0] { STATE_PTP_READ_1, STATE_PTP_READ_2, STATE_PTP_SET, + STATE_BOARD_CMD, + STATE_BOARD_RSP, STATE_SEND_RSP, STATE_PAD_RSP } state_t; @@ -154,6 +170,7 @@ logic s_axis_cmd_tready_reg = 1'b0, s_axis_cmd_tready_next; logic [31:0] m_axis_rsp_tdata_reg = '0, m_axis_rsp_tdata_next; logic m_axis_rsp_tvalid_reg = 1'b0, m_axis_rsp_tvalid_next; logic m_axis_rsp_tlast_reg = 1'b0, m_axis_rsp_tlast_next; +logic [CMD_ID_W-1:0] m_axis_rsp_tid_reg = '0, m_axis_rsp_tid_next; logic [DP_APB_ADDR_W-1:0] m_apb_dp_ctrl_paddr_reg = '0, m_apb_dp_ctrl_paddr_next; logic m_apb_dp_ctrl_psel_reg = 1'b0, m_apb_dp_ctrl_psel_next; @@ -162,6 +179,13 @@ logic m_apb_dp_ctrl_pwrite_reg = 1'b0, m_apb_dp_ctrl_pwrite_next; logic [DP_APB_DATA_W-1:0] m_apb_dp_ctrl_pwdata_reg = '0, m_apb_dp_ctrl_pwdata_next; logic [DP_APB_STRB_W-1:0] m_apb_dp_ctrl_pstrb_reg = '0, m_apb_dp_ctrl_pstrb_next; +logic [31:0] m_axis_brd_ctrl_cmd_tdata_reg = '0, m_axis_brd_ctrl_cmd_tdata_next; +logic m_axis_brd_ctrl_cmd_tvalid_reg = 1'b0, m_axis_brd_ctrl_cmd_tvalid_next; +logic m_axis_brd_ctrl_cmd_tlast_reg = 1'b0, m_axis_brd_ctrl_cmd_tlast_next; +logic [BRD_CMD_ID_W-1:0] m_axis_brd_ctrl_cmd_tid_reg = '0, m_axis_brd_ctrl_cmd_tid_next; + +logic s_axis_brd_ctrl_rsp_tready_reg = 1'b0, s_axis_brd_ctrl_rsp_tready_next; + // command RAM localparam CMD_AW = 4; @@ -267,7 +291,7 @@ assign m_axis_rsp.tkeep = '1; assign m_axis_rsp.tstrb = m_axis_rsp.tkeep; assign m_axis_rsp.tvalid = m_axis_rsp_tvalid_reg; assign m_axis_rsp.tlast = m_axis_rsp_tlast_reg; -assign m_axis_rsp.tid = '0; +assign m_axis_rsp.tid = m_axis_rsp_tid_reg; assign m_axis_rsp.tdest = '0; assign m_axis_rsp.tuser = '0; @@ -281,6 +305,17 @@ assign m_apb_dp_ctrl.pstrb = m_apb_dp_ctrl_pstrb_reg; assign m_apb_dp_ctrl.pauser = '0; assign m_apb_dp_ctrl.pwuser = '0; +assign m_axis_brd_ctrl_cmd.tdata = m_axis_brd_ctrl_cmd_tdata_reg; +assign m_axis_brd_ctrl_cmd.tkeep = '1; +assign m_axis_brd_ctrl_cmd.tstrb = m_axis_brd_ctrl_cmd.tkeep; +assign m_axis_brd_ctrl_cmd.tvalid = m_axis_brd_ctrl_cmd_tvalid_reg; +assign m_axis_brd_ctrl_cmd.tlast = m_axis_brd_ctrl_cmd_tlast_reg; +assign m_axis_brd_ctrl_cmd.tid = m_axis_brd_ctrl_cmd_tid_reg; +assign m_axis_brd_ctrl_cmd.tdest = '0; +assign m_axis_brd_ctrl_cmd.tuser = '0; + +assign s_axis_brd_ctrl_rsp.tready = s_axis_brd_ctrl_rsp_tready_reg; + logic cmd_frame_reg = 1'b0, cmd_frame_next; logic [3:0] cmd_wr_ptr_reg = '0, cmd_wr_ptr_next; logic rsp_frame_reg = 1'b0, rsp_frame_next; @@ -308,6 +343,7 @@ always_comb begin m_axis_rsp_tdata_next = m_axis_rsp_tdata_reg; m_axis_rsp_tvalid_next = m_axis_rsp_tvalid_reg && !m_axis_rsp.tready; m_axis_rsp_tlast_next = m_axis_rsp_tlast_reg; + m_axis_rsp_tid_next = m_axis_rsp_tid_reg; m_apb_dp_ctrl_paddr_next = m_apb_dp_ctrl_paddr_reg; m_apb_dp_ctrl_psel_next = m_apb_dp_ctrl_psel_reg && !m_apb_dp_ctrl.pready; @@ -316,6 +352,13 @@ always_comb begin m_apb_dp_ctrl_pwdata_next = m_apb_dp_ctrl_pwdata_reg; m_apb_dp_ctrl_pstrb_next = m_apb_dp_ctrl_pstrb_reg; + m_axis_brd_ctrl_cmd_tdata_next = m_axis_brd_ctrl_cmd_tdata_reg; + m_axis_brd_ctrl_cmd_tvalid_next = m_axis_brd_ctrl_cmd_tvalid_reg && !m_axis_brd_ctrl_cmd.tready; + m_axis_brd_ctrl_cmd_tlast_next = m_axis_brd_ctrl_cmd_tlast_reg; + m_axis_brd_ctrl_cmd_tid_next = m_axis_brd_ctrl_cmd_tid_reg; + + s_axis_brd_ctrl_rsp_tready_next = s_axis_brd_ctrl_rsp_tready_reg; + cmd_ram_wr_data = s_axis_cmd.tdata; cmd_ram_wr_addr = cmd_wr_ptr_reg; cmd_ram_wr_en = 1'b0; @@ -481,13 +524,13 @@ always_comb begin if (flags_reg[15:0] != 0) begin // update something cmd_ptr_next = 2; - dp_ptr_next = PTP_BASE_ADDR_DP + 'h50; + dp_ptr_next = DP_APB_ADDR_W'(PTP_BASE_ADDR_DP + 'h50); cnt_next = '0; state_next = STATE_PTP_SET; end else begin // dump state cmd_ptr_next = 2; - dp_ptr_next = PTP_BASE_ADDR_DP + 'h30; + dp_ptr_next = DP_APB_ADDR_W'(PTP_BASE_ADDR_DP + 'h30); cnt_next = '0; state_next = STATE_PTP_READ_1; end @@ -500,6 +543,20 @@ always_comb begin state_next = STATE_SEND_RSP; end end + CMD_OP_HWID, CMD_OP_HWMON, CMD_OP_PLL: begin + if (BRD_CTRL_EN) begin + // Forward board command + cmd_ptr_next = 2; + state_next = STATE_BOARD_CMD; + end else begin + // PTP not enabled + m_axis_rsp_tdata_next = '0; // TODO + m_axis_rsp_tvalid_next = 1'b1; + m_axis_rsp_tlast_next = 1'b0; + + state_next = STATE_SEND_RSP; + end + end CMD_OP_CREATE_EQ, CMD_OP_CREATE_CQ, CMD_OP_CREATE_SQ, @@ -866,7 +923,7 @@ always_comb begin state_next = STATE_SEND_RSP; end else if (cnt_reg == 7) begin // jump to period registers - dp_ptr_next = PTP_BASE_ADDR_DP + 'h70; + dp_ptr_next = DP_APB_ADDR_W'(PTP_BASE_ADDR_DP + 'h70); state_next = STATE_PTP_READ_1; end else begin // more to read @@ -959,6 +1016,51 @@ always_comb begin state_next = STATE_PTP_SET; end end + STATE_BOARD_CMD: begin + // send board command + cmd_ram_rd_addr = cmd_ptr_reg; + + if (m_axis_brd_ctrl_cmd.tready || !m_axis_brd_ctrl_cmd.tvalid) begin + m_axis_brd_ctrl_cmd_tdata_next = cmd_ram_rd_data; + m_axis_brd_ctrl_cmd_tvalid_next = 1'b1; + m_axis_brd_ctrl_cmd_tlast_next = &cmd_ptr_reg; + + cmd_ptr_next = cmd_ptr_reg + 1; + + if (&cmd_ptr_reg) begin + cmd_ptr_next = 2; + state_next = STATE_BOARD_RSP; + end else begin + state_next = STATE_BOARD_CMD; + end + end else begin + state_next = STATE_BOARD_CMD; + end + end + STATE_BOARD_RSP: begin + // store response + s_axis_brd_ctrl_rsp_tready_next = 1'b1; + + cmd_ram_wr_data = s_axis_brd_ctrl_rsp.tdata; + cmd_ram_wr_addr = cmd_ptr_reg; + cmd_ram_wr_en = 1'b1; + + if (s_axis_brd_ctrl_rsp.tready && s_axis_brd_ctrl_rsp.tvalid) begin + cmd_ptr_next = cmd_ptr_reg + 1; + + if (s_axis_brd_ctrl_rsp.tlast) begin + m_axis_rsp_tdata_next = '0; // TODO + m_axis_rsp_tvalid_next = 1'b1; + m_axis_rsp_tlast_next = 1'b0; + + state_next = STATE_SEND_RSP; + end else begin + state_next = STATE_BOARD_RSP; + end + end else begin + state_next = STATE_BOARD_RSP; + end + end STATE_SEND_RSP: begin // send response in the form of an edited command cmd_ram_rd_addr = rsp_rd_ptr_reg; @@ -1037,6 +1139,7 @@ always_ff @(posedge clk) begin m_axis_rsp_tdata_reg <= m_axis_rsp_tdata_next; m_axis_rsp_tvalid_reg <= m_axis_rsp_tvalid_next; m_axis_rsp_tlast_reg <= m_axis_rsp_tlast_next; + m_axis_rsp_tid_reg <= m_axis_rsp_tid_next; m_apb_dp_ctrl_paddr_reg <= m_apb_dp_ctrl_paddr_next; m_apb_dp_ctrl_psel_reg <= m_apb_dp_ctrl_psel_next; @@ -1045,6 +1148,13 @@ always_ff @(posedge clk) begin m_apb_dp_ctrl_pwdata_reg <= m_apb_dp_ctrl_pwdata_next; m_apb_dp_ctrl_pstrb_reg <= m_apb_dp_ctrl_pstrb_next; + m_axis_brd_ctrl_cmd_tdata_reg <= m_axis_brd_ctrl_cmd_tdata_next; + m_axis_brd_ctrl_cmd_tvalid_reg <= m_axis_brd_ctrl_cmd_tvalid_next; + m_axis_brd_ctrl_cmd_tlast_reg <= m_axis_brd_ctrl_cmd_tlast_next; + m_axis_brd_ctrl_cmd_tid_reg <= m_axis_brd_ctrl_cmd_tid_next; + + s_axis_brd_ctrl_rsp_tready_reg <= s_axis_brd_ctrl_rsp_tready_next; + cmd_frame_reg <= cmd_frame_next; cmd_wr_ptr_reg <= cmd_wr_ptr_next; rsp_frame_reg <= rsp_frame_next; @@ -1073,6 +1183,9 @@ always_ff @(posedge clk) begin m_apb_dp_ctrl_psel_reg <= 1'b0; m_apb_dp_ctrl_penable_reg <= 1'b0; + m_axis_brd_ctrl_cmd_tvalid_reg <= 1'b0; + s_axis_brd_ctrl_rsp_tready_reg <= 1'b0; + cmd_frame_reg <= 1'b0; cmd_wr_ptr_reg <= '0; rsp_frame_reg <= 1'b0; diff --git a/src/cndm/rtl/cndm_micro_pcie_us.sv b/src/cndm/rtl/cndm_micro_pcie_us.sv index 3749d13..9bc9093 100644 --- a/src/cndm/rtl/cndm_micro_pcie_us.sv +++ b/src/cndm/rtl/cndm_micro_pcie_us.sv @@ -35,6 +35,7 @@ module cndm_micro_pcie_us #( // Structural configuration parameter PORTS = 2, + parameter logic BRD_CTRL_EN = 1'b0, parameter SYS_CLK_PER_NS_NUM = 4, parameter SYS_CLK_PER_NS_DEN = 1, @@ -109,6 +110,12 @@ module cndm_micro_pcie_us #( output wire logic [7:0] cfg_interrupt_msi_tph_st_tag, output wire logic [7:0] cfg_interrupt_msi_function_number, + /* + * Board control + */ + taxi_axis_if.src m_axis_brd_ctrl_cmd, + taxi_axis_if.snk s_axis_brd_ctrl_rsp, + /* * PTP */ @@ -561,6 +568,7 @@ cndm_micro_core #( // Structural configuration .PORTS(PORTS), + .BRD_CTRL_EN(BRD_CTRL_EN), .SYS_CLK_PER_NS_NUM(SYS_CLK_PER_NS_NUM), .SYS_CLK_PER_NS_DEN(SYS_CLK_PER_NS_DEN), @@ -599,6 +607,12 @@ core_inst ( */ .m_axis_irq(axis_irq), + /* + * Board control + */ + .m_axis_brd_ctrl_cmd(m_axis_brd_ctrl_cmd), + .s_axis_brd_ctrl_rsp(s_axis_brd_ctrl_rsp), + /* * PTP */ diff --git a/src/cndm/tb/cndm.py b/src/cndm/tb/cndm.py index ec88f1e..2476787 100644 --- a/src/cndm/tb/cndm.py +++ b/src/cndm/tb/cndm.py @@ -26,6 +26,9 @@ CNDM_CMD_OP_CFG = 0x0100 CNDM_CMD_OP_ACCESS_REG = 0x0180 CNDM_CMD_OP_PTP = 0x0190 +CNDM_CMD_OP_HWID = 0x01A0 +CNDM_CMD_OP_HWMON = 0x01B0 +CNDM_CMD_OP_PLL = 0x01C0 CNDM_CMD_OP_CREATE_EQ = 0x0200 CNDM_CMD_OP_MODIFY_EQ = 0x0201 @@ -63,6 +66,33 @@ CNDM_CMD_PTP_FLG_OFFSET_FNS = 0x00000010 CNDM_CMD_PTP_FLG_SET_PERIOD = 0x00000080 +# Board operation commands +CNDM_CMD_BRD_OP_NOP = 0x0000 + +CNDM_CMD_BRD_OP_FLASH_RD = 0x0100 +CNDM_CMD_BRD_OP_FLASH_WR = 0x0101 +CNDM_CMD_BRD_OP_FLASH_CMD = 0x0108 + +CNDM_CMD_BRD_OP_EEPROM_RD = 0x0200 +CNDM_CMD_BRD_OP_EEPROM_WR = 0x0201 + +CNDM_CMD_BRD_OP_OPTIC_RD = 0x0300 +CNDM_CMD_BRD_OP_OPTIC_WR = 0x0301 + +CNDM_CMD_BRD_OP_HWID_SN_RD = 0x0400 +CNDM_CMD_BRD_OP_HWID_VPD_RD = 0x0410 +CNDM_CMD_BRD_OP_HWID_MAC_RD = 0x0480 + +CNDM_CMD_BRD_OP_PLL_STATUS_RD = 0x0500 +CNDM_CMD_BRD_OP_PLL_TUNE_RAW_RD = 0x0502 +CNDM_CMD_BRD_OP_PLL_TUNE_RAW_WR = 0x0503 +CNDM_CMD_BRD_OP_PLL_TUNE_PPT_RD = 0x0504 +CNDM_CMD_BRD_OP_PLL_TUNE_PPT_WR = 0x0505 + +CNDM_CMD_BRD_OP_I2C_RD = 0x8100 +CNDM_CMD_BRD_OP_I2C_WR = 0x8101 + + class Eq: def __init__(self, driver, port): self.driver = driver diff --git a/src/cndm/tb/cndm_lite_pcie_us/Makefile b/src/cndm/tb/cndm_lite_pcie_us/Makefile index b56dfae..3ca0c18 100644 --- a/src/cndm/tb/cndm_lite_pcie_us/Makefile +++ b/src/cndm/tb/cndm_lite_pcie_us/Makefile @@ -38,6 +38,7 @@ export PARAM_FAMILY := "\"virtexuplus\"" # Structural configuration export PARAM_PORTS := 2 +export PARAM_BRD_CTRL_EN := 0 export PARAM_SYS_CLK_PER_NS_NUM := 4 export PARAM_SYS_CLK_PER_NS_DEN := 1 diff --git a/src/cndm/tb/cndm_lite_pcie_us/test_cndm_lite_pcie_us.py b/src/cndm/tb/cndm_lite_pcie_us/test_cndm_lite_pcie_us.py index dd23dc7..38d3f4e 100644 --- a/src/cndm/tb/cndm_lite_pcie_us/test_cndm_lite_pcie_us.py +++ b/src/cndm/tb/cndm_lite_pcie_us/test_cndm_lite_pcie_us.py @@ -20,7 +20,7 @@ import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge, FallingEdge, Timer -from cocotbext.axi import AxiStreamBus +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink from cocotbext.eth import EthMac from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice @@ -271,6 +271,10 @@ class TB: self.dev.functions[0].configure_bar(0, 2**int(dut.uut.axil_ctrl_bar.ADDR_W)) + # Board control + self.brd_ctrl_cmd = AxiStreamSink(AxiStreamBus(dut.m_axis_brd_ctrl_cmd), dut.pcie_clk, dut.pcie_rst) + self.brd_ctrl_rsp = AxiStreamSource(AxiStreamBus(dut.s_axis_brd_ctrl_rsp), dut.pcie_clk, dut.pcie_rst) + # PTP cocotb.start_soon(Clock(dut.ptp_clk, 3.102, units="ns").start()) cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) @@ -484,6 +488,7 @@ def test_cndm_lite_pcie_us(request, pcie_data_w, mac_data_w): # Structural configuration parameters['PORTS'] = 2 + parameters['BRD_CTRL_EN'] = 0 parameters['SYS_CLK_PER_NS_NUM'] = 4 parameters['SYS_CLK_PER_NS_DEN'] = 1 diff --git a/src/cndm/tb/cndm_lite_pcie_us/test_cndm_lite_pcie_us.sv b/src/cndm/tb/cndm_lite_pcie_us/test_cndm_lite_pcie_us.sv index ea7a094..7b5228c 100644 --- a/src/cndm/tb/cndm_lite_pcie_us/test_cndm_lite_pcie_us.sv +++ b/src/cndm/tb/cndm_lite_pcie_us/test_cndm_lite_pcie_us.sv @@ -34,6 +34,7 @@ module test_cndm_lite_pcie_us # // Structural configuration parameter PORTS = 2, + parameter logic BRD_CTRL_EN = 1'b0, parameter SYS_CLK_PER_NS_NUM = 4, parameter SYS_CLK_PER_NS_DEN = 1, @@ -155,6 +156,15 @@ logic [1:0] cfg_interrupt_msi_tph_type; logic [7:0] cfg_interrupt_msi_tph_st_tag; logic [7:0] cfg_interrupt_msi_function_number; +taxi_axis_if #( + .DATA_W(32), + .KEEP_EN(1), + .ID_EN(1), + .ID_W(4), + .USER_EN(1), + .USER_W(1) +) m_axis_brd_ctrl_cmd(), s_axis_brd_ctrl_rsp(); + logic ptp_rst; logic ptp_clk; logic ptp_sample_clk; @@ -328,6 +338,7 @@ cndm_lite_pcie_us #( // Structural configuration .PORTS(PORTS), + .BRD_CTRL_EN(BRD_CTRL_EN), .SYS_CLK_PER_NS_NUM(SYS_CLK_PER_NS_NUM), .SYS_CLK_PER_NS_DEN(SYS_CLK_PER_NS_DEN), @@ -402,6 +413,12 @@ uut ( .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + /* + * Board control + */ + .m_axis_brd_ctrl_cmd(m_axis_brd_ctrl_cmd), + .s_axis_brd_ctrl_rsp(s_axis_brd_ctrl_rsp), + /* * PTP */ diff --git a/src/cndm/tb/cndm_micro_pcie_us/Makefile b/src/cndm/tb/cndm_micro_pcie_us/Makefile index 09c3468..1ea80d6 100644 --- a/src/cndm/tb/cndm_micro_pcie_us/Makefile +++ b/src/cndm/tb/cndm_micro_pcie_us/Makefile @@ -38,6 +38,7 @@ export PARAM_FAMILY := "\"virtexuplus\"" # Structural configuration export PARAM_PORTS := 2 +export PARAM_BRD_CTRL_EN := 0 export PARAM_SYS_CLK_PER_NS_NUM := 4 export PARAM_SYS_CLK_PER_NS_DEN := 1 diff --git a/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py b/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py index 7f24b9e..5ab5686 100644 --- a/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py +++ b/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.py @@ -20,7 +20,7 @@ import cocotb from cocotb.clock import Clock from cocotb.triggers import RisingEdge, FallingEdge, Timer -from cocotbext.axi import AxiStreamBus +from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink from cocotbext.eth import EthMac from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice @@ -271,6 +271,10 @@ class TB: self.dev.functions[0].configure_bar(0, 2**int(dut.uut.axil_ctrl_bar.ADDR_W)) + # Board control + self.brd_ctrl_cmd = AxiStreamSink(AxiStreamBus(dut.m_axis_brd_ctrl_cmd), dut.pcie_clk, dut.pcie_rst) + self.brd_ctrl_rsp = AxiStreamSource(AxiStreamBus(dut.s_axis_brd_ctrl_rsp), dut.pcie_clk, dut.pcie_rst) + # PTP cocotb.start_soon(Clock(dut.ptp_clk, 3.102, units="ns").start()) cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start()) @@ -483,6 +487,7 @@ def test_cndm_micro_pcie_us(request, pcie_data_w, mac_data_w): # Structural configuration parameters['PORTS'] = 2 + parameters['BRD_CTRL_EN'] = 0 parameters['SYS_CLK_PER_NS_NUM'] = 4 parameters['SYS_CLK_PER_NS_DEN'] = 1 diff --git a/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv b/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv index fff8fe5..1270de8 100644 --- a/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv +++ b/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv @@ -34,6 +34,7 @@ module test_cndm_micro_pcie_us # // Structural configuration parameter PORTS = 2, + parameter logic BRD_CTRL_EN = 1'b0, parameter SYS_CLK_PER_NS_NUM = 4, parameter SYS_CLK_PER_NS_DEN = 1, @@ -155,6 +156,15 @@ logic [1:0] cfg_interrupt_msi_tph_type; logic [7:0] cfg_interrupt_msi_tph_st_tag; logic [7:0] cfg_interrupt_msi_function_number; +taxi_axis_if #( + .DATA_W(32), + .KEEP_EN(1), + .ID_EN(1), + .ID_W(4), + .USER_EN(1), + .USER_W(1) +) m_axis_brd_ctrl_cmd(), s_axis_brd_ctrl_rsp(); + logic ptp_rst; logic ptp_clk; logic ptp_sample_clk; @@ -328,6 +338,7 @@ cndm_micro_pcie_us #( // Structural configuration .PORTS(PORTS), + .BRD_CTRL_EN(BRD_CTRL_EN), .SYS_CLK_PER_NS_NUM(SYS_CLK_PER_NS_NUM), .SYS_CLK_PER_NS_DEN(SYS_CLK_PER_NS_DEN), @@ -402,6 +413,12 @@ uut ( .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + /* + * Board control + */ + .m_axis_brd_ctrl_cmd(m_axis_brd_ctrl_cmd), + .s_axis_brd_ctrl_rsp(s_axis_brd_ctrl_rsp), + /* * PTP */