diff --git a/src/cndm/rtl/cndm_micro_core.sv b/src/cndm/rtl/cndm_micro_core.sv index 9fc0e18..9bbfee6 100644 --- a/src/cndm/rtl/cndm_micro_core.sv +++ b/src/cndm/rtl/cndm_micro_core.sv @@ -304,9 +304,11 @@ cmd_mbox_inst ( // datapath manager +localparam APB_DP_ADDR_W = 16+$clog2(PORTS+PORT_OFFSET_DP); + taxi_apb_if #( .DATA_W(32), - .ADDR_W(16+$clog2(PORTS+PORT_OFFSET_DP)) + .ADDR_W(APB_DP_ADDR_W) ) apb_dp_ctrl(); @@ -346,7 +348,7 @@ apb_port_dp_ctrl[PORT_OFFSET_DP+PORTS](); taxi_apb_interconnect #( .M_CNT($size(apb_port_dp_ctrl)), - .ADDR_W(apb_dp_ctrl.ADDR_W), + .ADDR_W(APB_DP_ADDR_W), .M_REGIONS(1), .M_BASE_ADDR('0), .M_ADDR_W({$size(apb_port_dp_ctrl){{1{32'd16}}}}), diff --git a/src/cndm/rtl/cndm_micro_desc_rd.sv b/src/cndm/rtl/cndm_micro_desc_rd.sv index ea77771..af46695 100644 --- a/src/cndm/rtl/cndm_micro_desc_rd.sv +++ b/src/cndm/rtl/cndm_micro_desc_rd.sv @@ -41,7 +41,7 @@ module cndm_micro_desc_rd #( taxi_dma_desc_if.sts_snk dma_rd_desc_sts, taxi_dma_ram_if.wr_slv dma_ram_wr, - input wire logic [1:0] desc_req, + taxi_axis_if.snk s_axis_desc_req, taxi_axis_if.src m_axis_desc ); @@ -132,7 +132,9 @@ typedef enum logic [1:0] { state_t state_reg = STATE_IDLE; -logic [1:0] desc_req_reg = '0; +logic s_axis_desc_req_tready_reg = 1'b0; + +assign s_axis_desc_req.tready = s_axis_desc_req_tready_reg; always_ff @(posedge clk) begin dma_rd_desc_req.req_src_sel <= '0; @@ -163,25 +165,18 @@ always_ff @(posedge clk) begin wq_req_valid_reg <= wq_req_valid_reg && !wq_req_ready; wq_rsp_ready_reg <= 1'b0; - desc_req_reg <= desc_req_reg | desc_req; + s_axis_desc_req_tready_reg <= 1'b0; case (state_reg) STATE_IDLE: begin - wq_req_wqn_reg <= 0; + s_axis_desc_req_tready_reg <= 1'b1; - if (desc_req_reg[1]) begin - desc_req_reg[1] <= 1'b0; - wq_req_wqn_reg <= 1; - wq_req_qtype_reg <= QTYPE_RQ; + if (s_axis_desc_req.tvalid && s_axis_desc_req.tready) begin + s_axis_desc_req_tready_reg <= 1'b0; + wq_req_wqn_reg <= s_axis_desc_req.tdest; + wq_req_qtype_reg <= s_axis_desc_req.tuser; wq_req_valid_reg <= 1'b1; - dma_desc.req_id <= 1'b1; - state_reg <= STATE_QUERY_WQ; - end else if (desc_req_reg[0]) begin - desc_req_reg[0] <= 1'b0; - wq_req_wqn_reg <= 0; - wq_req_qtype_reg <= QTYPE_SQ; - wq_req_valid_reg <= 1'b1; - dma_desc.req_id <= 1'b0; + dma_desc.req_id <= s_axis_desc_req.tid; state_reg <= STATE_QUERY_WQ; end else begin state_reg <= STATE_IDLE; diff --git a/src/cndm/rtl/cndm_micro_dp_mgr.sv b/src/cndm/rtl/cndm_micro_dp_mgr.sv index 4ee8d70..5958578 100644 --- a/src/cndm/rtl/cndm_micro_dp_mgr.sv +++ b/src/cndm/rtl/cndm_micro_dp_mgr.sv @@ -26,7 +26,12 @@ module cndm_micro_dp_mgr # parameter PTP_BASE_ADDR_DP = 0, parameter PORT_BASE_ADDR_DP = 0, - parameter PORT_BASE_ADDR_HOST = 0 + parameter PORT_BASE_ADDR_HOST = 0, + parameter PORT_STRIDE = 'h10000, + parameter WQ_REG_STRIDE = 32, + parameter QM_OFFSET = 'h0000, + parameter CQM_OFFSET = 'h4000, + parameter PORT_CTRL_OFFSET = 'h8000 ) ( input wire logic clk, @@ -103,6 +108,7 @@ typedef enum logic [4:0] { STATE_CREATE_Q_SET_BASE_H, STATE_CREATE_Q_SET_DQN, STATE_CREATE_Q_ENABLE, + STATE_CREATE_Q_PORT_CONFIG, STATE_DESTROY_Q_DISABLE, STATE_PTP_READ_1, STATE_PTP_READ_2, @@ -282,48 +288,48 @@ always_comb begin begin cnt_next = 2**CQN_W-1; qtype_next = QTYPE_CQ; - dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h8000) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); - host_ptr_next = 32'({port_reg, 16'd0} | 'h8000) + PORT_BASE_ADDR_HOST; + dp_ptr_next = DP_APB_ADDR_W'((port_reg * PORT_STRIDE) + CQM_OFFSET + PORT_BASE_ADDR_DP); + host_ptr_next = (port_reg * PORT_STRIDE) + CQM_OFFSET + PORT_BASE_ADDR_HOST; end CMD_OP_MODIFY_CQ, CMD_OP_QUERY_CQ, CMD_OP_DESTROY_CQ: begin qtype_next = QTYPE_CQ; - dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h8000 | {qn_reg, 5'd00}) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); - host_ptr_next = 32'({port_reg, 16'd0} | 'h8000 | {qn_reg, 5'd00}) + PORT_BASE_ADDR_HOST; + dp_ptr_next = DP_APB_ADDR_W'((port_reg * PORT_STRIDE) + CQM_OFFSET + (qn_reg * WQ_REG_STRIDE) + PORT_BASE_ADDR_DP); + host_ptr_next = (port_reg * PORT_STRIDE) + CQM_OFFSET + (qn_reg * WQ_REG_STRIDE) + PORT_BASE_ADDR_HOST; end // SQ CMD_OP_CREATE_SQ: begin - cnt_next = 0; + cnt_next = 2**WQN_W-1; qtype_next = QTYPE_SQ; - dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0000) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); - host_ptr_next = 32'({port_reg, 16'd0} | 'h0000) + PORT_BASE_ADDR_HOST; + dp_ptr_next = DP_APB_ADDR_W'((port_reg * PORT_STRIDE) + QM_OFFSET + PORT_BASE_ADDR_DP); + host_ptr_next = (port_reg * PORT_STRIDE) + QM_OFFSET + PORT_BASE_ADDR_HOST; end CMD_OP_MODIFY_SQ, CMD_OP_QUERY_SQ, CMD_OP_DESTROY_SQ: begin qtype_next = QTYPE_SQ; - dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0000) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); - host_ptr_next = 32'({port_reg, 16'd0} | 'h0000) + PORT_BASE_ADDR_HOST; + dp_ptr_next = DP_APB_ADDR_W'((port_reg * PORT_STRIDE) + QM_OFFSET + (qn_reg * WQ_REG_STRIDE) + PORT_BASE_ADDR_DP); + host_ptr_next = (port_reg * PORT_STRIDE) + QM_OFFSET + (qn_reg * WQ_REG_STRIDE) + PORT_BASE_ADDR_HOST; end // RQ CMD_OP_CREATE_RQ: begin - cnt_next = 0; + cnt_next = 2**WQN_W-1; qtype_next = QTYPE_RQ; - dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0020) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); - host_ptr_next = 32'({port_reg, 16'd0} | 'h0020) + PORT_BASE_ADDR_HOST; + dp_ptr_next = DP_APB_ADDR_W'((port_reg * PORT_STRIDE) + QM_OFFSET + (qn_reg * WQ_REG_STRIDE) + PORT_BASE_ADDR_DP); + host_ptr_next = (port_reg * PORT_STRIDE) + QM_OFFSET + (qn_reg * WQ_REG_STRIDE) + PORT_BASE_ADDR_HOST; end CMD_OP_MODIFY_RQ, CMD_OP_QUERY_RQ, CMD_OP_DESTROY_RQ: begin qtype_next = QTYPE_RQ; - dp_ptr_next = DP_APB_ADDR_W'({port_reg, 16'd0} | 'h0020) + DP_APB_ADDR_W'(PORT_BASE_ADDR_DP); - host_ptr_next = 32'({port_reg, 16'd0} | 'h0020) + PORT_BASE_ADDR_HOST; + dp_ptr_next = DP_APB_ADDR_W'((port_reg * PORT_STRIDE) + QM_OFFSET + PORT_BASE_ADDR_DP); + host_ptr_next = (port_reg * PORT_STRIDE) + QM_OFFSET + PORT_BASE_ADDR_HOST; end default: begin end endcase @@ -488,8 +494,8 @@ always_comb begin end else begin // queue is active qn_next = qn_reg + 1; - dp_ptr_next = dp_ptr_reg + 'h20; - host_ptr_next = host_ptr_reg + 'h20; + dp_ptr_next = dp_ptr_reg + WQ_REG_STRIDE; + host_ptr_next = host_ptr_reg + WQ_REG_STRIDE; if (cnt_reg == 0) begin // no more queues m_axis_rsp_tdata_next = '0; // TODO @@ -614,9 +620,27 @@ always_comb begin m_apb_dp_ctrl_psel_next = 1'b1; m_apb_dp_ctrl_pwrite_next = 1'b1; m_apb_dp_ctrl_pwdata_next = '0; - m_apb_dp_ctrl_pwdata_next[19:16] = cmd_ram_rd_data[3:0]; - m_apb_dp_ctrl_pwdata_next[23:20] = 4'(qtype_reg); - m_apb_dp_ctrl_pwdata_next[0] = 1'b1; + m_apb_dp_ctrl_pwdata_next[23:20] = 4'(qtype_reg); // type + m_apb_dp_ctrl_pwdata_next[19:16] = cmd_ram_rd_data[3:0]; // size + m_apb_dp_ctrl_pwdata_next[0] = 1'b1; // enable + m_apb_dp_ctrl_pstrb_next = '1; + + state_next = STATE_CREATE_Q_PORT_CONFIG; + end else begin + state_next = STATE_CREATE_Q_ENABLE; + end + end + STATE_CREATE_Q_PORT_CONFIG: begin + // set up port + if (!m_apb_dp_ctrl_psel_reg) begin + if (qtype_reg == QTYPE_SQ) begin + m_apb_dp_ctrl_paddr_next = DP_APB_ADDR_W'(PORT_BASE_ADDR_DP + (port_reg * PORT_STRIDE) + PORT_CTRL_OFFSET + 'h0010); + end else begin + m_apb_dp_ctrl_paddr_next = DP_APB_ADDR_W'(PORT_BASE_ADDR_DP + (port_reg * PORT_STRIDE) + PORT_CTRL_OFFSET + 'h0020); + end + m_apb_dp_ctrl_psel_next = 1'b1; + m_apb_dp_ctrl_pwrite_next = qtype_reg == QTYPE_SQ || qtype_reg == QTYPE_RQ; + m_apb_dp_ctrl_pwdata_next = 32'(qn_reg); m_apb_dp_ctrl_pstrb_next = '1; m_axis_rsp_tdata_next = '0; // TODO @@ -625,7 +649,7 @@ always_comb begin state_next = STATE_SEND_RSP; end else begin - state_next = STATE_CREATE_Q_ENABLE; + state_next = STATE_CREATE_Q_PORT_CONFIG; end end STATE_DESTROY_Q_DISABLE: begin diff --git a/src/cndm/rtl/cndm_micro_port.sv b/src/cndm/rtl/cndm_micro_port.sv index d20b5ad..196af63 100644 --- a/src/cndm/rtl/cndm_micro_port.sv +++ b/src/cndm/rtl/cndm_micro_port.sv @@ -74,15 +74,20 @@ module cndm_micro_port #( localparam AXIL_ADDR_W = s_axil_ctrl_wr.ADDR_W; localparam AXIL_DATA_W = s_axil_ctrl_wr.DATA_W; +localparam APB_ADDR_W = s_apb_dp_ctrl.ADDR_W; +localparam APB_DATA_W = s_apb_dp_ctrl.DATA_W; + localparam RAM_SEGS = dma_ram_wr.SEGS; localparam RAM_SEG_ADDR_W = dma_ram_wr.SEG_ADDR_W; localparam RAM_SEG_DATA_W = dma_ram_wr.SEG_DATA_W; localparam RAM_SEG_BE_W = dma_ram_wr.SEG_BE_W; localparam RAM_SEL_W = dma_ram_wr.SEL_W; +localparam PORT_ADDR_W = 14; + taxi_axil_if #( .DATA_W(s_axil_ctrl_wr.DATA_W), - .ADDR_W(15), + .ADDR_W(PORT_ADDR_W), .STRB_W(s_axil_ctrl_wr.STRB_W), .AWUSER_EN(s_axil_ctrl_wr.AWUSER_EN), .AWUSER_W(s_axil_ctrl_wr.AWUSER_W), @@ -102,7 +107,7 @@ taxi_axil_interconnect_1s #( .ADDR_W(s_axil_ctrl_wr.ADDR_W), .M_REGIONS(1), .M_BASE_ADDR('0), - .M_ADDR_W({$size(axil_ctrl){{1{32'd15}}}}), + .M_ADDR_W({$size(axil_ctrl){{1{32'd14}}}}), .M_SECURE({$size(axil_ctrl){1'b0}}) ) port_intercon_inst ( @@ -124,16 +129,16 @@ port_intercon_inst ( taxi_apb_if #( .DATA_W(32), - .ADDR_W(15) + .ADDR_W(PORT_ADDR_W) ) -apb_dp_ctrl[2](); +apb_dp_ctrl[3](); taxi_apb_interconnect #( .M_CNT($size(apb_dp_ctrl)), .ADDR_W(s_apb_dp_ctrl.ADDR_W), .M_REGIONS(1), .M_BASE_ADDR('0), - .M_ADDR_W({$size(apb_dp_ctrl){{1{32'd15}}}}), + .M_ADDR_W({$size(apb_dp_ctrl){{1{32'd14}}}}), .M_SECURE({$size(apb_dp_ctrl){1'b0}}) ) port_dp_intercon_inst ( @@ -151,6 +156,47 @@ port_dp_intercon_inst ( .m_apb(apb_dp_ctrl) ); +// Port control registers + +logic apb_dp_ctrl_pready_reg = 1'b0; +logic [APB_DATA_W-1:0] apb_dp_ctrl_prdata_reg = '0; + +assign apb_dp_ctrl[2].pready = apb_dp_ctrl_pready_reg; +assign apb_dp_ctrl[2].prdata = apb_dp_ctrl_prdata_reg; +assign apb_dp_ctrl[2].pslverr = 1'b0; +assign apb_dp_ctrl[2].pruser = '0; +assign apb_dp_ctrl[2].pbuser = '0; + +logic [WQN_W-1:0] tx_queue_reg = '0; +logic [WQN_W-1:0] rx_queue_reg = '0; + +always_ff @(posedge clk) begin + apb_dp_ctrl_pready_reg <= 1'b0; + + if (apb_dp_ctrl[2].penable && apb_dp_ctrl[2].psel && !apb_dp_ctrl_pready_reg) begin + apb_dp_ctrl_pready_reg <= 1'b1; + apb_dp_ctrl_prdata_reg <= '0; + + if (apb_dp_ctrl[2].pwrite) begin + case (8'({apb_dp_ctrl[2].paddr >> 2, 2'b00})) + 8'h10: tx_queue_reg <= WQN_W'(apb_dp_ctrl[2].pwdata); + 8'h20: rx_queue_reg <= WQN_W'(apb_dp_ctrl[2].pwdata); + default: begin end + endcase + end + + case (8'({apb_dp_ctrl[2].paddr >> 2, 2'b00})) + 8'h10: apb_dp_ctrl_prdata_reg <= 32'(tx_queue_reg); + 8'h20: apb_dp_ctrl_prdata_reg <= 32'(rx_queue_reg); + default: begin end + endcase + end + + if (rst) begin + apb_dp_ctrl_pready_reg <= 1'b0; + end +end + taxi_dma_desc_if #( .SRC_ADDR_W(dma_rd_desc_req.SRC_ADDR_W), .SRC_SEL_EN(dma_rd_desc_req.SRC_SEL_EN), @@ -267,7 +313,50 @@ wr_dma_mux_inst ( ); // descriptor fetch -wire [1:0] desc_req; +taxi_axis_if #( + .DATA_W(8), + .KEEP_EN(0), + .LAST_EN(1), + .ID_EN(1), + .ID_W(1), + .DEST_EN(1), + .DEST_W(WQN_W), + .USER_EN(1), + .USER_W(3) +) axis_desc_req(); + +taxi_axis_if #( + .DATA_W(8), + .KEEP_EN(0), + .LAST_EN(1), + .ID_EN(1), + .ID_W(1), + .DEST_EN(1), + .DEST_W(WQN_W), + .USER_EN(1), + .USER_W(3) +) axis_desc_req_txrx[2](); + +taxi_axis_arb_mux #( + .S_COUNT(2), + .UPDATE_TID(1), + .ARB_ROUND_ROBIN(0), + .ARB_LSB_HIGH_PRIO(0) // prefer RX requests +) +desc_req_mux_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4-Stream input (sink) + */ + .s_axis(axis_desc_req_txrx), + + /* + * AXI4-Stream output (source) + */ + .m_axis(axis_desc_req) +); taxi_axis_if #( .DATA_W(16*8), @@ -307,7 +396,7 @@ desc_rd_inst ( .dma_rd_desc_sts(dma_rd_desc_int[0]), .dma_ram_wr(dma_ram_wr_int[0]), - .desc_req(desc_req), + .s_axis_desc_req(axis_desc_req), .m_axis_desc(axis_desc) ); @@ -533,6 +622,8 @@ tx_cpl_fifo ( ); cndm_micro_tx #( + .WQN_W(WQN_W), + .PTP_TS_EN(PTP_TS_EN), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD) ) @@ -554,7 +645,8 @@ tx_inst ( .dma_rd_desc_sts(dma_rd_desc_int[1]), .dma_ram_wr(dma_ram_wr_int[1]), - .desc_req(desc_req[0]), + .tx_queue(tx_queue_reg), + .m_axis_desc_req(axis_desc_req_txrx[0]), .s_axis_desc(axis_desc_txrx[0]), .tx_data(mac_tx_int), .tx_cpl(mac_tx_cpl_int), @@ -617,6 +709,8 @@ rx_fifo ( ); cndm_micro_rx #( + .WQN_W(WQN_W), + .PTP_TS_EN(PTP_TS_EN), .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD) ) @@ -639,7 +733,8 @@ rx_inst ( .dma_ram_rd(dma_ram_rd_int[1]), .rx_data(mac_rx_int), - .desc_req(desc_req[1]), + .rx_queue(rx_queue_reg), + .m_axis_desc_req(axis_desc_req_txrx[1]), .s_axis_desc(axis_desc_txrx[1]), .m_axis_cpl(axis_cpl_txrx[1]) ); diff --git a/src/cndm/rtl/cndm_micro_rx.sv b/src/cndm/rtl/cndm_micro_rx.sv index 7acbbee..1d144e6 100644 --- a/src/cndm/rtl/cndm_micro_rx.sv +++ b/src/cndm/rtl/cndm_micro_rx.sv @@ -16,35 +16,45 @@ Authors: * Corundum-micro receive datapath */ module cndm_micro_rx #( + parameter WQN_W = 5, + parameter logic PTP_TS_EN = 1'b1, parameter logic PTP_TS_FMT_TOD = 1'b0 ) ( - input wire logic clk, - input wire logic rst, + input wire logic clk, + input wire logic rst, /* * PTP */ - input wire logic ptp_clk = 1'b0, - input wire logic ptp_rst = 1'b0, - input wire logic ptp_td_sdi = 1'b0, + input wire logic ptp_clk = 1'b0, + input wire logic ptp_rst = 1'b0, + input wire logic ptp_td_sdi = 1'b0, /* * DMA */ - taxi_dma_desc_if.req_src dma_wr_desc_req, - taxi_dma_desc_if.sts_snk dma_wr_desc_sts, - taxi_dma_ram_if.rd_slv dma_ram_rd, + taxi_dma_desc_if.req_src dma_wr_desc_req, + taxi_dma_desc_if.sts_snk dma_wr_desc_sts, + taxi_dma_ram_if.rd_slv dma_ram_rd, - taxi_axis_if.snk rx_data, - output wire logic desc_req, - taxi_axis_if.snk s_axis_desc, - taxi_axis_if.src m_axis_cpl + taxi_axis_if.snk rx_data, + input wire logic [WQN_W-1:0] rx_queue, + taxi_axis_if.src m_axis_desc_req, + taxi_axis_if.snk s_axis_desc, + taxi_axis_if.src m_axis_cpl ); localparam RAM_ADDR_W = 16; +typedef enum logic [2:0] { + QTYPE_EQ, + QTYPE_CQ, + QTYPE_SQ, + QTYPE_RQ +} qtype_t; + taxi_dma_desc_if #( .SRC_ADDR_W(RAM_ADDR_W), .SRC_SEL_EN(1'b0), @@ -70,9 +80,18 @@ typedef enum logic [1:0] { state_t state_reg = STATE_IDLE; -logic desc_req_reg = 1'b0; +logic m_axis_desc_req_tvalid_reg = 1'b0; +logic [WQN_W-1:0] m_axis_desc_req_tdest_reg = '0; +logic [2:0] m_axis_desc_req_tuser_reg = '0; -assign desc_req = desc_req_reg; +assign m_axis_desc_req.tdata = '0; +assign m_axis_desc_req.tkeep = '0; +assign m_axis_desc_req.tstrb = '0; +assign m_axis_desc_req.tlast = 1'b1; +assign m_axis_desc_req.tvalid = m_axis_desc_req_tvalid_reg; +assign m_axis_desc_req.tid = '0; +assign m_axis_desc_req.tdest = rx_queue; +assign m_axis_desc_req.tuser = m_axis_desc_req_tuser_reg; wire [95:0] rx_ptp_ts; wire rx_ptp_ts_valid; @@ -153,7 +172,7 @@ end else begin end always_ff @(posedge clk) begin - desc_req_reg <= 1'b0; + m_axis_desc_req_tvalid_reg <= m_axis_desc_req_tvalid_reg && !m_axis_desc_req.tready; s_axis_desc.tready <= 1'b0; @@ -205,7 +224,9 @@ always_ff @(posedge clk) begin dma_wr_desc_req.req_len <= 20'(dma_desc.sts_len); m_axis_cpl.tdata[47:32] <= 16'(dma_desc.sts_len); if (dma_desc.sts_valid) begin - desc_req_reg <= 1'b1; + m_axis_desc_req_tvalid_reg <= 1'b1; + m_axis_desc_req_tdest_reg <= rx_queue; + m_axis_desc_req_tuser_reg <= QTYPE_RQ; state_reg <= STATE_READ_DESC; end end diff --git a/src/cndm/rtl/cndm_micro_tx.sv b/src/cndm/rtl/cndm_micro_tx.sv index e7a491c..87cbb72 100644 --- a/src/cndm/rtl/cndm_micro_tx.sv +++ b/src/cndm/rtl/cndm_micro_tx.sv @@ -16,36 +16,46 @@ Authors: * Corundum-micro transmit datapath */ module cndm_micro_tx #( + parameter WQN_W = 5, + parameter logic PTP_TS_EN = 1'b1, parameter logic PTP_TS_FMT_TOD = 1'b0 ) ( - input wire logic clk, - input wire logic rst, + input wire logic clk, + input wire logic rst, /* * PTP */ - input wire logic ptp_clk = 1'b0, - input wire logic ptp_rst = 1'b0, - input wire logic ptp_td_sdi = 1'b0, + input wire logic ptp_clk = 1'b0, + input wire logic ptp_rst = 1'b0, + input wire logic ptp_td_sdi = 1'b0, /* * DMA */ - taxi_dma_desc_if.req_src dma_rd_desc_req, - taxi_dma_desc_if.sts_snk dma_rd_desc_sts, - taxi_dma_ram_if.wr_slv dma_ram_wr, + taxi_dma_desc_if.req_src dma_rd_desc_req, + taxi_dma_desc_if.sts_snk dma_rd_desc_sts, + taxi_dma_ram_if.wr_slv dma_ram_wr, - output wire logic desc_req, - taxi_axis_if.snk s_axis_desc, - taxi_axis_if.src tx_data, - taxi_axis_if.snk tx_cpl, - taxi_axis_if.src m_axis_cpl + input wire logic [WQN_W-1:0] tx_queue, + taxi_axis_if.src m_axis_desc_req, + taxi_axis_if.snk s_axis_desc, + taxi_axis_if.src tx_data, + taxi_axis_if.snk tx_cpl, + taxi_axis_if.src m_axis_cpl ); localparam RAM_ADDR_W = 16; +typedef enum logic [2:0] { + QTYPE_EQ, + QTYPE_CQ, + QTYPE_SQ, + QTYPE_RQ +} qtype_t; + taxi_dma_desc_if #( .SRC_ADDR_W(RAM_ADDR_W), .SRC_SEL_EN(1'b0), @@ -71,9 +81,18 @@ typedef enum logic [1:0] { state_t state_reg = STATE_IDLE; -logic desc_req_reg = 1'b0; +logic m_axis_desc_req_tvalid_reg = 1'b0; +logic [WQN_W-1:0] m_axis_desc_req_tdest_reg = '0; +logic [2:0] m_axis_desc_req_tuser_reg = '0; -assign desc_req = desc_req_reg; +assign m_axis_desc_req.tdata = '0; +assign m_axis_desc_req.tkeep = '0; +assign m_axis_desc_req.tstrb = '0; +assign m_axis_desc_req.tlast = 1'b1; +assign m_axis_desc_req.tvalid = m_axis_desc_req_tvalid_reg; +assign m_axis_desc_req.tid = '0; +assign m_axis_desc_req.tdest = m_axis_desc_req_tdest_reg; +assign m_axis_desc_req.tuser = m_axis_desc_req_tuser_reg; wire [95:0] tx_cpl_ptp_ts; wire tx_cpl_valid; @@ -138,7 +157,7 @@ end else begin end always_ff @(posedge clk) begin - desc_req_reg <= 1'b0; + m_axis_desc_req_tvalid_reg <= m_axis_desc_req_tvalid_reg && !m_axis_desc_req.tready; s_axis_desc.tready <= 1'b0; @@ -175,7 +194,10 @@ always_ff @(posedge clk) begin case (state_reg) STATE_IDLE: begin - desc_req_reg <= 1'b1; + m_axis_desc_req_tvalid_reg <= 1'b1; + m_axis_desc_req_tdest_reg <= tx_queue; + m_axis_desc_req_tuser_reg <= QTYPE_SQ; + state_reg <= STATE_READ_DESC; end STATE_READ_DESC: begin