diff --git a/src/eth/example/HTG9200/fpga/README.md b/src/eth/example/HTG9200/fpga/README.md
index 0671294..93fc0d8 100644
--- a/src/eth/example/HTG9200/fpga/README.md
+++ b/src/eth/example/HTG9200/fpga/README.md
@@ -15,7 +15,6 @@ The design places looped-back MACs on the Ethernet ports, as well as XFCP on the
 
 *  FPGA: xcvu9p-flgb2104-2-e
 *  USB UART: Silicon Labs CP2103
-*  1000BASE-T PHY: TI DP83867IRPAP via RGMII
 
 ## Licensing
 
diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga.sv b/src/eth/example/HTG9200/fpga/rtl/fpga.sv
index b36744a..d28a2bb 100644
--- a/src/eth/example/HTG9200/fpga/rtl/fpga.sv
+++ b/src/eth/example/HTG9200/fpga/rtl/fpga.sv
@@ -315,7 +315,28 @@ assign i2c_sda_i = i2c_main_sda;
 assign i2c_main_sda = i2c_sda_o ? 1'bz : 1'b0;
 assign i2c_main_rst_n = 1'b1;
 
-fpga_core
+localparam PORT_CNT = 9;
+localparam GTY_QUAD_CNT = PORT_CNT;
+localparam GTY_CNT = GTY_QUAD_CNT*4;
+localparam GTY_CLK_CNT = GTY_QUAD_CNT;
+
+assign clk_gty2_fdec = 1'b0;
+assign clk_gty2_finc = 1'b0;
+assign clk_gty2_oe_n = 1'b0;
+assign clk_gty2_sync_n = 1'b1;
+assign clk_gty2_rst_n = !rst_125mhz_int;
+
+wire eth_pll_locked = clk_gty2_lol_n;
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .PORT_CNT(PORT_CNT),
+    .GTY_QUAD_CNT(GTY_QUAD_CNT),
+    .GTY_CNT(GTY_CNT),
+    .GTY_CLK_CNT(GTY_CLK_CNT)
+)
 core_inst (
     /*
      * Clock: 125MHz
@@ -339,17 +360,6 @@ core_inst (
     .i2c_sda_i(i2c_sda_i),
     .i2c_sda_o(i2c_sda_o),
 
-    /*
-     * PLL
-     */
-    .clk_gty2_fdec(clk_gty2_fdec),
-    .clk_gty2_finc(clk_gty2_finc),
-    .clk_gty2_intr_n(clk_gty2_intr_n),
-    .clk_gty2_lol_n(clk_gty2_lol_n),
-    .clk_gty2_oe_n(clk_gty2_oe_n),
-    .clk_gty2_sync_n(clk_gty2_sync_n),
-    .clk_gty2_rst_n(clk_gty2_rst_n),
-
     /*
      * UART: 921600 bps, 8N1
      */
@@ -363,6 +373,8 @@ core_inst (
     /*
      * Ethernet: QSFP28
      */
+    .eth_pll_locked(eth_pll_locked),
+
     .eth_gty_tx_p({qsfp_9_tx_p, qsfp_8_tx_p, qsfp_7_tx_p, qsfp_6_tx_p, qsfp_5_tx_p, qsfp_4_tx_p, qsfp_3_tx_p, qsfp_2_tx_p, qsfp_1_tx_p}),
     .eth_gty_tx_n({qsfp_9_tx_n, qsfp_8_tx_n, qsfp_7_tx_n, qsfp_6_tx_n, qsfp_5_tx_n, qsfp_4_tx_n, qsfp_3_tx_n, qsfp_2_tx_n, qsfp_1_tx_n}),
     .eth_gty_rx_p({qsfp_9_rx_p, qsfp_8_rx_p, qsfp_7_rx_p, qsfp_6_rx_p, qsfp_5_rx_p, qsfp_4_rx_p, qsfp_3_rx_p, qsfp_2_rx_p, qsfp_1_rx_p}),
diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv
index 6bc9212..fc4b1b4 100644
--- a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv
+++ b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv
@@ -48,17 +48,6 @@ module fpga_core #
     input  wire logic                    i2c_sda_i,
     output wire logic                    i2c_sda_o,
 
-    /*
-     * PLL
-     */
-    output wire logic                    clk_gty2_fdec,
-    output wire logic                    clk_gty2_finc,
-    input  wire logic                    clk_gty2_intr_n,
-    input  wire logic                    clk_gty2_lol_n,
-    output wire logic                    clk_gty2_oe_n,
-    output wire logic                    clk_gty2_sync_n,
-    output wire logic                    clk_gty2_rst_n,
-
     /*
      * UART: 921600 bps, 8N1
      */
@@ -72,6 +61,8 @@ module fpga_core #
     /*
      * Ethernet: QSFP28
      */
+    input  wire logic                    eth_pll_locked,
+
     output wire logic [GTY_CNT-1:0]      eth_gty_tx_p,
     output wire logic [GTY_CNT-1:0]      eth_gty_tx_n,
     input  wire logic [GTY_CNT-1:0]      eth_gty_rx_p,
@@ -166,12 +157,6 @@ si5341_i2c_init_inst (
     .start(1'b1)
 );
 
-assign clk_gty2_fdec = 1'b0;
-assign clk_gty2_finc = 1'b0;
-assign clk_gty2_oe_n = 1'b0;
-assign clk_gty2_sync_n = 1'b1;
-assign clk_gty2_rst_n = !rst_125mhz;
-
 // XFCP
 taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
 
@@ -301,7 +286,7 @@ xfcp_mod_i2c_inst (
 );
 
 // Ethernet
-wire eth_reset = SIM ? 1'b0 : (si5341_i2c_busy || !clk_gty2_lol_n);
+wire eth_reset = SIM ? 1'b0 : (si5341_i2c_busy || !eth_pll_locked);
 assign eth_port_resetl = {PORT_CNT{~eth_reset}};
 
 wire [GTY_CNT-1:0] eth_gty_tx_clk;
diff --git a/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py
index 3a1c49c..f388680 100644
--- a/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py
+++ b/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py
@@ -86,9 +86,8 @@ class TB:
 
         dut.i2c_scl_i.setimmediatevalue(1)
         dut.i2c_sda_i.setimmediatevalue(1)
-        dut.clk_gty2_intr_n.setimmediatevalue(1)
-        dut.clk_gty2_lol_n.setimmediatevalue(1)
         dut.sw.setimmediatevalue(0)
+        dut.eth_pll_locked.setimmediatevalue(1)
         dut.eth_port_modprsl.setimmediatevalue(0)
         dut.eth_port_intl.setimmediatevalue(0)