From cf44abae0de591039d088295f450c55ab8b8b5b1 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 25 Feb 2025 17:13:10 -0800 Subject: [PATCH] axis: Use signal sync module for async FIFO output pause Signed-off-by: Alex Forencich --- rtl/axis/taxi_axis_async_fifo.f | 1 + rtl/axis/taxi_axis_async_fifo.sv | 44 +++++++++++++++-------------- syn/vivado/taxi_axis_async_fifo.tcl | 17 ----------- 3 files changed, 24 insertions(+), 38 deletions(-) diff --git a/rtl/axis/taxi_axis_async_fifo.f b/rtl/axis/taxi_axis_async_fifo.f index 7d2bef6..91a82f3 100644 --- a/rtl/axis/taxi_axis_async_fifo.f +++ b/rtl/axis/taxi_axis_async_fifo.f @@ -1,3 +1,4 @@ taxi_axis_async_fifo.sv ../sync/taxi_sync_reset.sv +../sync/taxi_sync_signal.sv taxi_axis_if.sv diff --git a/rtl/axis/taxi_axis_async_fifo.sv b/rtl/axis/taxi_axis_async_fifo.sv index 7a7549d..fd4ffc6 100644 --- a/rtl/axis/taxi_axis_async_fifo.sv +++ b/rtl/axis/taxi_axis_async_fifo.sv @@ -802,24 +802,27 @@ if (PAUSE_EN) begin : pause logic pause_reg = 1'b0; logic pause_frame_reg = 1'b0; - logic s_pause_req_sync1_reg; - logic s_pause_req_sync2_reg; - logic s_pause_req_sync3_reg; - logic s_pause_ack_sync1_reg; - logic s_pause_ack_sync2_reg; - logic s_pause_ack_sync3_reg; + wire s_pause_req_sync; - always_ff @(posedge s_clk) begin - s_pause_req_sync1_reg <= s_pause_req; - s_pause_ack_sync2_reg <= s_pause_ack_sync1_reg; - s_pause_ack_sync3_reg <= s_pause_ack_sync2_reg; - end + taxi_sync_signal #( + .WIDTH(1), + .N(2) + ) + pause_req_sync_inst ( + .clk(m_clk), + .in(s_pause_req), + .out(s_pause_req_sync) + ); - always_ff @(posedge m_clk) begin - s_pause_req_sync2_reg <= s_pause_req_sync1_reg; - s_pause_req_sync3_reg <= s_pause_req_sync2_reg; - s_pause_ack_sync1_reg <= pause_reg; - end + taxi_sync_signal #( + .WIDTH(1), + .N(2) + ) + pause_ack_sync_inst ( + .clk(s_clk), + .in(pause_reg), + .out(s_pause_ack) + ); assign m_axis_tready_out = m_axis.tready && !pause_reg; assign m_axis.tvalid = m_axis_tvalid_out && !pause_reg; @@ -832,28 +835,27 @@ if (PAUSE_EN) begin : pause assign m_axis.tdest = m_axis_tdest_out; assign m_axis.tuser = m_axis_tuser_out; - assign s_pause_ack = s_pause_ack_sync3_reg; assign m_pause_ack = pause_reg; always_ff @(posedge m_clk) begin if (FRAME_PAUSE) begin if (pause_reg) begin // paused; update pause status - pause_reg <= m_pause_req || s_pause_req_sync3_reg; + pause_reg <= m_pause_req || s_pause_req_sync; end else if (m_axis_tvalid_out) begin // frame transfer; set frame bit pause_frame_reg <= 1'b1; if (m_axis.tready && m_axis.tlast) begin // end of frame; clear frame bit and update pause status pause_frame_reg <= 1'b0; - pause_reg <= m_pause_req || s_pause_req_sync3_reg; + pause_reg <= m_pause_req || s_pause_req_sync; end end else if (!pause_frame_reg) begin // idle; update pause status - pause_reg <= m_pause_req || s_pause_req_sync3_reg; + pause_reg <= m_pause_req || s_pause_req_sync; end end else begin - pause_reg <= m_pause_req || s_pause_req_sync3_reg; + pause_reg <= m_pause_req || s_pause_req_sync; end if (m_rst) begin diff --git a/syn/vivado/taxi_axis_async_fifo.tcl b/syn/vivado/taxi_axis_async_fifo.tcl index 69db15f..f6ce878 100644 --- a/syn/vivado/taxi_axis_async_fifo.tcl +++ b/syn/vivado/taxi_axis_async_fifo.tcl @@ -77,21 +77,4 @@ foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_axis_async_fi set_max_delay -from [get_cells "$fifo_inst/${i}_sync1_reg_reg"] -to [get_cells "$fifo_inst/${i}_sync2_reg_reg"] -datapath_only $read_clk_period } } - - # pause sync - set sync_ffs [get_cells -quiet -hier -regexp ".*/pause.s_pause_req_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"] - - if {[llength $sync_ffs]} { - set_property ASYNC_REG TRUE $sync_ffs - - set_max_delay -from [get_cells "$fifo_inst/pause.s_pause_req_sync1_reg_reg"] -to [get_cells "$fifo_inst/pause.s_pause_req_sync2_reg_reg"] -datapath_only $read_clk_period - } - - set sync_ffs [get_cells -quiet -hier -regexp ".*/pause.s_pause_ack_sync\[123\]_reg_reg" -filter "PARENT == $fifo_inst"] - - if {[llength $sync_ffs]} { - set_property ASYNC_REG TRUE $sync_ffs - - set_max_delay -from [get_cells "$fifo_inst/pause.s_pause_ack_sync1_reg_reg"] -to [get_cells "$fifo_inst/pause.s_pause_ack_sync2_reg_reg"] -datapath_only $write_clk_period - } }