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cndm: Add support for RK-XCKU5P-F
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
35
src/cndm/board/RK_XCKU5P_F/fpga/README.md
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35
src/cndm/board/RK_XCKU5P_F/fpga/README.md
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@@ -0,0 +1,35 @@
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# Corundum for RK-XCKU5P-F
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## Introduction
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This design targets the RK-XCKU5P-F FPGA board.
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* USB UART
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* XFCP (3 Mbaud)
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* QSFP28 cage
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* 10GBASE-R or 25GBASE-R MAC via GTY transceiver
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## Board details
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* FPGA: xcku5p-ffvb676-2-e
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* USB UART: FTDI FT2232
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* PCIe: gen 3 x4 (~32 Gbps)
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* Reference oscillator: Fixed 156.25 MHz
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* 25GBASE-R PHY: Soft PCS with GTY transceiver
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## Licensing
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* Toolchain
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* Vivado Standard (enterprise license not required)
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* IP
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* No licensed vendor IP or 3rd party IP
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## How to build
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Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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On the host system, run `make` in `modules/cndm` to build the driver. Ensure that the headers for the running kernel are installed, otherwise the driver cannot be compiled.
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## How to test
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Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod cndm.ko`. Check `dmesg` for output from driver initialization. Run `cndm_ddcmd.sh =p` to enable all debug messages.
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153
src/cndm/board/RK_XCKU5P_F/fpga/common/vivado.mk
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153
src/cndm/board/RK_XCKU5P_F/fpga/common/vivado.mk
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@@ -0,0 +1,153 @@
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# SPDX-License-Identifier: MIT
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016-2025 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - list of source files
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# INC_FILES - list of include files
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# XDC_FILES - list of timing constraint files
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# XCI_FILES - list of IP XCI files
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# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
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# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
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#
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# Note: both SYN_FILES and INC_FILES support file list files. File list
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# files are files with a .f extension that contain a list of additional
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# files to include, one path relative to the .f file location per line.
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# The .f files are processed recursively, and then the complete file list
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# is de-duplicated, with later files in the list taking precedence.
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include $(CONFIG)
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FPGA_TOP ?= fpga
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PROJECT ?= $(FPGA_TOP)
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XDC_FILES ?= $(PROJECT).xdc
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
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INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
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###################################################################
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# Main Targets
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#
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# all: build everything (fpga)
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# fpga: build FPGA config
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# vivado: open project in Vivado
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# tmpclean: remove intermediate files
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# clean: remove output files and project files
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# distclean: remove archived output files
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###################################################################
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all: fpga
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fpga: $(PROJECT).bit
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vivado: $(PROJECT).xpr
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vivado $(PROJECT).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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# create fresh project if Makefile or IP files have changed
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create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
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echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
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for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
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# source config TCL scripts if any source file has changed
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update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
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echo "open_project -quiet $(PROJECT).xpr" > $@
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for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
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$(PROJECT).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
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echo "open_project $(PROJECT).xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
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echo "open_project $(PROJECT).xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "open_run impl_1" >> run_impl.tcl
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echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
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echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# output files (including potentially bit, bin, ltx, and xsa)
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$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
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echo "open_project $(PROJECT).xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
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echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
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echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
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if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
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386
src/cndm/board/RK_XCKU5P_F/fpga/fpga.xdc
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386
src/cndm/board/RK_XCKU5P_F/fpga/fpga.xdc
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@@ -0,0 +1,386 @@
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2026 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# XDC constraints for the RK-XCKU5P-F
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# part: xcku5p-ffvb676-2-e
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 72.9 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]
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set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
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# 200 MHz system clock (Y2)
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set_property -dict {LOC T24 IOSTANDARD LVDS} [get_ports {clk_200mhz_p}]
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set_property -dict {LOC U24 IOSTANDARD LVDS} [get_ports {clk_200mhz_n}]
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create_clock -period 5.000 -name clk_200mhz [get_ports {clk_200mhz_p}]
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# LEDs
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set_property -dict {LOC H9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[0]}] ;# LED2
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set_property -dict {LOC J9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[1]}] ;# LED3
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set_property -dict {LOC G11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[2]}] ;# LED4
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set_property -dict {LOC H11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {led[3]}] ;# LED5
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set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# Buttons
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set_property -dict {LOC K9 IOSTANDARD LVCMOS33} [get_ports {btn[0]}] ;# K1
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set_property -dict {LOC K10 IOSTANDARD LVCMOS33} [get_ports {btn[1]}] ;# K2
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set_property -dict {LOC J10 IOSTANDARD LVCMOS33} [get_ports {btn[2]}] ;# K3
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set_property -dict {LOC J11 IOSTANDARD LVCMOS33} [get_ports {btn[3]}] ;# K4
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set_false_path -from [get_ports {btn[*]}]
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set_input_delay 0 [get_ports {btn[*]}]
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# GPIO
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#set_property -dict {LOC D10 IOSTANDARD LVCMOS33} [get_ports {gpio[0]}] ;# J1.3
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#set_property -dict {LOC D11 IOSTANDARD LVCMOS33} [get_ports {gpio[1]}] ;# J1.4
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#set_property -dict {LOC E10 IOSTANDARD LVCMOS33} [get_ports {gpio[2]}] ;# J1.5
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#set_property -dict {LOC E11 IOSTANDARD LVCMOS33} [get_ports {gpio[3]}] ;# J1.6
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#set_property -dict {LOC B11 IOSTANDARD LVCMOS33} [get_ports {gpio[4]}] ;# J1.7
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#set_property -dict {LOC C11 IOSTANDARD LVCMOS33} [get_ports {gpio[5]}] ;# J1.8
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#set_property -dict {LOC C9 IOSTANDARD LVCMOS33} [get_ports {gpio[6]}] ;# J1.9
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#set_property -dict {LOC D9 IOSTANDARD LVCMOS33} [get_ports {gpio[7]}] ;# J1.10
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#set_property -dict {LOC A9 IOSTANDARD LVCMOS33} [get_ports {gpio[8]}] ;# J1.11
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#set_property -dict {LOC B9 IOSTANDARD LVCMOS33} [get_ports {gpio[9]}] ;# J1.12
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#set_property -dict {LOC A10 IOSTANDARD LVCMOS33} [get_ports {gpio[10]}] ;# J1.13
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#set_property -dict {LOC B10 IOSTANDARD LVCMOS33} [get_ports {gpio[11]}] ;# J1.14
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#set_property -dict {LOC A12 IOSTANDARD LVCMOS33} [get_ports {gpio[12]}] ;# J1.15
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#set_property -dict {LOC A13 IOSTANDARD LVCMOS33} [get_ports {gpio[13]}] ;# J1.16
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#set_property -dict {LOC A14 IOSTANDARD LVCMOS33} [get_ports {gpio[14]}] ;# J1.17
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#set_property -dict {LOC B14 IOSTANDARD LVCMOS33} [get_ports {gpio[15]}] ;# J1.18
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#set_property -dict {LOC C13 IOSTANDARD LVCMOS33} [get_ports {gpio[16]}] ;# J1.19
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#set_property -dict {LOC C14 IOSTANDARD LVCMOS33} [get_ports {gpio[17]}] ;# J1.20
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#set_property -dict {LOC B12 IOSTANDARD LVCMOS33} [get_ports {gpio[18]}] ;# J1.21
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#set_property -dict {LOC C12 IOSTANDARD LVCMOS33} [get_ports {gpio[19]}] ;# J1.22
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#set_property -dict {LOC D13 IOSTANDARD LVCMOS33} [get_ports {gpio[20]}] ;# J1.23
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#set_property -dict {LOC D14 IOSTANDARD LVCMOS33} [get_ports {gpio[21]}] ;# J1.24
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#set_property -dict {LOC E12 IOSTANDARD LVCMOS33} [get_ports {gpio[22]}] ;# J1.25
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#set_property -dict {LOC E13 IOSTANDARD LVCMOS33} [get_ports {gpio[23]}] ;# J1.26
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#set_property -dict {LOC F13 IOSTANDARD LVCMOS33} [get_ports {gpio[24]}] ;# J1.27
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#set_property -dict {LOC F14 IOSTANDARD LVCMOS33} [get_ports {gpio[25]}] ;# J1.28
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#set_property -dict {LOC F12 IOSTANDARD LVCMOS33} [get_ports {gpio[26]}] ;# J1.29
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#set_property -dict {LOC G12 IOSTANDARD LVCMOS33} [get_ports {gpio[27]}] ;# J1.30
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#set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports {gpio[28]}] ;# J1.31
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#set_property -dict {LOC H14 IOSTANDARD LVCMOS33} [get_ports {gpio[29]}] ;# J1.32
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#set_property -dict {LOC J14 IOSTANDARD LVCMOS33} [get_ports {gpio[30]}] ;# J1.33
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#set_property -dict {LOC J15 IOSTANDARD LVCMOS33} [get_ports {gpio[31]}] ;# J1.34
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#set_property -dict {LOC H13 IOSTANDARD LVCMOS33} [get_ports {gpio[32]}] ;# J1.35
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#set_property -dict {LOC J13 IOSTANDARD LVCMOS33} [get_ports {gpio[33]}] ;# J1.36
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# UART
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set_property -dict {LOC AC14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U9.38 BDBUS0
|
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set_property -dict {LOC AD13 IOSTANDARD LVCMOS33} [get_ports {uart_rxd}] ;# U9.39 BDBUS1
|
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set_false_path -to [get_ports {uart_txd}]
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set_output_delay 0 [get_ports {uart_txd}]
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set_false_path -from [get_ports {uart_rxd}]
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set_input_delay 0 [get_ports {uart_rxd}]
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# Micro SD
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#set_property -dict {LOC Y15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8} [get_ports {sd_clk}] ;# SD1.5 CLK SCLK
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#set_property -dict {LOC AA15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8} [get_ports {sd_cmd}] ;# SD1.3 CMD DI
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#set_property -dict {LOC AB14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8} [get_ports {sd_d[0]}] ;# SD1.7 D0 DO
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#set_property -dict {LOC AA14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8} [get_ports {sd_d[1]}] ;# SD1.8 D1
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#set_property -dict {LOC AB16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8} [get_ports {sd_d[2]}] ;# SD1.1 D2
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#set_property -dict {LOC AB15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8} [get_ports {sd_d[3]}] ;# SD1.2 D3 CS
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#set_property -dict {LOC Y16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8} [get_ports {sd_cd}] ;# SD1.9 CD
|
||||
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# Fan
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#set_property -dict {LOC G9 IOSTANDARD LVCMOS33 QUIETIO SLOW DRIVE 8} [get_ports {fan}] ;# J2
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# Gigabit Ethernet RGMII PHY
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#set_property -dict {LOC K22 IOSTANDARD LVCMOS18} [get_ports {phy_rx_clk}] ;# from U16.28 RXC
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||||
#set_property -dict {LOC L24 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[0]}] ;# from U16.26 RXD0
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#set_property -dict {LOC L25 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[1]}] ;# from U16.25 RXD1
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#set_property -dict {LOC K25 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[2]}] ;# from U16.24 RXD2
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||||
#set_property -dict {LOC K26 IOSTANDARD LVCMOS18} [get_ports {phy_rxd[3]}] ;# from U16.23 RXD3
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||||
#set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {phy_rx_ctl}] ;# from U16.27 RXCTL
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||||
#set_property -dict {LOC M25 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_tx_clk}] ;# from U16.21 TXC
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||||
#set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] ;# from U16.19 TXD0
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||||
#set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] ;# from U16.18 TXD1
|
||||
#set_property -dict {LOC L20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] ;# from U16.17 TXD2
|
||||
#set_property -dict {LOC K20 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] ;# from U16.16 TXD3
|
||||
#set_property -dict {LOC M26 IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy_tx_ctl}] ;# from U16.20 TXCTL
|
||||
#set_property -dict {LOC M19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy_mdio}] ;# from U16.14 MDIO
|
||||
#set_property -dict {LOC L19 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy_mdc}] ;# from U16.13 MDC
|
||||
|
||||
#create_clock -period 8.000 -name {phy_rx_clk} [get_ports {phy_rx_clk}]
|
||||
|
||||
# QSFP28 Interface
|
||||
set_property -dict {LOC Y2 } [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC Y1 } [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AA5 } [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC AA4 } [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC V2 } [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC V1 } [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC W5 } [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC W4 } [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC T2 } [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC T1 } [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC U5 } [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC U4 } [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC P2 } [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC P1 } [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC R5 } [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC R4 } [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
|
||||
set_property -dict {LOC V7 } [get_ports {qsfp_mgt_refclk_p}] ;# MGTREFCLK0P_225
|
||||
set_property -dict {LOC V6 } [get_ports {qsfp_mgt_refclk_n}] ;# MGTREFCLK0N_225
|
||||
set_property -dict {LOC W13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_modsell]
|
||||
set_property -dict {LOC W12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_resetl]
|
||||
set_property -dict {LOC AA13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_modprsl]
|
||||
set_property -dict {LOC Y13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports qsfp_intl]
|
||||
set_property -dict {LOC W14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports qsfp_lpmode]
|
||||
#set_property -dict {LOC AE15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {qsfp_i2c_scl}]
|
||||
#set_property -dict {LOC AE13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports {qsfp_i2c_sda}]
|
||||
|
||||
# 156.25 MHz MGT reference clock
|
||||
create_clock -period 6.4 -name qsfp_mgt_refclk [get_ports {qsfp_mgt_refclk_p}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp_modsell qsfp_resetl qsfp_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp_modsell qsfp_resetl qsfp_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp_modprsl qsfp_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp_modprsl qsfp_intl}]
|
||||
|
||||
#set_false_path -to [get_ports {qsfp_i2c_sda[*] qsfp_i2c_scl[*]}]
|
||||
#set_output_delay 0 [get_ports {qsfp_i2c_sda[*] qsfp_i2c_scl[*]}]
|
||||
#set_false_path -from [get_ports {qsfp_i2c_sda[*] qsfp_i2c_scl[*]}]
|
||||
#set_input_delay 0 [get_ports {qsfp_i2c_sda[*] qsfp_i2c_scl[*]}]
|
||||
|
||||
# PCIe Interface
|
||||
set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AC5 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AC4 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AE9 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AE8 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
|
||||
set_property -dict {LOC AB7 } [get_ports pcie_refclk_p] ;# MGTREFCLK1P_224
|
||||
set_property -dict {LOC AB6 } [get_ports pcie_refclk_n] ;# MGTREFCLK1N_224
|
||||
set_property -dict {LOC T19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n]
|
||||
|
||||
set_false_path -from [get_ports {pcie_reset_n}]
|
||||
set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p]
|
||||
|
||||
# FMC interface
|
||||
# FMC HPC J4
|
||||
#set_property -dict {LOC G24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[0]}] ;# J4.G9 LA00_P_CC
|
||||
#set_property -dict {LOC G25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[0]}] ;# J4.G10 LA00_N_CC
|
||||
#set_property -dict {LOC J23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[1]}] ;# J4.D8 LA01_P_CC
|
||||
#set_property -dict {LOC J24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[1]}] ;# J4.D9 LA01_N_CC
|
||||
#set_property -dict {LOC H21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[2]}] ;# J4.H7 LA02_P
|
||||
#set_property -dict {LOC H22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[2]}] ;# J4.H8 LA02_N
|
||||
#set_property -dict {LOC J19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[3]}] ;# J4.G12 LA03_P
|
||||
#set_property -dict {LOC J20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[3]}] ;# J4.G13 LA03_N
|
||||
#set_property -dict {LOC H26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[4]}] ;# J4.H10 LA04_P
|
||||
#set_property -dict {LOC G26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[4]}] ;# J4.H11 LA04_N
|
||||
#set_property -dict {LOC F24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[5]}] ;# J4.D11 LA05_P
|
||||
#set_property -dict {LOC F25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[5]}] ;# J4.D12 LA05_N
|
||||
#set_property -dict {LOC G20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[6]}] ;# J4.C10 LA06_P
|
||||
#set_property -dict {LOC G21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[6]}] ;# J4.C11 LA06_N
|
||||
#set_property -dict {LOC D24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[7]}] ;# J4.H13 LA07_P
|
||||
#set_property -dict {LOC D25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[7]}] ;# J4.H14 LA07_N
|
||||
#set_property -dict {LOC D26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[8]}] ;# J4.G12 LA08_P
|
||||
#set_property -dict {LOC C26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[8]}] ;# J4.G13 LA08_N
|
||||
#set_property -dict {LOC E25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[9]}] ;# J4.D14 LA09_P
|
||||
#set_property -dict {LOC E26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[9]}] ;# J4.D15 LA09_N
|
||||
#set_property -dict {LOC B25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[10]}] ;# J4.C14 LA10_P
|
||||
#set_property -dict {LOC B26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[10]}] ;# J4.C15 LA10_N
|
||||
#set_property -dict {LOC A24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[11]}] ;# J4.H16 LA11_P
|
||||
#set_property -dict {LOC A25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[11]}] ;# J4.H17 LA11_N
|
||||
#set_property -dict {LOC D23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[12]}] ;# J4.G15 LA12_P
|
||||
#set_property -dict {LOC C24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[12]}] ;# J4.G16 LA12_N
|
||||
#set_property -dict {LOC F23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[13]}] ;# J4.D17 LA13_P
|
||||
#set_property -dict {LOC E23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[13]}] ;# J4.D18 LA13_N
|
||||
#set_property -dict {LOC C23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[14]}] ;# J4.C18 LA14_P
|
||||
#set_property -dict {LOC B24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[14]}] ;# J4.C19 LA14_N
|
||||
#set_property -dict {LOC H18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[15]}] ;# J4.H19 LA15_P
|
||||
#set_property -dict {LOC H19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[15]}] ;# J4.H20 LA15_N
|
||||
#set_property -dict {LOC E21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[16]}] ;# J4.G18 LA16_P
|
||||
#set_property -dict {LOC D21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[16]}] ;# J4.G19 LA16_N
|
||||
#set_property -dict {LOC C18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[17]}] ;# J4.D20 LA17_P_CC
|
||||
#set_property -dict {LOC C19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[17]}] ;# J4.D21 LA17_N_CC
|
||||
#set_property -dict {LOC D19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[18]}] ;# J4.C22 LA18_P_CC
|
||||
#set_property -dict {LOC D20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[18]}] ;# J4.C23 LA18_N_CC
|
||||
#set_property -dict {LOC A22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[19]}] ;# J4.H22 LA19_P
|
||||
#set_property -dict {LOC A23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[19]}] ;# J4.H23 LA19_N
|
||||
#set_property -dict {LOC F20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[20]}] ;# J4.G21 LA20_P
|
||||
#set_property -dict {LOC E20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[20]}] ;# J4.G22 LA20_N
|
||||
#set_property -dict {LOC C21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[21]}] ;# J4.H25 LA21_P
|
||||
#set_property -dict {LOC B21 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[21]}] ;# J4.H26 LA21_N
|
||||
#set_property -dict {LOC H16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[22]}] ;# J4.G24 LA22_P
|
||||
#set_property -dict {LOC G16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[22]}] ;# J4.G25 LA22_N
|
||||
#set_property -dict {LOC C22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[23]}] ;# J4.D23 LA23_P
|
||||
#set_property -dict {LOC B22 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[23]}] ;# J4.D24 LA23_N
|
||||
#set_property -dict {LOC A17 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[24]}] ;# J4.H28 LA24_P
|
||||
#set_property -dict {LOC A18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[24]}] ;# J4.H29 LA24_N
|
||||
#set_property -dict {LOC E18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[25]}] ;# J4.G27 LA25_P
|
||||
#set_property -dict {LOC D18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[25]}] ;# J4.G28 LA25_N
|
||||
#set_property -dict {LOC A19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[26]}] ;# J4.D26 LA26_P
|
||||
#set_property -dict {LOC A20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[26]}] ;# J4.D27 LA26_N
|
||||
#set_property -dict {LOC F18 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[27]}] ;# J4.C26 LA27_P
|
||||
#set_property -dict {LOC F19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[27]}] ;# J4.C27 LA27_N
|
||||
#set_property -dict {LOC C17 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[28]}] ;# J4.H31 LA28_P
|
||||
#set_property -dict {LOC B17 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[28]}] ;# J4.H32 LA28_N
|
||||
#set_property -dict {LOC E16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[29]}] ;# J4.G30 LA29_P
|
||||
#set_property -dict {LOC E17 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[29]}] ;# J4.G31 LA29_N
|
||||
#set_property -dict {LOC D16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[30]}] ;# J4.H34 LA30_P
|
||||
#set_property -dict {LOC C16 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[30]}] ;# J4.H35 LA30_N
|
||||
#set_property -dict {LOC G15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[31]}] ;# J4.G33 LA31_P
|
||||
#set_property -dict {LOC F15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[31]}] ;# J4.G34 LA31_N
|
||||
#set_property -dict {LOC B15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[32]}] ;# J4.H37 LA32_P
|
||||
#set_property -dict {LOC A15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[32]}] ;# J4.H38 LA32_N
|
||||
#set_property -dict {LOC E15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_p[33]}] ;# J4.G36 LA33_P
|
||||
#set_property -dict {LOC D15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_la_n[33]}] ;# J4.G37 LA33_N
|
||||
|
||||
#set_property -dict {LOC H23 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_clk0_m2c_p}] ;# J4.H4 CLK0_M2C_P
|
||||
#set_property -dict {LOC H24 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_clk0_m2c_n}] ;# J4.H5 CLK0_M2C_N
|
||||
#set_property -dict {LOC B19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_clk1_m2c_p}] ;# J4.G2 CLK1_M2C_P
|
||||
#set_property -dict {LOC B20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {fmc_clk1_m2c_n}] ;# J4.G3 CLK1_M2C_N
|
||||
|
||||
#set_property -dict {LOC F10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {fmc_scl}] ;# J4.C30 SCL
|
||||
#set_property -dict {LOC F9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {fmc_sda}] ;# J4.C31 SDA
|
||||
#set_property -dict {LOC G10 IOSTANDARD LVCMOS33} [get_ports {fmc_pg_m2c}] ;# J4.F1 PG_M2C
|
||||
|
||||
#set_property -dict {LOC N5 } [get_ports {fmc_dp_c2m_p[0]}] ;# MGTHTXP0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y3 from J4.C2 DP0_C2M_P
|
||||
#set_property -dict {LOC N4 } [get_ports {fmc_dp_c2m_n[0]}] ;# MGTHTXN0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y3 from J4.C3 DP0_C2M_N
|
||||
#set_property -dict {LOC M2 } [get_ports {fmc_dp_m2c_p[0]}] ;# MGTHRXP0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y3 from J4.C6 DP0_M2C_P
|
||||
#set_property -dict {LOC M1 } [get_ports {fmc_dp_m2c_n[0]}] ;# MGTHRXN0_226 GTHE4_CHANNEL_X0Y8 / GTHE4_COMMON_X0Y3 from J4.C7 DP0_M2C_N
|
||||
#set_property -dict {LOC L5 } [get_ports {fmc_dp_c2m_p[1]}] ;# MGTHTXP1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y3 from J4.A22 DP1_C2M_P
|
||||
#set_property -dict {LOC L4 } [get_ports {fmc_dp_c2m_n[1]}] ;# MGTHTXN1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y3 from J4.A23 DP1_C2M_N
|
||||
#set_property -dict {LOC K2 } [get_ports {fmc_dp_m2c_p[1]}] ;# MGTHRXP1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y3 from J4.A2 DP1_M2C_P
|
||||
#set_property -dict {LOC K1 } [get_ports {fmc_dp_m2c_n[1]}] ;# MGTHRXN1_226 GTHE4_CHANNEL_X0Y9 / GTHE4_COMMON_X0Y3 from J4.A3 DP1_M2C_N
|
||||
#set_property -dict {LOC J5 } [get_ports {fmc_dp_c2m_p[2]}] ;# MGTHTXP2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y3 from J4.A26 DP2_C2M_P
|
||||
#set_property -dict {LOC J4 } [get_ports {fmc_dp_c2m_n[2]}] ;# MGTHTXN2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y3 from J4.A27 DP2_C2M_N
|
||||
#set_property -dict {LOC H2 } [get_ports {fmc_dp_m2c_p[2]}] ;# MGTHRXP2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y3 from J4.A6 DP2_M2C_P
|
||||
#set_property -dict {LOC H1 } [get_ports {fmc_dp_m2c_n[2]}] ;# MGTHRXN2_226 GTHE4_CHANNEL_X0Y10 / GTHE4_COMMON_X0Y3 from J4.A7 DP2_M2C_N
|
||||
#set_property -dict {LOC G5 } [get_ports {fmc_dp_c2m_p[3]}] ;# MGTHTXP3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y3 from J4.A30 DP3_C2M_P
|
||||
#set_property -dict {LOC G4 } [get_ports {fmc_dp_c2m_n[3]}] ;# MGTHTXN3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y3 from J4.A31 DP3_C2M_N
|
||||
#set_property -dict {LOC F2 } [get_ports {fmc_dp_m2c_p[3]}] ;# MGTHRXP3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y3 from J4.A10 DP3_M2C_P
|
||||
#set_property -dict {LOC F1 } [get_ports {fmc_dp_m2c_n[3]}] ;# MGTHRXN3_226 GTHE4_CHANNEL_X0Y11 / GTHE4_COMMON_X0Y3 from J4.A11 DP3_M2C_N
|
||||
|
||||
#set_property -dict {LOC F7 } [get_ports {fmc_dp_c2m_p[4]}] ;# MGTHTXP0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y4 from J4.A34 DP4_C2M_P
|
||||
#set_property -dict {LOC F6 } [get_ports {fmc_dp_c2m_n[4]}] ;# MGTHTXN0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y4 from J4.A35 DP4_C2M_N
|
||||
#set_property -dict {LOC D2 } [get_ports {fmc_dp_m2c_p[4]}] ;# MGTHRXP0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y4 from J4.A14 DP4_M2C_P
|
||||
#set_property -dict {LOC D1 } [get_ports {fmc_dp_m2c_n[4]}] ;# MGTHRXN0_227 GTHE4_CHANNEL_X0Y12 / GTHE4_COMMON_X0Y4 from J4.A15 DP4_M2C_N
|
||||
#set_property -dict {LOC E5 } [get_ports {fmc_dp_c2m_p[5]}] ;# MGTHTXP1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y4 from J4.A38 DP5_C2M_P
|
||||
#set_property -dict {LOC E4 } [get_ports {fmc_dp_c2m_n[5]}] ;# MGTHTXN1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y4 from J4.A39 DP5_C2M_N
|
||||
#set_property -dict {LOC C4 } [get_ports {fmc_dp_m2c_p[5]}] ;# MGTHRXP1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y4 from J4.A18 DP5_M2C_P
|
||||
#set_property -dict {LOC C3 } [get_ports {fmc_dp_m2c_n[5]}] ;# MGTHRXN1_227 GTHE4_CHANNEL_X0Y13 / GTHE4_COMMON_X0Y4 from J4.A19 DP5_M2C_N
|
||||
#set_property -dict {LOC D7 } [get_ports {fmc_dp_c2m_p[6]}] ;# MGTHTXP2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y4 from J4.B36 DP6_C2M_P
|
||||
#set_property -dict {LOC D6 } [get_ports {fmc_dp_c2m_n[6]}] ;# MGTHTXN2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y4 from J4.B37 DP6_C2M_N
|
||||
#set_property -dict {LOC B2 } [get_ports {fmc_dp_m2c_p[6]}] ;# MGTHRXP2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y4 from J4.B16 DP6_M2C_P
|
||||
#set_property -dict {LOC B1 } [get_ports {fmc_dp_m2c_n[6]}] ;# MGTHRXN2_227 GTHE4_CHANNEL_X0Y14 / GTHE4_COMMON_X0Y4 from J4.B17 DP6_M2C_N
|
||||
#set_property -dict {LOC B7 } [get_ports {fmc_dp_c2m_p[7]}] ;# MGTHTXP3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y4 from J4.B32 DP7_C2M_P
|
||||
#set_property -dict {LOC B6 } [get_ports {fmc_dp_c2m_n[7]}] ;# MGTHTXN3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y4 from J4.B33 DP7_C2M_N
|
||||
#set_property -dict {LOC A4 } [get_ports {fmc_dp_m2c_p[7]}] ;# MGTHRXP3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y4 from J4.B12 DP7_M2C_P
|
||||
#set_property -dict {LOC A3 } [get_ports {fmc_dp_m2c_n[7]}] ;# MGTHRXN3_227 GTHE4_CHANNEL_X0Y15 / GTHE4_COMMON_X0Y4 from J4.B13 DP7_M2C_N
|
||||
#set_property -dict {LOC P7 } [get_ports {fmc_mgt_refclk_0_p}] ;# MGTREFCLK0P_226 from J4.D4 GBTCLK0_M2C_P
|
||||
#set_property -dict {LOC P6 } [get_ports {fmc_mgt_refclk_0_n}] ;# MGTREFCLK0N_226 from J4.D5 GBTCLK0_M2C_N
|
||||
#set_property -dict {LOC K7 } [get_ports {fmc_mgt_refclk_1_p}] ;# MGTREFCLK0P_227 from J4.B20 GBTCLK1_M2C_P
|
||||
#set_property -dict {LOC K6 } [get_ports {fmc_mgt_refclk_1_n}] ;# MGTREFCLK0N_227 from J4.B21 GBTCLK1_M2C_N
|
||||
|
||||
# reference clock
|
||||
#create_clock -period 6.400 -name fmc_mgt_refclk_0 [get_ports {fmc_mgt_refclk_0_p}]
|
||||
#create_clock -period 6.400 -name fmc_mgt_refclk_1 [get_ports {fmc_mgt_refclk_1_p}]
|
||||
|
||||
# DDR4
|
||||
# 2x MT40A512M16LY-062E:E U3, U6
|
||||
#set_property -dict {LOC Y22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}]
|
||||
#set_property -dict {LOC Y25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}]
|
||||
#set_property -dict {LOC W23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}]
|
||||
#set_property -dict {LOC V26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}]
|
||||
#set_property -dict {LOC R26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}]
|
||||
#set_property -dict {LOC U26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}]
|
||||
#set_property -dict {LOC R21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}]
|
||||
#set_property -dict {LOC W25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}]
|
||||
#set_property -dict {LOC R20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}]
|
||||
#set_property -dict {LOC Y26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}]
|
||||
#set_property -dict {LOC R25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}]
|
||||
#set_property -dict {LOC V23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}]
|
||||
#set_property -dict {LOC AA24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}]
|
||||
#set_property -dict {LOC W26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}]
|
||||
#set_property -dict {LOC P23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}]
|
||||
#set_property -dict {LOC AA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}]
|
||||
#set_property -dict {LOC T25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}]
|
||||
#set_property -dict {LOC P21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}]
|
||||
#set_property -dict {LOC P26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}]
|
||||
#set_property -dict {LOC R22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}]
|
||||
#set_property -dict {LOC V24 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}]
|
||||
#set_property -dict {LOC W24 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}]
|
||||
#set_property -dict {LOC P20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}]
|
||||
#set_property -dict {LOC P25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}]
|
||||
#set_property -dict {LOC P24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}]
|
||||
#set_property -dict {LOC R23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}]
|
||||
#set_property -dict {LOC Y23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_par}]
|
||||
#set_property -dict {LOC P19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}]
|
||||
#set_property -dict {LOC U25 IOSTANDARD LVCMOS12 } [get_ports {ddr4_alert_n}]
|
||||
|
||||
#set_property -dict {LOC AB26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}]
|
||||
#set_property -dict {LOC AB25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}]
|
||||
#set_property -dict {LOC AF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}]
|
||||
#set_property -dict {LOC AF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}]
|
||||
#set_property -dict {LOC AD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}]
|
||||
#set_property -dict {LOC AD24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}]
|
||||
#set_property -dict {LOC AC24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}]
|
||||
#set_property -dict {LOC AB24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}]
|
||||
#set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}]
|
||||
#set_property -dict {LOC AD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}]
|
||||
#set_property -dict {LOC AC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}]
|
||||
#set_property -dict {LOC AC22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}]
|
||||
#set_property -dict {LOC AE21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}]
|
||||
#set_property -dict {LOC AD21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}]
|
||||
#set_property -dict {LOC AC21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}]
|
||||
#set_property -dict {LOC AB21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}]
|
||||
#set_property -dict {LOC AC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}] ;# U3.G3 DQSL_T
|
||||
#set_property -dict {LOC AD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}] ;# U3.F3 DQSL_C
|
||||
#set_property -dict {LOC AA22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}] ;# U3.B7 DQSU_T
|
||||
#set_property -dict {LOC AB22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}] ;# U3.A7 DQSU_C
|
||||
#set_property -dict {LOC AE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] ;# U3.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC AE22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] ;# U3.E2 DMU_B/DBIU_B
|
||||
|
||||
#set_property -dict {LOC AD19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}]
|
||||
#set_property -dict {LOC AC19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}]
|
||||
#set_property -dict {LOC AF19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}]
|
||||
#set_property -dict {LOC AF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}]
|
||||
#set_property -dict {LOC AF17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}]
|
||||
#set_property -dict {LOC AE17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}]
|
||||
#set_property -dict {LOC AE16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}]
|
||||
#set_property -dict {LOC AD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}]
|
||||
#set_property -dict {LOC AB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}]
|
||||
#set_property -dict {LOC AA19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}]
|
||||
#set_property -dict {LOC AB20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}]
|
||||
#set_property -dict {LOC AA20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}]
|
||||
#set_property -dict {LOC AA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}]
|
||||
#set_property -dict {LOC Y17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}]
|
||||
#set_property -dict {LOC AA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}]
|
||||
#set_property -dict {LOC Y18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}]
|
||||
#set_property -dict {LOC AC18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}] ;# U6.G3 DQSL_T
|
||||
#set_property -dict {LOC AD18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}] ;# U6.F3 DQSL_C
|
||||
#set_property -dict {LOC AB17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}] ;# U6.B7 DQSU_T
|
||||
#set_property -dict {LOC AC17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}] ;# U6.A7 DQSU_C
|
||||
#set_property -dict {LOC AD20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}] ;# U6.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC Y20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}] ;# U6.E2 DMU_B/DBIU_B
|
||||
98
src/cndm/board/RK_XCKU5P_F/fpga/fpga/Makefile
Normal file
98
src/cndm/board/RK_XCKU5P_F/fpga/fpga/Makefile
Normal file
@@ -0,0 +1,98 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025-2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcku5p-ffvb676-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
|
||||
IP_TCL_FILES += ../ip/pcie4_uscale_plus_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 32 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu256-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
131
src/cndm/board/RK_XCKU5P_F/fpga/fpga/config.tcl
Normal file
131
src/cndm/board/RK_XCKU5P_F/fpga/fpga/config.tcl
Normal file
@@ -0,0 +1,131 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025-2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# collect build information
|
||||
set build_date [clock seconds]
|
||||
set git_hash 00000000
|
||||
set git_tag ""
|
||||
|
||||
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
|
||||
puts "Error running git or project not under version control"
|
||||
}
|
||||
|
||||
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
|
||||
puts "Error running git, project not under version control, or no tag found"
|
||||
}
|
||||
|
||||
puts "Build date: ${build_date}"
|
||||
puts "Git hash: ${git_hash}"
|
||||
puts "Git tag: ${git_tag}"
|
||||
|
||||
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
|
||||
puts "Failed to extract version from git tag"
|
||||
set tag_ver 0.0.1
|
||||
}
|
||||
|
||||
puts "Tag version: ${tag_ver}"
|
||||
|
||||
# FW and board IDs
|
||||
set fpga_id [expr 0x4A62093]
|
||||
set fw_id [expr 0x0000C001]
|
||||
set fw_ver $tag_ver
|
||||
set board_vendor_id [expr 0x1234]
|
||||
set board_device_id [expr 0x9005]
|
||||
set board_ver 1.0
|
||||
set release_info [expr 0x00000000]
|
||||
|
||||
# PCIe IDs
|
||||
set pcie_vendor_id [expr 0x1234]
|
||||
set pcie_device_id [expr 0xC001]
|
||||
set pcie_class_code [expr 0x020000]
|
||||
set pcie_revision_id [expr 0x00]
|
||||
set pcie_subsystem_device_id $board_device_id
|
||||
set pcie_subsystem_vendor_id $board_vendor_id
|
||||
|
||||
# FW ID
|
||||
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
|
||||
dict set params FW_ID [format "32'h%08x" $fw_id]
|
||||
dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0]
|
||||
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
|
||||
dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0]
|
||||
dict set params BUILD_DATE "32'd${build_date}"
|
||||
dict set params GIT_HASH "32'h${git_hash}"
|
||||
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||
|
||||
# PTP configuration
|
||||
dict set params PTP_TS_EN "1"
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
dict set params AXIL_CTRL_DATA_W "32"
|
||||
dict set params AXIL_CTRL_ADDR_W "24"
|
||||
|
||||
# MAC configuration
|
||||
dict set params CFG_LOW_LATENCY "1"
|
||||
dict set params COMBINED_MAC_PCS "1"
|
||||
dict set params MAC_DATA_W "64"
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
# configure BAR settings
|
||||
proc configure_bar {pcie pf bar aperture} {
|
||||
set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
|
||||
for { set i 0 } { $i < [llength $size_list] } { incr i } {
|
||||
set scale [lindex $size_list $i]
|
||||
|
||||
if {$aperture > 0 && $aperture < ($i+1)*10} {
|
||||
set size [expr 1 << $aperture - ($i*10)]
|
||||
|
||||
puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
|
||||
|
||||
set pcie_config [dict create]
|
||||
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
|
||||
|
||||
set_property -dict $pcie_config $pcie
|
||||
|
||||
return
|
||||
}
|
||||
}
|
||||
puts "${pcie} PF${pf} BAR${bar}: disabled"
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W]
|
||||
|
||||
# PCIe IP core configuration
|
||||
set pcie_config [dict create]
|
||||
|
||||
# PCIe IDs
|
||||
dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id]
|
||||
dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id]
|
||||
dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code]
|
||||
dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id]
|
||||
dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id]
|
||||
dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id]
|
||||
|
||||
# MSI
|
||||
dict set pcie_config "CONFIG.pf0_msi_enabled" {true}
|
||||
|
||||
set_property -dict $pcie_config $pcie
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
98
src/cndm/board/RK_XCKU5P_F/fpga/fpga_10g/Makefile
Normal file
98
src/cndm/board/RK_XCKU5P_F/fpga/fpga_10g/Makefile
Normal file
@@ -0,0 +1,98 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025-2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcku5p-ffvb676-2-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = kintexuplus
|
||||
|
||||
RTL_DIR = ../rtl
|
||||
LIB_DIR = ../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||
SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = ../fpga.xdc
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl
|
||||
IP_TCL_FILES += ../ip/pcie4_uscale_plus_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(PROJECT).bit
|
||||
echo "open_hw_manager" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||
echo "write_cfgmem -force -format mcs -size 32 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu256-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
131
src/cndm/board/RK_XCKU5P_F/fpga/fpga_10g/config.tcl
Normal file
131
src/cndm/board/RK_XCKU5P_F/fpga/fpga_10g/config.tcl
Normal file
@@ -0,0 +1,131 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2025-2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set params [dict create]
|
||||
|
||||
# collect build information
|
||||
set build_date [clock seconds]
|
||||
set git_hash 00000000
|
||||
set git_tag ""
|
||||
|
||||
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
|
||||
puts "Error running git or project not under version control"
|
||||
}
|
||||
|
||||
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
|
||||
puts "Error running git, project not under version control, or no tag found"
|
||||
}
|
||||
|
||||
puts "Build date: ${build_date}"
|
||||
puts "Git hash: ${git_hash}"
|
||||
puts "Git tag: ${git_tag}"
|
||||
|
||||
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
|
||||
puts "Failed to extract version from git tag"
|
||||
set tag_ver 0.0.1
|
||||
}
|
||||
|
||||
puts "Tag version: ${tag_ver}"
|
||||
|
||||
# FW and board IDs
|
||||
set fpga_id [expr 0x4A62093]
|
||||
set fw_id [expr 0x0000C001]
|
||||
set fw_ver $tag_ver
|
||||
set board_vendor_id [expr 0x1234]
|
||||
set board_device_id [expr 0x9005]
|
||||
set board_ver 1.0
|
||||
set release_info [expr 0x00000000]
|
||||
|
||||
# PCIe IDs
|
||||
set pcie_vendor_id [expr 0x1234]
|
||||
set pcie_device_id [expr 0xC001]
|
||||
set pcie_class_code [expr 0x020000]
|
||||
set pcie_revision_id [expr 0x00]
|
||||
set pcie_subsystem_device_id $board_device_id
|
||||
set pcie_subsystem_vendor_id $board_vendor_id
|
||||
|
||||
# FW ID
|
||||
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
|
||||
dict set params FW_ID [format "32'h%08x" $fw_id]
|
||||
dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0]
|
||||
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
|
||||
dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0]
|
||||
dict set params BUILD_DATE "32'd${build_date}"
|
||||
dict set params GIT_HASH "32'h${git_hash}"
|
||||
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||
|
||||
# PTP configuration
|
||||
dict set params PTP_TS_EN "1"
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
dict set params AXIL_CTRL_DATA_W "32"
|
||||
dict set params AXIL_CTRL_ADDR_W "24"
|
||||
|
||||
# MAC configuration
|
||||
dict set params CFG_LOW_LATENCY "1"
|
||||
dict set params COMBINED_MAC_PCS "1"
|
||||
dict set params MAC_DATA_W "32"
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
# configure BAR settings
|
||||
proc configure_bar {pcie pf bar aperture} {
|
||||
set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
|
||||
for { set i 0 } { $i < [llength $size_list] } { incr i } {
|
||||
set scale [lindex $size_list $i]
|
||||
|
||||
if {$aperture > 0 && $aperture < ($i+1)*10} {
|
||||
set size [expr 1 << $aperture - ($i*10)]
|
||||
|
||||
puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
|
||||
|
||||
set pcie_config [dict create]
|
||||
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
|
||||
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
|
||||
|
||||
set_property -dict $pcie_config $pcie
|
||||
|
||||
return
|
||||
}
|
||||
}
|
||||
puts "${pcie} PF${pf} BAR${bar}: disabled"
|
||||
set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
|
||||
}
|
||||
|
||||
# Control BAR (BAR 0)
|
||||
configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W]
|
||||
|
||||
# PCIe IP core configuration
|
||||
set pcie_config [dict create]
|
||||
|
||||
# PCIe IDs
|
||||
dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id]
|
||||
dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id]
|
||||
dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code]
|
||||
dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id]
|
||||
dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id]
|
||||
dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id]
|
||||
|
||||
# MSI
|
||||
dict set pcie_config "CONFIG.pf0_msi_enabled" {true}
|
||||
|
||||
set_property -dict $pcie_config $pcie
|
||||
|
||||
# apply parameters to top-level
|
||||
set param_list {}
|
||||
dict for {name value} $params {
|
||||
lappend param_list $name=$value
|
||||
}
|
||||
|
||||
set_property generic $param_list [get_filesets sources_1]
|
||||
30
src/cndm/board/RK_XCKU5P_F/fpga/ip/pcie4_uscale_plus_0.tcl
Normal file
30
src/cndm/board/RK_XCKU5P_F/fpga/ip/pcie4_uscale_plus_0.tcl
Normal file
@@ -0,0 +1,30 @@
|
||||
|
||||
create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
|
||||
CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X4} \
|
||||
CONFIG.AXISTEN_IF_RC_STRADDLE {false} \
|
||||
CONFIG.axisten_if_enable_client_tag {true} \
|
||||
CONFIG.axisten_if_width {128_bit} \
|
||||
CONFIG.extended_tag_field {true} \
|
||||
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
|
||||
CONFIG.axisten_freq {250} \
|
||||
CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \
|
||||
CONFIG.PF0_CLASS_CODE {020000} \
|
||||
CONFIG.PF0_DEVICE_ID {C001} \
|
||||
CONFIG.PF0_SUBSYSTEM_ID {0009} \
|
||||
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1234} \
|
||||
CONFIG.pf0_bar0_64bit {true} \
|
||||
CONFIG.pf0_bar0_prefetchable {true} \
|
||||
CONFIG.pf0_bar0_scale {Megabytes} \
|
||||
CONFIG.pf0_bar0_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
CONFIG.legacy_ext_pcie_cfg_space_enabled {true} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.mode_selection {Advanced} \
|
||||
CONFIG.en_gt_selection {true} \
|
||||
CONFIG.select_quad {GTY_Quad_224} \
|
||||
] [get_ips pcie4_uscale_plus_0]
|
||||
1
src/cndm/board/RK_XCKU5P_F/fpga/lib/taxi
Symbolic link
1
src/cndm/board/RK_XCKU5P_F/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
||||
../../../../../../
|
||||
901
src/cndm/board/RK_XCKU5P_F/fpga/rtl/fpga.sv
Normal file
901
src/cndm/board/RK_XCKU5P_F/fpga/rtl/fpga.sv
Normal file
@@ -0,0 +1,901 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter string VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter string FAMILY = "kintexuplus",
|
||||
|
||||
// FW ID
|
||||
parameter FPGA_ID = 32'h4A62093,
|
||||
parameter FW_ID = 32'h0000C001,
|
||||
parameter FW_VER = 32'h000_01_000,
|
||||
parameter BOARD_ID = 32'h1234_9005,
|
||||
parameter BOARD_VER = 32'h001_00_000,
|
||||
parameter BUILD_DATE = 32'd602976000,
|
||||
parameter GIT_HASH = 32'h5f87c2e8,
|
||||
parameter RELEASE_INFO = 32'h00000000,
|
||||
|
||||
// PTP configuration
|
||||
parameter logic PTP_TS_EN = 1'b1,
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
parameter AXIL_CTRL_DATA_W = 32,
|
||||
parameter AXIL_CTRL_ADDR_W = 24,
|
||||
|
||||
// MAC configuration
|
||||
parameter logic CFG_LOW_LATENCY = 1'b1,
|
||||
parameter logic COMBINED_MAC_PCS = 1'b1,
|
||||
parameter MAC_DATA_W = 64
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 200MHz LVDS
|
||||
*/
|
||||
input wire logic clk_200mhz_p,
|
||||
input wire logic clk_200mhz_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire logic [3:0] btn,
|
||||
output wire logic [3:0] led,
|
||||
|
||||
/*
|
||||
* UART: 300000 bps, 8N1
|
||||
*/
|
||||
input wire logic uart_rxd,
|
||||
output wire logic uart_txd,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T SGMII
|
||||
*/
|
||||
// input wire logic phy_rx_clk,
|
||||
// input wire logic [3:0] phy_rxd,
|
||||
// input wire logic phy_rx_ctl,
|
||||
// output wire logic phy_tx_clk,
|
||||
// output wire logic [3:0] phy_txd,
|
||||
// output wire logic phy_tx_ctl,
|
||||
// output wire logic phy_mdc,
|
||||
// inout wire logic phy_mdio,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
input wire logic qsfp_rx_p[4],
|
||||
input wire logic qsfp_rx_n[4],
|
||||
output wire logic qsfp_tx_p[4],
|
||||
output wire logic qsfp_tx_n[4],
|
||||
input wire logic qsfp_mgt_refclk_p,
|
||||
input wire logic qsfp_mgt_refclk_n,
|
||||
output wire logic qsfp_modsell,
|
||||
output wire logic qsfp_resetl,
|
||||
input wire logic qsfp_modprsl,
|
||||
input wire logic qsfp_intl,
|
||||
output wire logic qsfp_lpmode,
|
||||
// inout wire logic qsfp_i2c_scl,
|
||||
// inout wire logic qsfp_i2c_sda.
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
input wire logic [3:0] pcie_rx_p,
|
||||
input wire logic [3:0] pcie_rx_n,
|
||||
output wire logic [3:0] pcie_tx_p,
|
||||
output wire logic [3:0] pcie_tx_n,
|
||||
input wire logic pcie_refclk_p,
|
||||
input wire logic pcie_refclk_n,
|
||||
input wire logic pcie_reset_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
wire pcie_user_rst;
|
||||
|
||||
wire clk_200mhz_ibufg;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
IBUFGDS #(
|
||||
.DIFF_TERM("FALSE"),
|
||||
.IBUF_LOW_PWR("FALSE")
|
||||
)
|
||||
clk_200mhz_ibufg_inst (
|
||||
.O (clk_200mhz_ibufg),
|
||||
.I (clk_200mhz_p),
|
||||
.IB (clk_200mhz_n)
|
||||
);
|
||||
|
||||
// MMCM instance
|
||||
MMCME4_BASE #(
|
||||
// 100 MHz input
|
||||
.CLKIN1_PERIOD(10.0),
|
||||
.REF_JITTER1(0.010),
|
||||
// 200 MHz input / 4 = 50 MHz PFD (range 10 MHz to 500 MHz)
|
||||
.DIVCLK_DIVIDE(4),
|
||||
// 50 MHz PFD * 25 = 1250 MHz VCO (range 800 MHz to 1600 MHz)
|
||||
.CLKFBOUT_MULT_F(25),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
// 1250 MHz / 10 = 125 MHz, 0 degrees
|
||||
.CLKOUT0_DIVIDE_F(10),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT4_CASCADE("FALSE"),
|
||||
// Not used
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
// Not used
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
|
||||
// optimized bandwidth
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
// don't wait for lock during startup
|
||||
.STARTUP_WAIT("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
// 200 MHz input
|
||||
.CLKIN1(clk_200mhz_ibufg),
|
||||
// direct clkfb feeback
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
// 125 MHz, 0 degrees
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
// Not used
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
// Not used
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
// Not used
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
// Not used
|
||||
.CLKOUT4(),
|
||||
// Not used
|
||||
.CLKOUT5(),
|
||||
// Not used
|
||||
.CLKOUT6(),
|
||||
// reset input
|
||||
.RST(mmcm_rst),
|
||||
// don't power down
|
||||
.PWRDWN(1'b0),
|
||||
// locked output
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
wire [3:0] btn_int;
|
||||
|
||||
taxi_debounce_switch #(
|
||||
.WIDTH(4),
|
||||
.N(4),
|
||||
.RATE(125000)
|
||||
)
|
||||
debounce_switch_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(rst_125mhz_int),
|
||||
.in({btn}),
|
||||
.out({btn_int})
|
||||
);
|
||||
|
||||
wire uart_rxd_int;
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(1),
|
||||
.N(2)
|
||||
)
|
||||
sync_signal_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.in({uart_rxd}),
|
||||
.out({uart_rxd_int})
|
||||
);
|
||||
|
||||
// Flash
|
||||
wire qspi_clk_int;
|
||||
wire [3:0] qspi_dq_int;
|
||||
wire [3:0] qspi_dq_i_int;
|
||||
wire [3:0] qspi_dq_o_int;
|
||||
wire [3:0] qspi_dq_oe_int;
|
||||
wire qspi_cs_int;
|
||||
|
||||
reg qspi_clk_reg;
|
||||
reg [3:0] qspi_dq_o_reg;
|
||||
reg [3:0] qspi_dq_oe_reg;
|
||||
reg qspi_cs_reg;
|
||||
|
||||
always_ff @(posedge pcie_user_clk) begin
|
||||
qspi_clk_reg <= qspi_clk_int;
|
||||
qspi_dq_o_reg <= qspi_dq_o_int;
|
||||
qspi_dq_oe_reg <= qspi_dq_oe_int;
|
||||
qspi_cs_reg <= qspi_cs_int;
|
||||
end
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(8),
|
||||
.N(2)
|
||||
)
|
||||
flash_sync_inst (
|
||||
.clk(pcie_user_clk),
|
||||
.in({qspi_dq_int}),
|
||||
.out({qspi_dq_i_int})
|
||||
);
|
||||
|
||||
STARTUPE3
|
||||
startupe3_inst (
|
||||
.CFGCLK(),
|
||||
.CFGMCLK(),
|
||||
.DI(qspi_dq_int),
|
||||
.DO(qspi_dq_o_reg),
|
||||
.DTS(~qspi_dq_oe_reg),
|
||||
.EOS(),
|
||||
.FCSBO(qspi_cs_reg),
|
||||
.FCSBTS(1'b0),
|
||||
.GSR(1'b0),
|
||||
.GTS(1'b0),
|
||||
.KEYCLEARB(1'b1),
|
||||
.PACK(1'b0),
|
||||
.PREQ(),
|
||||
.USRCCLKO(qspi_clk_reg),
|
||||
.USRCCLKTS(1'b0),
|
||||
.USRDONEO(1'b0),
|
||||
.USRDONETS(1'b1)
|
||||
);
|
||||
|
||||
// FPGA boot
|
||||
wire fpga_boot;
|
||||
wire fpga_boot_sync;
|
||||
|
||||
taxi_sync_signal #(
|
||||
.WIDTH(1),
|
||||
.N(2)
|
||||
)
|
||||
fpga_boot_sync_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.in({fpga_boot}),
|
||||
.out({fpga_boot_sync})
|
||||
);
|
||||
|
||||
wire icap_avail;
|
||||
logic [2:0] icap_state_reg = 0;
|
||||
logic icap_csib_reg = 1'b1;
|
||||
logic icap_rdwrb_reg = 1'b0;
|
||||
logic [31:0] icap_di_reg = 32'hffffffff;
|
||||
|
||||
wire [31:0] icap_di_rev;
|
||||
|
||||
assign icap_di_rev[ 7] = icap_di_reg[ 0];
|
||||
assign icap_di_rev[ 6] = icap_di_reg[ 1];
|
||||
assign icap_di_rev[ 5] = icap_di_reg[ 2];
|
||||
assign icap_di_rev[ 4] = icap_di_reg[ 3];
|
||||
assign icap_di_rev[ 3] = icap_di_reg[ 4];
|
||||
assign icap_di_rev[ 2] = icap_di_reg[ 5];
|
||||
assign icap_di_rev[ 1] = icap_di_reg[ 6];
|
||||
assign icap_di_rev[ 0] = icap_di_reg[ 7];
|
||||
|
||||
assign icap_di_rev[15] = icap_di_reg[ 8];
|
||||
assign icap_di_rev[14] = icap_di_reg[ 9];
|
||||
assign icap_di_rev[13] = icap_di_reg[10];
|
||||
assign icap_di_rev[12] = icap_di_reg[11];
|
||||
assign icap_di_rev[11] = icap_di_reg[12];
|
||||
assign icap_di_rev[10] = icap_di_reg[13];
|
||||
assign icap_di_rev[ 9] = icap_di_reg[14];
|
||||
assign icap_di_rev[ 8] = icap_di_reg[15];
|
||||
|
||||
assign icap_di_rev[23] = icap_di_reg[16];
|
||||
assign icap_di_rev[22] = icap_di_reg[17];
|
||||
assign icap_di_rev[21] = icap_di_reg[18];
|
||||
assign icap_di_rev[20] = icap_di_reg[19];
|
||||
assign icap_di_rev[19] = icap_di_reg[20];
|
||||
assign icap_di_rev[18] = icap_di_reg[21];
|
||||
assign icap_di_rev[17] = icap_di_reg[22];
|
||||
assign icap_di_rev[16] = icap_di_reg[23];
|
||||
|
||||
assign icap_di_rev[31] = icap_di_reg[24];
|
||||
assign icap_di_rev[30] = icap_di_reg[25];
|
||||
assign icap_di_rev[29] = icap_di_reg[26];
|
||||
assign icap_di_rev[28] = icap_di_reg[27];
|
||||
assign icap_di_rev[27] = icap_di_reg[28];
|
||||
assign icap_di_rev[26] = icap_di_reg[29];
|
||||
assign icap_di_rev[25] = icap_di_reg[30];
|
||||
assign icap_di_rev[24] = icap_di_reg[31];
|
||||
|
||||
always_ff @(posedge clk_125mhz_int) begin
|
||||
case (icap_state_reg)
|
||||
0: begin
|
||||
icap_state_reg <= 0;
|
||||
icap_csib_reg <= 1'b1;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hffffffff; // dummy word
|
||||
|
||||
if (fpga_boot_sync && icap_avail) begin
|
||||
icap_state_reg <= 1;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hffffffff; // dummy word
|
||||
end
|
||||
end
|
||||
1: begin
|
||||
icap_state_reg <= 2;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hAA995566; // sync word
|
||||
end
|
||||
2: begin
|
||||
icap_state_reg <= 3;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h20000000; // type 1 noop
|
||||
end
|
||||
3: begin
|
||||
icap_state_reg <= 4;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h30008001; // write 1 word to CMD
|
||||
end
|
||||
4: begin
|
||||
icap_state_reg <= 5;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h0000000F; // IPROG
|
||||
end
|
||||
5: begin
|
||||
icap_state_reg <= 0;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h20000000; // type 1 noop
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
ICAPE3
|
||||
icape3_inst (
|
||||
.AVAIL(icap_avail),
|
||||
.CLK(clk_125mhz_int),
|
||||
.CSIB(icap_csib_reg),
|
||||
.I(icap_di_rev),
|
||||
.O(),
|
||||
.PRDONE(),
|
||||
.PRERROR(),
|
||||
.RDWRB(icap_rdwrb_reg)
|
||||
);
|
||||
|
||||
// PCIe
|
||||
localparam AXIS_PCIE_DATA_W = 128;
|
||||
localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32);
|
||||
localparam AXIS_PCIE_RC_USER_W = 75;
|
||||
localparam AXIS_PCIE_RQ_USER_W = 62;
|
||||
localparam AXIS_PCIE_CQ_USER_W = 85;
|
||||
localparam AXIS_PCIE_CC_USER_W = 33;
|
||||
localparam RC_STRADDLE = 1'b0; // AXIS_PCIE_DATA_W >= 256;
|
||||
|
||||
localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6;
|
||||
localparam RQ_SEQ_NUM_EN = 1;
|
||||
|
||||
localparam PCIE_TAG_CNT = AXIS_PCIE_RQ_USER_W == 60 ? 64 : 256;
|
||||
localparam BAR0_APERTURE = 24;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(AXIS_PCIE_DATA_W),
|
||||
.KEEP_EN(1),
|
||||
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||
.USER_EN(1),
|
||||
.USER_W(AXIS_PCIE_CQ_USER_W)
|
||||
) axis_pcie_cq();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(AXIS_PCIE_DATA_W),
|
||||
.KEEP_EN(1),
|
||||
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||
.USER_EN(1),
|
||||
.USER_W(AXIS_PCIE_CC_USER_W)
|
||||
) axis_pcie_cc();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(AXIS_PCIE_DATA_W),
|
||||
.KEEP_EN(1),
|
||||
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||
.USER_EN(1),
|
||||
.USER_W(AXIS_PCIE_RQ_USER_W)
|
||||
) axis_pcie_rq();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(AXIS_PCIE_DATA_W),
|
||||
.KEEP_EN(1),
|
||||
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||
.USER_EN(1),
|
||||
.USER_W(AXIS_PCIE_RC_USER_W)
|
||||
) axis_pcie_rc();
|
||||
|
||||
wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0;
|
||||
wire pcie_rq_seq_num_vld0;
|
||||
wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1;
|
||||
wire pcie_rq_seq_num_vld1;
|
||||
|
||||
wire [2:0] cfg_max_payload;
|
||||
wire [2:0] cfg_max_read_req;
|
||||
wire [3:0] cfg_rcb_status;
|
||||
|
||||
wire [9:0] cfg_mgmt_addr;
|
||||
wire [7:0] cfg_mgmt_function_number;
|
||||
wire cfg_mgmt_write;
|
||||
wire [31:0] cfg_mgmt_write_data;
|
||||
wire [3:0] cfg_mgmt_byte_enable;
|
||||
wire cfg_mgmt_read;
|
||||
wire [31:0] cfg_mgmt_read_data;
|
||||
wire cfg_mgmt_read_write_done;
|
||||
|
||||
wire [7:0] cfg_fc_ph;
|
||||
wire [11:0] cfg_fc_pd;
|
||||
wire [7:0] cfg_fc_nph;
|
||||
wire [11:0] cfg_fc_npd;
|
||||
wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire cfg_ext_read_received;
|
||||
wire cfg_ext_write_received;
|
||||
wire [9:0] cfg_ext_register_number;
|
||||
wire [7:0] cfg_ext_function_number;
|
||||
wire [31:0] cfg_ext_write_data;
|
||||
wire [3:0] cfg_ext_write_byte_enable;
|
||||
wire [31:0] cfg_ext_read_data;
|
||||
wire cfg_ext_read_data_valid;
|
||||
|
||||
// wire [3:0] cfg_interrupt_msix_enable;
|
||||
// wire [3:0] cfg_interrupt_msix_mask;
|
||||
// wire [251:0] cfg_interrupt_msix_vf_enable;
|
||||
// wire [251:0] cfg_interrupt_msix_vf_mask;
|
||||
// wire [63:0] cfg_interrupt_msix_address;
|
||||
// wire [31:0] cfg_interrupt_msix_data;
|
||||
// wire cfg_interrupt_msix_int;
|
||||
// wire [1:0] cfg_interrupt_msix_vec_pending;
|
||||
// wire cfg_interrupt_msix_vec_pending_status;
|
||||
// wire cfg_interrupt_msix_sent;
|
||||
// wire cfg_interrupt_msix_fail;
|
||||
// wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [1:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [1:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [7:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire stat_err_cor;
|
||||
wire stat_err_uncor;
|
||||
|
||||
wire pcie_sys_clk;
|
||||
wire pcie_sys_clk_gt;
|
||||
|
||||
IBUFDS_GTE4 #(
|
||||
.REFCLK_HROW_CK_SEL(2'b00)
|
||||
)
|
||||
ibufds_gte4_pcie_refclk_inst (
|
||||
.I (pcie_refclk_p),
|
||||
.IB (pcie_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (pcie_sys_clk_gt),
|
||||
.ODIV2 (pcie_sys_clk)
|
||||
);
|
||||
|
||||
pcie4_uscale_plus_0
|
||||
pcie4_uscale_plus_inst (
|
||||
.pci_exp_txn(pcie_tx_n),
|
||||
.pci_exp_txp(pcie_tx_p),
|
||||
.pci_exp_rxn(pcie_rx_n),
|
||||
.pci_exp_rxp(pcie_rx_p),
|
||||
.user_clk(pcie_user_clk),
|
||||
.user_reset(pcie_user_rst),
|
||||
.user_lnk_up(),
|
||||
|
||||
.s_axis_rq_tdata(axis_pcie_rq.tdata),
|
||||
.s_axis_rq_tkeep(axis_pcie_rq.tkeep),
|
||||
.s_axis_rq_tlast(axis_pcie_rq.tlast),
|
||||
.s_axis_rq_tready(axis_pcie_rq.tready),
|
||||
.s_axis_rq_tuser(axis_pcie_rq.tuser),
|
||||
.s_axis_rq_tvalid(axis_pcie_rq.tvalid),
|
||||
|
||||
.m_axis_rc_tdata(axis_pcie_rc.tdata),
|
||||
.m_axis_rc_tkeep(axis_pcie_rc.tkeep),
|
||||
.m_axis_rc_tlast(axis_pcie_rc.tlast),
|
||||
.m_axis_rc_tready(axis_pcie_rc.tready),
|
||||
.m_axis_rc_tuser(axis_pcie_rc.tuser),
|
||||
.m_axis_rc_tvalid(axis_pcie_rc.tvalid),
|
||||
|
||||
.m_axis_cq_tdata(axis_pcie_cq.tdata),
|
||||
.m_axis_cq_tkeep(axis_pcie_cq.tkeep),
|
||||
.m_axis_cq_tlast(axis_pcie_cq.tlast),
|
||||
.m_axis_cq_tready(axis_pcie_cq.tready),
|
||||
.m_axis_cq_tuser(axis_pcie_cq.tuser),
|
||||
.m_axis_cq_tvalid(axis_pcie_cq.tvalid),
|
||||
|
||||
.s_axis_cc_tdata(axis_pcie_cc.tdata),
|
||||
.s_axis_cc_tkeep(axis_pcie_cc.tkeep),
|
||||
.s_axis_cc_tlast(axis_pcie_cc.tlast),
|
||||
.s_axis_cc_tready(axis_pcie_cc.tready),
|
||||
.s_axis_cc_tuser(axis_pcie_cc.tuser),
|
||||
.s_axis_cc_tvalid(axis_pcie_cc.tvalid),
|
||||
|
||||
.pcie_rq_seq_num0(pcie_rq_seq_num0),
|
||||
.pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0),
|
||||
.pcie_rq_seq_num1(pcie_rq_seq_num1),
|
||||
.pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1),
|
||||
.pcie_rq_tag0(),
|
||||
.pcie_rq_tag1(),
|
||||
.pcie_rq_tag_av(),
|
||||
.pcie_rq_tag_vld0(),
|
||||
.pcie_rq_tag_vld1(),
|
||||
|
||||
.pcie_tfc_nph_av(),
|
||||
.pcie_tfc_npd_av(),
|
||||
|
||||
.pcie_cq_np_req(1'b1),
|
||||
.pcie_cq_np_req_count(),
|
||||
|
||||
.cfg_phy_link_down(),
|
||||
.cfg_phy_link_status(),
|
||||
.cfg_negotiated_width(),
|
||||
.cfg_current_speed(),
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_function_status(),
|
||||
.cfg_function_power_state(),
|
||||
.cfg_vf_status(),
|
||||
.cfg_vf_power_state(),
|
||||
.cfg_link_power_state(),
|
||||
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_function_number(cfg_mgmt_function_number),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
.cfg_mgmt_debug_access(1'b0),
|
||||
|
||||
.cfg_err_cor_out(),
|
||||
.cfg_err_nonfatal_out(),
|
||||
.cfg_err_fatal_out(),
|
||||
.cfg_local_error_valid(),
|
||||
.cfg_local_error_out(),
|
||||
.cfg_ltssm_state(),
|
||||
.cfg_rx_pm_state(),
|
||||
.cfg_tx_pm_state(),
|
||||
.cfg_rcb_status(cfg_rcb_status),
|
||||
.cfg_obff_enable(),
|
||||
.cfg_pl_status_change(),
|
||||
.cfg_tph_requester_enable(),
|
||||
.cfg_tph_st_mode(),
|
||||
.cfg_vf_tph_requester_enable(),
|
||||
.cfg_vf_tph_st_mode(),
|
||||
|
||||
.cfg_msg_received(),
|
||||
.cfg_msg_received_data(),
|
||||
.cfg_msg_received_type(),
|
||||
.cfg_msg_transmit(1'b0),
|
||||
.cfg_msg_transmit_type(3'd0),
|
||||
.cfg_msg_transmit_data(32'd0),
|
||||
.cfg_msg_transmit_done(),
|
||||
|
||||
.cfg_fc_ph(cfg_fc_ph),
|
||||
.cfg_fc_pd(cfg_fc_pd),
|
||||
.cfg_fc_nph(cfg_fc_nph),
|
||||
.cfg_fc_npd(cfg_fc_npd),
|
||||
.cfg_fc_cplh(cfg_fc_cplh),
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_dsn(64'd0),
|
||||
|
||||
.cfg_bus_number(),
|
||||
|
||||
.cfg_power_state_change_ack(1'b1),
|
||||
.cfg_power_state_change_interrupt(),
|
||||
|
||||
.cfg_err_cor_in(stat_err_cor),
|
||||
.cfg_err_uncor_in(stat_err_uncor),
|
||||
.cfg_flr_in_process(),
|
||||
.cfg_flr_done(4'd0),
|
||||
.cfg_vf_flr_in_process(),
|
||||
.cfg_vf_flr_func_num(8'd0),
|
||||
.cfg_vf_flr_done(8'd0),
|
||||
|
||||
.cfg_link_training_enable(1'b1),
|
||||
|
||||
.cfg_ext_read_received(cfg_ext_read_received),
|
||||
.cfg_ext_write_received(cfg_ext_write_received),
|
||||
.cfg_ext_register_number(cfg_ext_register_number),
|
||||
.cfg_ext_function_number(cfg_ext_function_number),
|
||||
.cfg_ext_write_data(cfg_ext_write_data),
|
||||
.cfg_ext_write_byte_enable(cfg_ext_write_byte_enable),
|
||||
.cfg_ext_read_data(cfg_ext_read_data),
|
||||
.cfg_ext_read_data_valid(cfg_ext_read_data_valid),
|
||||
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
// .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
// .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
// .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
// .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
// .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
// .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
// .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
// .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
// .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
// .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
||||
// .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
||||
// .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
.cfg_pm_aspm_tx_l0s_entry_disable(1'b0),
|
||||
|
||||
.cfg_hot_reset_out(),
|
||||
|
||||
.cfg_config_space_enable(1'b1),
|
||||
.cfg_req_pm_transition_l23_ready(1'b0),
|
||||
.cfg_hot_reset_in(1'b0),
|
||||
|
||||
.cfg_ds_port_number(8'd0),
|
||||
.cfg_ds_bus_number(8'd0),
|
||||
.cfg_ds_device_number(5'd0),
|
||||
|
||||
.sys_clk(pcie_sys_clk),
|
||||
.sys_clk_gt(pcie_sys_clk_gt),
|
||||
.sys_reset(pcie_reset_n),
|
||||
|
||||
.phy_rdy_out()
|
||||
);
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
// FW ID
|
||||
.FPGA_ID(FPGA_ID),
|
||||
.FW_ID(FW_ID),
|
||||
.FW_VER(FW_VER),
|
||||
.BOARD_ID(BOARD_ID),
|
||||
.BOARD_VER(BOARD_VER),
|
||||
.BUILD_DATE(BUILD_DATE),
|
||||
.GIT_HASH(GIT_HASH),
|
||||
.RELEASE_INFO(RELEASE_INFO),
|
||||
|
||||
// PTP configuration
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
|
||||
// PCIe interface configuration
|
||||
.RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
.AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W),
|
||||
.AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W),
|
||||
|
||||
// MAC configuration
|
||||
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
|
||||
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
|
||||
.MAC_DATA_W(MAC_DATA_W)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz_int),
|
||||
.rst_125mhz(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.btn(btn_int),
|
||||
.led(led),
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
.uart_rxd(uart_rxd_int),
|
||||
.uart_txd(uart_txd),
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T RGMII
|
||||
*/
|
||||
// .phy_rgmii_rx_clk(phy_rx_clk),
|
||||
// .phy_rgmii_rxd(phy_rxd_int),
|
||||
// .phy_rgmii_rx_ctl(phy_rx_ctl_int),
|
||||
// .phy_rgmii_tx_clk(phy_tx_clk),
|
||||
// .phy_rgmii_txd(phy_txd),
|
||||
// .phy_rgmii_tx_ctl(phy_tx_ctl),
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
.qsfp_rx_p(qsfp_rx_p),
|
||||
.qsfp_rx_n(qsfp_rx_n),
|
||||
.qsfp_tx_p(qsfp_tx_p),
|
||||
.qsfp_tx_n(qsfp_tx_n),
|
||||
.qsfp_mgt_refclk_p(qsfp_mgt_refclk_p),
|
||||
.qsfp_mgt_refclk_n(qsfp_mgt_refclk_n),
|
||||
.qsfp_modsell(qsfp_modsell),
|
||||
.qsfp_resetl(qsfp_resetl),
|
||||
.qsfp_modprsl(qsfp_modprsl),
|
||||
.qsfp_intl(qsfp_intl),
|
||||
.qsfp_lpmode(qsfp_lpmode),
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
.pcie_clk(pcie_user_clk),
|
||||
.pcie_rst(pcie_user_rst),
|
||||
.s_axis_pcie_cq(axis_pcie_cq),
|
||||
.m_axis_pcie_cc(axis_pcie_cc),
|
||||
.m_axis_pcie_rq(axis_pcie_rq),
|
||||
.s_axis_pcie_rc(axis_pcie_rc),
|
||||
|
||||
.pcie_rq_seq_num0(pcie_rq_seq_num0),
|
||||
.pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0),
|
||||
.pcie_rq_seq_num1(pcie_rq_seq_num1),
|
||||
.pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1),
|
||||
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_rcb_status(cfg_rcb_status),
|
||||
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_function_number(cfg_mgmt_function_number),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
|
||||
.cfg_fc_ph(cfg_fc_ph),
|
||||
.cfg_fc_pd(cfg_fc_pd),
|
||||
.cfg_fc_nph(cfg_fc_nph),
|
||||
.cfg_fc_npd(cfg_fc_npd),
|
||||
.cfg_fc_cplh(cfg_fc_cplh),
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_ext_read_received(cfg_ext_read_received),
|
||||
.cfg_ext_write_received(cfg_ext_write_received),
|
||||
.cfg_ext_register_number(cfg_ext_register_number),
|
||||
.cfg_ext_function_number(cfg_ext_function_number),
|
||||
.cfg_ext_write_data(cfg_ext_write_data),
|
||||
.cfg_ext_write_byte_enable(cfg_ext_write_byte_enable),
|
||||
.cfg_ext_read_data(cfg_ext_read_data),
|
||||
.cfg_ext_read_data_valid(cfg_ext_read_data_valid),
|
||||
|
||||
// .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
// .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
// .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
// .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
// .cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
// .cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
// .cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
// .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
// .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
// .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
// .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
// .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
.fpga_boot(fpga_boot),
|
||||
.qspi_clk(qspi_clk_int),
|
||||
.qspi_dq_i(qspi_dq_i_int),
|
||||
.qspi_dq_o(qspi_dq_o_int),
|
||||
.qspi_dq_oe(qspi_dq_oe_int),
|
||||
.qspi_cs(qspi_cs_int)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
763
src/cndm/board/RK_XCKU5P_F/fpga/rtl/fpga_core.sv
Normal file
763
src/cndm/board/RK_XCKU5P_F/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,763 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic
|
||||
*/
|
||||
module fpga_core #
|
||||
(
|
||||
// simulation (set to avoid vendor primitives)
|
||||
parameter logic SIM = 1'b0,
|
||||
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||
parameter string VENDOR = "XILINX",
|
||||
// device family
|
||||
parameter string FAMILY = "kintexuplus",
|
||||
|
||||
// FW ID
|
||||
parameter FPGA_ID = 32'h4A62093,
|
||||
parameter FW_ID = 32'h0000C001,
|
||||
parameter FW_VER = 32'h000_01_000,
|
||||
parameter BOARD_ID = 32'h1234_9005,
|
||||
parameter BOARD_VER = 32'h001_00_000,
|
||||
parameter BUILD_DATE = 32'd602976000,
|
||||
parameter GIT_HASH = 32'h5f87c2e8,
|
||||
parameter RELEASE_INFO = 32'h00000000,
|
||||
|
||||
// PTP configuration
|
||||
parameter logic PTP_TS_EN = 1'b1,
|
||||
|
||||
// PCIe interface configuration
|
||||
parameter RQ_SEQ_NUM_W = 6,
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
parameter AXIL_CTRL_DATA_W = 32,
|
||||
parameter AXIL_CTRL_ADDR_W = 24,
|
||||
|
||||
// MAC configuration
|
||||
parameter logic CFG_LOW_LATENCY = 1'b1,
|
||||
parameter logic COMBINED_MAC_PCS = 1'b1,
|
||||
parameter MAC_DATA_W = 64
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
input wire logic clk_125mhz,
|
||||
input wire logic rst_125mhz,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
input wire logic [3:0] btn,
|
||||
output wire logic [3:0] led,
|
||||
|
||||
/*
|
||||
* UART: 3000000 bps, 8N1
|
||||
*/
|
||||
input wire logic uart_rxd,
|
||||
output wire logic uart_txd,
|
||||
|
||||
/*
|
||||
* Ethernet: 1000BASE-T RGMII
|
||||
*/
|
||||
// input wire logic phy_rgmii_rx_clk,
|
||||
// input wire logic [3:0] phy_rgmii_rxd,
|
||||
// input wire logic phy_rgmii_rx_ctl,
|
||||
// output wire logic phy_rgmii_tx_clk,
|
||||
// output wire logic [3:0] phy_rgmii_txd,
|
||||
// output wire logic phy_rgmii_tx_ctl,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
input wire logic qsfp_rx_p[4],
|
||||
input wire logic qsfp_rx_n[4],
|
||||
output wire logic qsfp_tx_p[4],
|
||||
output wire logic qsfp_tx_n[4],
|
||||
input wire logic qsfp_mgt_refclk_p,
|
||||
input wire logic qsfp_mgt_refclk_n,
|
||||
output wire logic qsfp_modsell,
|
||||
output wire logic qsfp_resetl,
|
||||
input wire logic qsfp_modprsl,
|
||||
input wire logic qsfp_intl,
|
||||
output wire logic qsfp_lpmode,
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
input wire logic pcie_clk,
|
||||
input wire logic pcie_rst,
|
||||
taxi_axis_if.snk s_axis_pcie_cq,
|
||||
taxi_axis_if.src m_axis_pcie_cc,
|
||||
taxi_axis_if.src m_axis_pcie_rq,
|
||||
taxi_axis_if.snk s_axis_pcie_rc,
|
||||
|
||||
input wire logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0,
|
||||
input wire logic pcie_rq_seq_num_vld0,
|
||||
input wire logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1,
|
||||
input wire logic pcie_rq_seq_num_vld1,
|
||||
|
||||
input wire logic [2:0] cfg_max_payload,
|
||||
input wire logic [2:0] cfg_max_read_req,
|
||||
input wire logic [3:0] cfg_rcb_status,
|
||||
|
||||
output wire logic [9:0] cfg_mgmt_addr,
|
||||
output wire logic [7:0] cfg_mgmt_function_number,
|
||||
output wire logic cfg_mgmt_write,
|
||||
output wire logic [31:0] cfg_mgmt_write_data,
|
||||
output wire logic [3:0] cfg_mgmt_byte_enable,
|
||||
output wire logic cfg_mgmt_read,
|
||||
output wire logic [31:0] cfg_mgmt_read_data,
|
||||
input wire logic cfg_mgmt_read_write_done,
|
||||
|
||||
input wire logic [7:0] cfg_fc_ph,
|
||||
input wire logic [11:0] cfg_fc_pd,
|
||||
input wire logic [7:0] cfg_fc_nph,
|
||||
input wire logic [11:0] cfg_fc_npd,
|
||||
input wire logic [7:0] cfg_fc_cplh,
|
||||
input wire logic [11:0] cfg_fc_cpld,
|
||||
output wire logic [2:0] cfg_fc_sel,
|
||||
|
||||
input wire logic cfg_ext_read_received,
|
||||
input wire logic cfg_ext_write_received,
|
||||
input wire logic [9:0] cfg_ext_register_number,
|
||||
input wire logic [7:0] cfg_ext_function_number,
|
||||
input wire logic [31:0] cfg_ext_write_data,
|
||||
input wire logic [3:0] cfg_ext_write_byte_enable,
|
||||
output wire logic [31:0] cfg_ext_read_data,
|
||||
output wire logic cfg_ext_read_data_valid,
|
||||
|
||||
input wire logic [3:0] cfg_interrupt_msi_enable,
|
||||
input wire logic [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire logic cfg_interrupt_msi_mask_update,
|
||||
input wire logic [31:0] cfg_interrupt_msi_data,
|
||||
output wire logic [1:0] cfg_interrupt_msi_select,
|
||||
output wire logic [31:0] cfg_interrupt_msi_int,
|
||||
output wire logic [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire logic cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire logic [1:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire logic cfg_interrupt_msi_sent,
|
||||
input wire logic cfg_interrupt_msi_fail,
|
||||
output wire logic [2:0] cfg_interrupt_msi_attr,
|
||||
output wire logic cfg_interrupt_msi_tph_present,
|
||||
output wire logic [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire logic [7:0] cfg_interrupt_msi_tph_st_tag,
|
||||
output wire logic [7:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
output wire logic fpga_boot,
|
||||
output wire logic qspi_clk,
|
||||
input wire logic [3:0] qspi_dq_i,
|
||||
output wire logic [3:0] qspi_dq_o,
|
||||
output wire logic [3:0] qspi_dq_oe,
|
||||
output wire logic qspi_cs
|
||||
);
|
||||
|
||||
localparam logic PTP_TS_FMT_TOD = 1'b0;
|
||||
localparam PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 48;
|
||||
|
||||
// flashing via PCIe VPD
|
||||
pyrite_pcie_us_vpd_qspi #(
|
||||
.VPD_CAP_ID(8'h03),
|
||||
.VPD_CAP_OFFSET(8'hB0),
|
||||
.VPD_CAP_NEXT(8'h00),
|
||||
|
||||
// FW ID
|
||||
.FPGA_ID(FPGA_ID),
|
||||
.FW_ID(FW_ID),
|
||||
.FW_VER(FW_VER),
|
||||
.BOARD_ID(BOARD_ID),
|
||||
.BOARD_VER(BOARD_VER),
|
||||
.BUILD_DATE(BUILD_DATE),
|
||||
.GIT_HASH(GIT_HASH),
|
||||
.RELEASE_INFO(RELEASE_INFO),
|
||||
|
||||
// Flash
|
||||
.FLASH_SEG_COUNT(4),
|
||||
.FLASH_SEG_DEFAULT(1),
|
||||
.FLASH_SEG_FALLBACK(0),
|
||||
.FLASH_SEG0_SIZE(32'h00000000),
|
||||
.FLASH_DATA_W(4),
|
||||
.FLASH_DUAL_QSPI(1'b0)
|
||||
)
|
||||
pyrite_inst (
|
||||
.clk(pcie_clk),
|
||||
.rst(pcie_rst),
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
.cfg_ext_read_received(cfg_ext_read_received),
|
||||
.cfg_ext_write_received(cfg_ext_write_received),
|
||||
.cfg_ext_register_number(cfg_ext_register_number),
|
||||
.cfg_ext_function_number(cfg_ext_function_number),
|
||||
.cfg_ext_write_data(cfg_ext_write_data),
|
||||
.cfg_ext_write_byte_enable(cfg_ext_write_byte_enable),
|
||||
.cfg_ext_read_data(cfg_ext_read_data),
|
||||
.cfg_ext_read_data_valid(cfg_ext_read_data_valid),
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
.fpga_boot(fpga_boot),
|
||||
.qspi_clk(qspi_clk),
|
||||
.qspi_0_dq_i(qspi_dq_i),
|
||||
.qspi_0_dq_o(qspi_dq_o),
|
||||
.qspi_0_dq_oe(qspi_dq_oe),
|
||||
.qspi_0_cs(qspi_cs),
|
||||
.qspi_1_dq_i('0),
|
||||
.qspi_1_dq_o(),
|
||||
.qspi_1_dq_oe(),
|
||||
.qspi_1_cs()
|
||||
);
|
||||
|
||||
// XFCP
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
|
||||
|
||||
taxi_xfcp_if_uart #(
|
||||
.TX_FIFO_DEPTH(512),
|
||||
.RX_FIFO_DEPTH(512)
|
||||
)
|
||||
xfcp_if_uart_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* UART interface
|
||||
*/
|
||||
.uart_rxd(uart_rxd),
|
||||
.uart_txd(uart_txd),
|
||||
|
||||
/*
|
||||
* XFCP downstream interface
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_ds),
|
||||
.xfcp_dsp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.prescale(16'(125000000/3000000))
|
||||
);
|
||||
|
||||
localparam XFCP_PORTS = 2;
|
||||
|
||||
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[XFCP_PORTS](), xfcp_sw_us[XFCP_PORTS]();
|
||||
|
||||
taxi_xfcp_switch #(
|
||||
.XFCP_ID_STR("RK-XCKU5P-F"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR("Taxi example"),
|
||||
.PORTS($size(xfcp_sw_us))
|
||||
)
|
||||
xfcp_sw_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_ds),
|
||||
.xfcp_usp_us(xfcp_us),
|
||||
|
||||
/*
|
||||
* XFCP downstream ports
|
||||
*/
|
||||
.xfcp_dsp_ds(xfcp_sw_ds),
|
||||
.xfcp_dsp_us(xfcp_sw_us)
|
||||
);
|
||||
|
||||
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
|
||||
|
||||
taxi_xfcp_mod_stats #(
|
||||
.XFCP_ID_STR("Statistics"),
|
||||
.XFCP_EXT_ID(0),
|
||||
.XFCP_EXT_ID_STR(""),
|
||||
.STAT_COUNT_W(64),
|
||||
.STAT_PIPELINE(2)
|
||||
)
|
||||
xfcp_stats_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_sw_ds[0]),
|
||||
.xfcp_usp_us(xfcp_sw_us[0]),
|
||||
|
||||
/*
|
||||
* Statistics increment input
|
||||
*/
|
||||
.s_axis_stat(axis_stat)
|
||||
);
|
||||
|
||||
// QSFP28
|
||||
assign qsfp_modsell = 1'b0;
|
||||
assign qsfp_resetl = 1'b1;
|
||||
assign qsfp_lpmode = 1'b0;
|
||||
|
||||
wire qsfp_tx_clk[4];
|
||||
wire qsfp_tx_rst[4];
|
||||
wire qsfp_rx_clk[4];
|
||||
wire qsfp_rx_rst[4];
|
||||
|
||||
wire qsfp_rx_status[4];
|
||||
|
||||
assign led[0] = qsfp_rx_status[0];
|
||||
assign led[1] = qsfp_rx_status[1];
|
||||
assign led[2] = qsfp_rx_status[2];
|
||||
assign led[3] = qsfp_rx_status[3];
|
||||
|
||||
wire qsfp_gtpowergood;
|
||||
|
||||
wire qsfp_mgt_refclk;
|
||||
wire qsfp_mgt_refclk_int;
|
||||
wire qsfp_mgt_refclk_bufg;
|
||||
|
||||
wire qsfp_rst;
|
||||
|
||||
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_qsfp_tx[4]();
|
||||
taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[4]();
|
||||
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1+PTP_TS_W)) axis_qsfp_rx[4]();
|
||||
|
||||
if (SIM) begin
|
||||
|
||||
assign qsfp_mgt_refclk = qsfp_mgt_refclk_p;
|
||||
assign qsfp_mgt_refclk_int = qsfp_mgt_refclk_p;
|
||||
assign qsfp_mgt_refclk_bufg = qsfp_mgt_refclk_int;
|
||||
|
||||
end else begin
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_qsfp_mgt_refclk_inst (
|
||||
.I (qsfp_mgt_refclk_p),
|
||||
.IB (qsfp_mgt_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (qsfp_mgt_refclk),
|
||||
.ODIV2 (qsfp_mgt_refclk_int)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_qsfp_mgt_refclk_inst (
|
||||
.CE (qsfp_gtpowergood),
|
||||
.CEMASK (1'b1),
|
||||
.CLR (1'b0),
|
||||
.CLRMASK (1'b1),
|
||||
.DIV (3'd0),
|
||||
.I (qsfp_mgt_refclk_int),
|
||||
.O (qsfp_mgt_refclk_bufg)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
taxi_sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
qsfp_sync_reset_inst (
|
||||
.clk(qsfp_mgt_refclk_bufg),
|
||||
.rst(rst_125mhz),
|
||||
.out(qsfp_rst)
|
||||
);
|
||||
|
||||
taxi_apb_if #(
|
||||
.ADDR_W(18),
|
||||
.DATA_W(16)
|
||||
)
|
||||
gt_apb_ctrl();
|
||||
|
||||
taxi_xfcp_mod_apb #(
|
||||
.XFCP_EXT_ID_STR("GTY CTRL")
|
||||
)
|
||||
xfcp_mod_apb_inst (
|
||||
.clk(clk_125mhz),
|
||||
.rst(rst_125mhz),
|
||||
|
||||
/*
|
||||
* XFCP upstream port
|
||||
*/
|
||||
.xfcp_usp_ds(xfcp_sw_ds[1]),
|
||||
.xfcp_usp_us(xfcp_sw_us[1]),
|
||||
|
||||
/*
|
||||
* APB master interface
|
||||
*/
|
||||
.m_apb(gt_apb_ctrl)
|
||||
);
|
||||
|
||||
wire ptp_clk = qsfp_mgt_refclk_bufg;
|
||||
wire ptp_rst = qsfp_rst;
|
||||
wire ptp_sample_clk = clk_125mhz;
|
||||
wire ptp_td_sd;
|
||||
wire ptp_pps;
|
||||
wire ptp_pps_str;
|
||||
|
||||
taxi_eth_mac_25g_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
.CNT(4),
|
||||
|
||||
// GT config
|
||||
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
|
||||
|
||||
// GT type
|
||||
.GT_TYPE("GTY"),
|
||||
|
||||
// MAC/PHY config
|
||||
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
|
||||
.DATA_W(MAC_DATA_W),
|
||||
.PADDING_EN(1'b1),
|
||||
.DIC_EN(1'b1),
|
||||
.MIN_FRAME_LEN(64),
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TD_EN(PTP_TS_EN),
|
||||
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
|
||||
.PTP_TS_W(PTP_TS_W),
|
||||
.PTP_TD_SDI_PIPELINE(2),
|
||||
.PRBS31_EN(1'b0),
|
||||
.TX_SERDES_PIPELINE(1),
|
||||
.RX_SERDES_PIPELINE(1),
|
||||
.COUNT_125US(125000/6.4),
|
||||
.STAT_EN(1),
|
||||
.STAT_TX_LEVEL(1),
|
||||
.STAT_RX_LEVEL(1),
|
||||
.STAT_ID_BASE(16+16),
|
||||
.STAT_UPDATE_PERIOD(1024),
|
||||
.STAT_STR_EN(1),
|
||||
.STAT_PREFIX_STR('{"QSFP.1", "QSFP.2", "QSFP.3", "QSFP.4"})
|
||||
)
|
||||
qsfp_mac_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz),
|
||||
.xcvr_ctrl_rst(qsfp_rst),
|
||||
|
||||
/*
|
||||
* Transceiver control
|
||||
*/
|
||||
.s_apb_ctrl(gt_apb_ctrl),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(qsfp_gtpowergood),
|
||||
.xcvr_gtrefclk00_in(qsfp_mgt_refclk),
|
||||
.xcvr_qpll0pd_in(1'b0),
|
||||
.xcvr_qpll0reset_in(1'b0),
|
||||
.xcvr_qpll0pcierate_in(3'd0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
.xcvr_gtrefclk01_in(qsfp_mgt_refclk),
|
||||
.xcvr_qpll1pd_in(1'b0),
|
||||
.xcvr_qpll1reset_in(1'b0),
|
||||
.xcvr_qpll1pcierate_in(3'd0),
|
||||
.xcvr_qpll1lock_out(),
|
||||
.xcvr_qpll1clk_out(),
|
||||
.xcvr_qpll1refclk_out(),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(qsfp_tx_p),
|
||||
.xcvr_txn(qsfp_tx_n),
|
||||
.xcvr_rxp(qsfp_rx_p),
|
||||
.xcvr_rxn(qsfp_rx_n),
|
||||
|
||||
/*
|
||||
* MAC clocks
|
||||
*/
|
||||
.rx_clk(qsfp_rx_clk),
|
||||
.rx_rst_in('{4{1'b0}}),
|
||||
.rx_rst_out(qsfp_rx_rst),
|
||||
.tx_clk(qsfp_tx_clk),
|
||||
.tx_rst_in('{4{1'b0}}),
|
||||
.tx_rst_out(qsfp_tx_rst),
|
||||
|
||||
/*
|
||||
* Transmit interface (AXI stream)
|
||||
*/
|
||||
.s_axis_tx(axis_qsfp_tx),
|
||||
.m_axis_tx_cpl(axis_qsfp_tx_cpl),
|
||||
|
||||
/*
|
||||
* Receive interface (AXI stream)
|
||||
*/
|
||||
.m_axis_rx(axis_qsfp_rx),
|
||||
|
||||
/*
|
||||
* PTP clock
|
||||
*/
|
||||
.ptp_clk(ptp_clk),
|
||||
.ptp_rst(ptp_rst),
|
||||
.ptp_sample_clk(ptp_sample_clk),
|
||||
.ptp_td_sdi(ptp_td_sd),
|
||||
.tx_ptp_ts_in('{4{'0}}),
|
||||
.tx_ptp_ts_out(),
|
||||
.tx_ptp_ts_step_out(),
|
||||
.tx_ptp_locked(),
|
||||
.rx_ptp_ts_in('{4{'0}}),
|
||||
.rx_ptp_ts_out(),
|
||||
.rx_ptp_ts_step_out(),
|
||||
.rx_ptp_locked(),
|
||||
|
||||
/*
|
||||
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||
*/
|
||||
.tx_lfc_req('{4{1'b0}}),
|
||||
.tx_lfc_resend('{4{1'b0}}),
|
||||
.rx_lfc_en('{4{1'b0}}),
|
||||
.rx_lfc_req(),
|
||||
.rx_lfc_ack('{4{1'b0}}),
|
||||
|
||||
/*
|
||||
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||
*/
|
||||
.tx_pfc_req('{4{'0}}),
|
||||
.tx_pfc_resend('{4{1'b0}}),
|
||||
.rx_pfc_en('{4{'0}}),
|
||||
.rx_pfc_req(),
|
||||
.rx_pfc_ack('{4{'0}}),
|
||||
|
||||
/*
|
||||
* Pause interface
|
||||
*/
|
||||
.tx_lfc_pause_en('{4{1'b0}}),
|
||||
.tx_pause_req('{4{1'b0}}),
|
||||
.tx_pause_ack(),
|
||||
|
||||
/*
|
||||
* Statistics
|
||||
*/
|
||||
.stat_clk(clk_125mhz),
|
||||
.stat_rst(rst_125mhz),
|
||||
.m_axis_stat(axis_stat),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.tx_start_packet(),
|
||||
.stat_tx_byte(),
|
||||
.stat_tx_pkt_len(),
|
||||
.stat_tx_pkt_ucast(),
|
||||
.stat_tx_pkt_mcast(),
|
||||
.stat_tx_pkt_bcast(),
|
||||
.stat_tx_pkt_vlan(),
|
||||
.stat_tx_pkt_good(),
|
||||
.stat_tx_pkt_bad(),
|
||||
.stat_tx_err_oversize(),
|
||||
.stat_tx_err_user(),
|
||||
.stat_tx_err_underflow(),
|
||||
.rx_start_packet(),
|
||||
.rx_error_count(),
|
||||
.rx_block_lock(),
|
||||
.rx_high_ber(),
|
||||
.rx_status(qsfp_rx_status),
|
||||
.stat_rx_byte(),
|
||||
.stat_rx_pkt_len(),
|
||||
.stat_rx_pkt_fragment(),
|
||||
.stat_rx_pkt_jabber(),
|
||||
.stat_rx_pkt_ucast(),
|
||||
.stat_rx_pkt_mcast(),
|
||||
.stat_rx_pkt_bcast(),
|
||||
.stat_rx_pkt_vlan(),
|
||||
.stat_rx_pkt_good(),
|
||||
.stat_rx_pkt_bad(),
|
||||
.stat_rx_err_oversize(),
|
||||
.stat_rx_err_bad_fcs(),
|
||||
.stat_rx_err_bad_block(),
|
||||
.stat_rx_err_framing(),
|
||||
.stat_rx_err_preamble(),
|
||||
.stat_rx_fifo_drop('{4{1'b0}}),
|
||||
.stat_tx_mcf(),
|
||||
.stat_rx_mcf(),
|
||||
.stat_tx_lfc_pkt(),
|
||||
.stat_tx_lfc_xon(),
|
||||
.stat_tx_lfc_xoff(),
|
||||
.stat_tx_lfc_paused(),
|
||||
.stat_tx_pfc_pkt(),
|
||||
.stat_tx_pfc_xon(),
|
||||
.stat_tx_pfc_xoff(),
|
||||
.stat_tx_pfc_paused(),
|
||||
.stat_rx_lfc_pkt(),
|
||||
.stat_rx_lfc_xon(),
|
||||
.stat_rx_lfc_xoff(),
|
||||
.stat_rx_lfc_paused(),
|
||||
.stat_rx_pfc_pkt(),
|
||||
.stat_rx_pfc_xon(),
|
||||
.stat_rx_pfc_xoff(),
|
||||
.stat_rx_pfc_paused(),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.cfg_tx_max_pkt_len('{4{16'd9218}}),
|
||||
.cfg_tx_ifg('{4{8'd12}}),
|
||||
.cfg_tx_enable('{4{1'b1}}),
|
||||
.cfg_rx_max_pkt_len('{4{16'd9218}}),
|
||||
.cfg_rx_enable('{4{1'b1}}),
|
||||
.cfg_tx_prbs31_enable('{4{1'b0}}),
|
||||
.cfg_rx_prbs31_enable('{4{1'b0}}),
|
||||
.cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_mcf_rx_check_eth_dst_mcast('{4{1'b1}}),
|
||||
.cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_dst_ucast('{4{1'b0}}),
|
||||
.cfg_mcf_rx_eth_src('{4{48'd0}}),
|
||||
.cfg_mcf_rx_check_eth_src('{4{1'b0}}),
|
||||
.cfg_mcf_rx_eth_type('{4{16'h8808}}),
|
||||
.cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
|
||||
.cfg_mcf_rx_check_opcode_lfc('{4{1'b1}}),
|
||||
.cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
|
||||
.cfg_mcf_rx_check_opcode_pfc('{4{1'b1}}),
|
||||
.cfg_mcf_rx_forward('{4{1'b0}}),
|
||||
.cfg_mcf_rx_enable('{4{1'b0}}),
|
||||
.cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_lfc_eth_type('{4{16'h8808}}),
|
||||
.cfg_tx_lfc_opcode('{4{16'h0001}}),
|
||||
.cfg_tx_lfc_en('{4{1'b0}}),
|
||||
.cfg_tx_lfc_quanta('{4{16'hffff}}),
|
||||
.cfg_tx_lfc_refresh('{4{16'h7fff}}),
|
||||
.cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
|
||||
.cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
|
||||
.cfg_tx_pfc_eth_type('{4{16'h8808}}),
|
||||
.cfg_tx_pfc_opcode('{4{16'h0101}}),
|
||||
.cfg_tx_pfc_en('{4{1'b0}}),
|
||||
.cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
|
||||
.cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
|
||||
.cfg_rx_lfc_opcode('{4{16'h0001}}),
|
||||
.cfg_rx_lfc_en('{4{1'b0}}),
|
||||
.cfg_rx_pfc_opcode('{4{16'h0101}}),
|
||||
.cfg_rx_pfc_en('{4{1'b0}})
|
||||
);
|
||||
|
||||
cndm_micro_pcie_us #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
// FW ID
|
||||
.FPGA_ID(FPGA_ID),
|
||||
.FW_ID(FW_ID),
|
||||
.FW_VER(FW_VER),
|
||||
.BOARD_ID(BOARD_ID),
|
||||
.BOARD_VER(BOARD_VER),
|
||||
.BUILD_DATE(BUILD_DATE),
|
||||
.GIT_HASH(GIT_HASH),
|
||||
.RELEASE_INFO(RELEASE_INFO),
|
||||
|
||||
// Structural configuration
|
||||
.PORTS(4),
|
||||
|
||||
// PTP configuration
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
.PTP_TS_FMT_TOD(1'b0),
|
||||
.PTP_CLK_PER_NS_NUM(32),
|
||||
.PTP_CLK_PER_NS_DENOM(5),
|
||||
|
||||
// PCIe interface configuration
|
||||
.RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
.AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W),
|
||||
.AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W)
|
||||
)
|
||||
cndm_inst (
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
.pcie_clk(pcie_clk),
|
||||
.pcie_rst(pcie_rst),
|
||||
.s_axis_pcie_cq(s_axis_pcie_cq),
|
||||
.m_axis_pcie_cc(m_axis_pcie_cc),
|
||||
.m_axis_pcie_rq(m_axis_pcie_rq),
|
||||
.s_axis_pcie_rc(s_axis_pcie_rc),
|
||||
|
||||
.pcie_rq_seq_num0(pcie_rq_seq_num0),
|
||||
.pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0),
|
||||
.pcie_rq_seq_num1(pcie_rq_seq_num1),
|
||||
.pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1),
|
||||
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_rcb_status(cfg_rcb_status),
|
||||
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_function_number(cfg_mgmt_function_number),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
|
||||
.cfg_fc_ph(cfg_fc_ph),
|
||||
.cfg_fc_pd(cfg_fc_pd),
|
||||
.cfg_fc_nph(cfg_fc_nph),
|
||||
.cfg_fc_npd(cfg_fc_npd),
|
||||
.cfg_fc_cplh(cfg_fc_cplh),
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
* PTP
|
||||
*/
|
||||
.ptp_clk(ptp_clk),
|
||||
.ptp_rst(ptp_rst),
|
||||
.ptp_sample_clk(ptp_sample_clk),
|
||||
.ptp_td_sdo(ptp_td_sd),
|
||||
.ptp_pps(ptp_pps),
|
||||
.ptp_pps_str(ptp_pps_str),
|
||||
.ptp_sync_locked(),
|
||||
.ptp_sync_ts_rel(),
|
||||
.ptp_sync_ts_rel_step(),
|
||||
.ptp_sync_ts_tod(),
|
||||
.ptp_sync_ts_tod_step(),
|
||||
.ptp_sync_pps(),
|
||||
.ptp_sync_pps_str(),
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
.mac_tx_clk(qsfp_tx_clk),
|
||||
.mac_tx_rst(qsfp_tx_rst),
|
||||
.mac_axis_tx(axis_qsfp_tx),
|
||||
.mac_axis_tx_cpl(axis_qsfp_tx_cpl),
|
||||
|
||||
.mac_rx_clk(qsfp_rx_clk),
|
||||
.mac_rx_rst(qsfp_rx_rst),
|
||||
.mac_axis_rx(axis_qsfp_rx)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
74
src/cndm/board/RK_XCKU5P_F/fpga/tb/fpga_core/Makefile
Normal file
74
src/cndm/board/RK_XCKU5P_F/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,74 @@
|
||||
# SPDX-License-Identifier: MIT
|
||||
#
|
||||
# Copyright (c) 2020-2026 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= verilator
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
RTL_DIR = ../../rtl
|
||||
LIB_DIR = ../../lib
|
||||
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||
|
||||
DUT = fpga_core
|
||||
COCOTB_TEST_MODULES = test_$(DUT)
|
||||
COCOTB_TOPLEVEL = test_$(DUT)
|
||||
MODULE = $(COCOTB_TEST_MODULES)
|
||||
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||
VERILOG_SOURCES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f
|
||||
|
||||
# handle file list files
|
||||
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||
|
||||
# module parameters
|
||||
export PARAM_SIM := "1'b1"
|
||||
export PARAM_VENDOR := "\"XILINX\""
|
||||
export PARAM_FAMILY := "\"kintexuplus\""
|
||||
|
||||
# PTP configuration
|
||||
export PARAM_PTP_TS_EN := 1
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
export PARAM_AXIL_CTRL_DATA_W := 32
|
||||
export PARAM_AXIL_CTRL_ADDR_W := 24
|
||||
|
||||
# MAC configuration
|
||||
export PARAM_CFG_LOW_LATENCY := 1
|
||||
export PARAM_COMBINED_MAC_PCS := 1
|
||||
export PARAM_MAC_DATA_W := "64"
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
VERILATOR_TRACE = 1
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
1
src/cndm/board/RK_XCKU5P_F/fpga/tb/fpga_core/baser.py
Symbolic link
1
src/cndm/board/RK_XCKU5P_F/fpga/tb/fpga_core/baser.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../../lib/taxi/src/eth/tb/baser.py
|
||||
1
src/cndm/board/RK_XCKU5P_F/fpga/tb/fpga_core/cndm.py
Symbolic link
1
src/cndm/board/RK_XCKU5P_F/fpga/tb/fpga_core/cndm.py
Symbolic link
@@ -0,0 +1 @@
|
||||
../../lib/taxi/src/cndm/tb/cndm.py
|
||||
524
src/cndm/board/RK_XCKU5P_F/fpga/tb/fpga_core/test_fpga_core.py
Normal file
524
src/cndm/board/RK_XCKU5P_F/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@@ -0,0 +1,524 @@
|
||||
#!/usr/bin/env python
|
||||
# SPDX-License-Identifier: MIT
|
||||
"""
|
||||
|
||||
Copyright (c) 2020-2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
import sys
|
||||
|
||||
import pytest
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, FallingEdge, Timer
|
||||
|
||||
from cocotbext.axi import AxiStreamBus
|
||||
from cocotbext.eth import XgmiiFrame
|
||||
from cocotbext.pcie.core import RootComplex
|
||||
from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
|
||||
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
import cndm
|
||||
except ImportError:
|
||||
# attempt import from current directory
|
||||
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||
try:
|
||||
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||
import cndm
|
||||
finally:
|
||||
del sys.path[0]
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = logging.getLogger("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
# Clocks
|
||||
cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
|
||||
|
||||
# PCIe
|
||||
self.rc = RootComplex()
|
||||
|
||||
self.rc.max_payload_size = 0x1 # 256 bytes
|
||||
self.rc.max_read_request_size = 0x2 # 512 bytes
|
||||
|
||||
self.dev = UltraScalePlusPcieDevice(
|
||||
# configuration options
|
||||
pcie_generation=3,
|
||||
pcie_link_width=4,
|
||||
user_clk_frequency=250e6,
|
||||
alignment="dword",
|
||||
cq_straddle=False,
|
||||
cc_straddle=False,
|
||||
rq_straddle=False,
|
||||
rc_straddle=False,
|
||||
rc_4tlp_straddle=False,
|
||||
pf_count=1,
|
||||
max_payload_size=1024,
|
||||
enable_client_tag=True,
|
||||
enable_extended_tag=True,
|
||||
enable_parity=False,
|
||||
enable_rx_msg_interface=False,
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
# signals
|
||||
# Clock and Reset Interface
|
||||
user_clk=dut.pcie_clk,
|
||||
user_reset=dut.pcie_rst,
|
||||
# user_lnk_up
|
||||
# sys_clk
|
||||
# sys_clk_gt
|
||||
# sys_reset
|
||||
# phy_rdy_out
|
||||
|
||||
# Requester reQuest Interface
|
||||
rq_bus=AxiStreamBus.from_entity(dut.m_axis_pcie_rq),
|
||||
pcie_rq_seq_num0=dut.pcie_rq_seq_num0,
|
||||
pcie_rq_seq_num_vld0=dut.pcie_rq_seq_num_vld0,
|
||||
pcie_rq_seq_num1=dut.pcie_rq_seq_num1,
|
||||
pcie_rq_seq_num_vld1=dut.pcie_rq_seq_num_vld1,
|
||||
# pcie_rq_tag0
|
||||
# pcie_rq_tag1
|
||||
# pcie_rq_tag_av
|
||||
# pcie_rq_tag_vld0
|
||||
# pcie_rq_tag_vld1
|
||||
|
||||
# Requester Completion Interface
|
||||
rc_bus=AxiStreamBus.from_entity(dut.s_axis_pcie_rc),
|
||||
|
||||
# Completer reQuest Interface
|
||||
cq_bus=AxiStreamBus.from_entity(dut.s_axis_pcie_cq),
|
||||
# pcie_cq_np_req
|
||||
# pcie_cq_np_req_count
|
||||
|
||||
# Completer Completion Interface
|
||||
cc_bus=AxiStreamBus.from_entity(dut.m_axis_pcie_cc),
|
||||
|
||||
# Transmit Flow Control Interface
|
||||
# pcie_tfc_nph_av=dut.pcie_tfc_nph_av,
|
||||
# pcie_tfc_npd_av=dut.pcie_tfc_npd_av,
|
||||
|
||||
# Configuration Management Interface
|
||||
cfg_mgmt_addr=dut.cfg_mgmt_addr,
|
||||
cfg_mgmt_function_number=dut.cfg_mgmt_function_number,
|
||||
cfg_mgmt_write=dut.cfg_mgmt_write,
|
||||
cfg_mgmt_write_data=dut.cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read=dut.cfg_mgmt_read,
|
||||
cfg_mgmt_read_data=dut.cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done,
|
||||
# cfg_mgmt_debug_access
|
||||
|
||||
# Configuration Status Interface
|
||||
# cfg_phy_link_down
|
||||
# cfg_phy_link_status
|
||||
# cfg_negotiated_width
|
||||
# cfg_current_speed
|
||||
# cfg_max_payload=dut.cfg_max_payload,
|
||||
# cfg_max_read_req=dut.cfg_max_read_req,
|
||||
# cfg_function_status
|
||||
# cfg_vf_status
|
||||
# cfg_function_power_state
|
||||
# cfg_vf_power_state
|
||||
# cfg_link_power_state
|
||||
# cfg_err_cor_out
|
||||
# cfg_err_nonfatal_out
|
||||
# cfg_err_fatal_out
|
||||
# cfg_local_error_out
|
||||
# cfg_local_error_valid
|
||||
# cfg_rx_pm_state
|
||||
# cfg_tx_pm_state
|
||||
# cfg_ltssm_state
|
||||
# cfg_rcb_status=dut.cfg_rcb_status,
|
||||
# cfg_obff_enable
|
||||
# cfg_pl_status_change
|
||||
# cfg_tph_requester_enable
|
||||
# cfg_tph_st_mode
|
||||
# cfg_vf_tph_requester_enable
|
||||
# cfg_vf_tph_st_mode
|
||||
|
||||
# Configuration Received Message Interface
|
||||
# cfg_msg_received
|
||||
# cfg_msg_received_data
|
||||
# cfg_msg_received_type
|
||||
|
||||
# Configuration Transmit Message Interface
|
||||
# cfg_msg_transmit
|
||||
# cfg_msg_transmit_type
|
||||
# cfg_msg_transmit_data
|
||||
# cfg_msg_transmit_done
|
||||
|
||||
# Configuration Flow Control Interface
|
||||
cfg_fc_ph=dut.cfg_fc_ph,
|
||||
cfg_fc_pd=dut.cfg_fc_pd,
|
||||
cfg_fc_nph=dut.cfg_fc_nph,
|
||||
cfg_fc_npd=dut.cfg_fc_npd,
|
||||
cfg_fc_cplh=dut.cfg_fc_cplh,
|
||||
cfg_fc_cpld=dut.cfg_fc_cpld,
|
||||
cfg_fc_sel=dut.cfg_fc_sel,
|
||||
|
||||
# Configuration Control Interface
|
||||
# cfg_hot_reset_in
|
||||
# cfg_hot_reset_out
|
||||
# cfg_config_space_enable
|
||||
# cfg_dsn
|
||||
# cfg_bus_number
|
||||
# cfg_ds_port_number
|
||||
# cfg_ds_bus_number
|
||||
# cfg_ds_device_number
|
||||
# cfg_ds_function_number
|
||||
# cfg_power_state_change_ack
|
||||
# cfg_power_state_change_interrupt
|
||||
# cfg_err_cor_in=dut.status_error_cor,
|
||||
# cfg_err_uncor_in=dut.status_error_uncor,
|
||||
# cfg_flr_in_process
|
||||
# cfg_flr_done
|
||||
# cfg_vf_flr_in_process
|
||||
# cfg_vf_flr_func_num
|
||||
# cfg_vf_flr_done
|
||||
# cfg_pm_aspm_l1_entry_reject
|
||||
# cfg_pm_aspm_tx_l0s_entry_disable
|
||||
# cfg_req_pm_transition_l23_ready
|
||||
# cfg_link_training_enable
|
||||
|
||||
# Configuration Interrupt Controller Interface
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
# cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
# cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
# cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
# cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
# cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
# cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
# cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
# cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
# cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
# cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
# cfg_ext_write_received
|
||||
# cfg_ext_register_number
|
||||
# cfg_ext_function_number
|
||||
# cfg_ext_write_data
|
||||
# cfg_ext_write_byte_enable
|
||||
# cfg_ext_read_data
|
||||
# cfg_ext_read_data_valid
|
||||
)
|
||||
|
||||
# self.dev.log.setLevel(logging.DEBUG)
|
||||
|
||||
self.rc.make_port().connect(self.dev)
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**int(dut.uut.cndm_inst.axil_ctrl_bar.ADDR_W))
|
||||
|
||||
# Ethernet
|
||||
cocotb.start_soon(Clock(dut.qsfp_mgt_refclk_p, 6.4, units="ns").start())
|
||||
|
||||
self.qsfp_sources = []
|
||||
self.qsfp_sinks = []
|
||||
|
||||
for ch in dut.uut.qsfp_mac_inst.ch:
|
||||
gt_inst = ch.ch_inst.gt.gt_inst
|
||||
|
||||
if ch.ch_inst.DATA_W.value == 64:
|
||||
if ch.ch_inst.CFG_LOW_LATENCY.value:
|
||||
clk = 2.482
|
||||
gbx_cfg = (66, [64, 65])
|
||||
else:
|
||||
clk = 2.56
|
||||
gbx_cfg = None
|
||||
else:
|
||||
if ch.ch_inst.CFG_LOW_LATENCY.value:
|
||||
clk = 3.102
|
||||
gbx_cfg = (66, [64, 65])
|
||||
else:
|
||||
clk = 3.2
|
||||
gbx_cfg = None
|
||||
|
||||
cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
|
||||
cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
|
||||
|
||||
self.qsfp_sources.append(BaseRSerdesSource(
|
||||
data=gt_inst.serdes_rx_data,
|
||||
data_valid=gt_inst.serdes_rx_data_valid,
|
||||
hdr=gt_inst.serdes_rx_hdr,
|
||||
hdr_valid=gt_inst.serdes_rx_hdr_valid,
|
||||
clock=gt_inst.rx_clk,
|
||||
slip=gt_inst.serdes_rx_bitslip,
|
||||
reverse=True,
|
||||
gbx_cfg=gbx_cfg
|
||||
))
|
||||
self.qsfp_sinks.append(BaseRSerdesSink(
|
||||
data=gt_inst.serdes_tx_data,
|
||||
data_valid=gt_inst.serdes_tx_data_valid,
|
||||
hdr=gt_inst.serdes_tx_hdr,
|
||||
hdr_valid=gt_inst.serdes_tx_hdr_valid,
|
||||
gbx_sync=gt_inst.serdes_tx_gbx_sync,
|
||||
clock=gt_inst.tx_clk,
|
||||
reverse=True,
|
||||
gbx_cfg=gbx_cfg
|
||||
))
|
||||
|
||||
dut.btn.setimmediatevalue(0)
|
||||
|
||||
dut.qsfp_modprsl.setimmediatevalue(0)
|
||||
dut.qsfp_intl.setimmediatevalue(0)
|
||||
|
||||
self.loopback_enable = False
|
||||
cocotb.start_soon(self._run_loopback())
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.rst_125mhz.setimmediatevalue(0)
|
||||
|
||||
await FallingEdge(self.dut.pcie_rst)
|
||||
await Timer(100, 'ns')
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
self.dut.rst_125mhz.value = 1
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
self.dut.rst_125mhz.value = 0
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk_125mhz)
|
||||
|
||||
await self.rc.enumerate()
|
||||
|
||||
async def _run_loopback(self):
|
||||
while True:
|
||||
await RisingEdge(self.dut.pcie_clk)
|
||||
|
||||
if self.loopback_enable:
|
||||
for src, snk in zip(self.qsfp_sources, self.qsfp_sinks):
|
||||
while not snk.empty():
|
||||
await src.send(await snk.recv())
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("Init driver model")
|
||||
driver = cndm.Driver()
|
||||
await driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||
|
||||
tb.log.info("Init complete")
|
||||
|
||||
tb.log.info("Wait for block lock")
|
||||
for k in range(1200):
|
||||
await RisingEdge(tb.dut.clk_125mhz)
|
||||
|
||||
for snk in tb.qsfp_sinks:
|
||||
snk.clear()
|
||||
|
||||
tb.log.info("Send and receive single packet on each port")
|
||||
|
||||
for k in range(len(driver.ports)):
|
||||
data = f"Corundum rocks on port {k}!".encode('ascii')
|
||||
|
||||
await driver.ports[k].start_xmit(data)
|
||||
|
||||
pkt = await tb.qsfp_sinks[k].recv()
|
||||
tb.log.info("Got TX packet: %s", pkt)
|
||||
|
||||
assert pkt.get_payload() == data.ljust(60, b'\x00')
|
||||
assert pkt.check_fcs()
|
||||
|
||||
await tb.qsfp_sources[k].send(pkt)
|
||||
|
||||
pkt = await driver.ports[k].recv()
|
||||
tb.log.info("Got RX packet: %s", pkt)
|
||||
|
||||
assert bytes(pkt) == data.ljust(60, b'\x00')
|
||||
|
||||
tb.log.info("Multiple small packets")
|
||||
|
||||
count = 64
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await driver.ports[0].start_xmit(p)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await driver.ports[0].recv()
|
||||
|
||||
tb.log.info("Got RX packet: %s", pkt)
|
||||
|
||||
assert bytes(pkt) == pkts[k].ljust(60, b'\x00')
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
tb.log.info("Multiple large packets")
|
||||
|
||||
count = 64
|
||||
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
tb.loopback_enable = True
|
||||
|
||||
for p in pkts:
|
||||
await driver.ports[0].start_xmit(p)
|
||||
|
||||
for k in range(count):
|
||||
pkt = await driver.ports[0].recv()
|
||||
|
||||
tb.log.info("Got RX packet: %s", pkt)
|
||||
|
||||
assert bytes(pkt) == pkts[k].ljust(60, b'\x00')
|
||||
|
||||
tb.loopback_enable = False
|
||||
|
||||
await RisingEdge(dut.clk_125mhz)
|
||||
await RisingEdge(dut.clk_125mhz)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
@pytest.mark.parametrize("mac_data_w", [32, 64])
|
||||
def test_fpga_core(request, mac_data_w):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(taxi_src_dir, "cndm", "rtl", "cndm_micro_pcie_us.f"),
|
||||
os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
|
||||
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_apb.f"),
|
||||
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
|
||||
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
|
||||
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
|
||||
os.path.join(taxi_src_dir, "pyrite", "rtl", "pyrite_pcie_us_vpd_qspi.f"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['SIM'] = "1'b1"
|
||||
parameters['VENDOR'] = "\"XILINX\""
|
||||
parameters['FAMILY'] = "\"kintexuplus\""
|
||||
|
||||
# PTP configuration
|
||||
parameters['PTP_TS_EN'] = 1
|
||||
|
||||
# AXI lite interface configuration (control)
|
||||
parameters['AXIL_CTRL_DATA_W'] = 32
|
||||
parameters['AXIL_CTRL_ADDR_W'] = 24
|
||||
|
||||
# MAC configuration
|
||||
parameters['CFG_LOW_LATENCY'] = 1
|
||||
parameters['COMBINED_MAC_PCS'] = 1
|
||||
parameters['MAC_DATA_W'] = mac_data_w
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
313
src/cndm/board/RK_XCKU5P_F/fpga/tb/fpga_core/test_fpga_core.sv
Normal file
313
src/cndm/board/RK_XCKU5P_F/fpga/tb/fpga_core/test_fpga_core.sv
Normal file
@@ -0,0 +1,313 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
|
||||
Copyright (c) 2025-2026 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA core logic testbench
|
||||
*/
|
||||
module test_fpga_core #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter logic SIM = 1'b0,
|
||||
parameter string VENDOR = "XILINX",
|
||||
parameter string FAMILY = "kintexuplus",
|
||||
|
||||
// FW ID
|
||||
parameter FPGA_ID = 32'h4A62093,
|
||||
parameter FW_ID = 32'h0000C001,
|
||||
parameter FW_VER = 32'h000_01_000,
|
||||
parameter BOARD_ID = 32'h1234_9005,
|
||||
parameter BOARD_VER = 32'h001_00_000,
|
||||
parameter BUILD_DATE = 32'd602976000,
|
||||
parameter GIT_HASH = 32'h5f87c2e8,
|
||||
parameter RELEASE_INFO = 32'h00000000,
|
||||
|
||||
// PTP configuration
|
||||
parameter logic PTP_TS_EN = 1'b1,
|
||||
|
||||
// PCIe interface configuration
|
||||
parameter AXIS_PCIE_DATA_W = 128,
|
||||
parameter AXIS_PCIE_RC_USER_W = AXIS_PCIE_DATA_W < 512 ? 75 : 161,
|
||||
parameter AXIS_PCIE_RQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 62 : 137,
|
||||
parameter AXIS_PCIE_CQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 85 : 183,
|
||||
parameter AXIS_PCIE_CC_USER_W = AXIS_PCIE_DATA_W < 512 ? 33 : 81,
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
parameter AXIL_CTRL_DATA_W = 32,
|
||||
parameter AXIL_CTRL_ADDR_W = 24,
|
||||
|
||||
// MAC configuration
|
||||
parameter logic CFG_LOW_LATENCY = 1'b1,
|
||||
parameter logic COMBINED_MAC_PCS = 1'b1,
|
||||
parameter MAC_DATA_W = 64
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32);
|
||||
localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6;
|
||||
|
||||
logic clk_125mhz;
|
||||
logic rst_125mhz;
|
||||
|
||||
logic [3:0] btn;
|
||||
logic [3:0] led;
|
||||
|
||||
logic uart_rxd;
|
||||
logic uart_txd;
|
||||
|
||||
logic qsfp_mgt_refclk_p;
|
||||
logic qsfp_mgt_refclk_n;
|
||||
logic qsfp_mgt_refclk_out;
|
||||
|
||||
logic qsfp_modsell;
|
||||
logic qsfp_resetl;
|
||||
logic qsfp_modprsl;
|
||||
logic qsfp_intl;
|
||||
logic qsfp_lpmode;
|
||||
|
||||
logic pcie_clk;
|
||||
logic pcie_rst;
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(AXIS_PCIE_DATA_W),
|
||||
.KEEP_EN(1),
|
||||
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||
.USER_EN(1),
|
||||
.USER_W(AXIS_PCIE_CQ_USER_W)
|
||||
) s_axis_pcie_cq();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(AXIS_PCIE_DATA_W),
|
||||
.KEEP_EN(1),
|
||||
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||
.USER_EN(1),
|
||||
.USER_W(AXIS_PCIE_CC_USER_W)
|
||||
) m_axis_pcie_cc();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(AXIS_PCIE_DATA_W),
|
||||
.KEEP_EN(1),
|
||||
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||
.USER_EN(1),
|
||||
.USER_W(AXIS_PCIE_RQ_USER_W)
|
||||
) m_axis_pcie_rq();
|
||||
|
||||
taxi_axis_if #(
|
||||
.DATA_W(AXIS_PCIE_DATA_W),
|
||||
.KEEP_EN(1),
|
||||
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||
.USER_EN(1),
|
||||
.USER_W(AXIS_PCIE_RC_USER_W)
|
||||
) s_axis_pcie_rc();
|
||||
|
||||
logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0;
|
||||
logic pcie_rq_seq_num_vld0;
|
||||
logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1;
|
||||
logic pcie_rq_seq_num_vld1;
|
||||
|
||||
logic [2:0] cfg_max_payload;
|
||||
logic [2:0] cfg_max_read_req;
|
||||
logic [3:0] cfg_rcb_status;
|
||||
|
||||
logic [9:0] cfg_mgmt_addr;
|
||||
logic [7:0] cfg_mgmt_function_number;
|
||||
logic cfg_mgmt_write;
|
||||
logic [31:0] cfg_mgmt_write_data;
|
||||
logic [3:0] cfg_mgmt_byte_enable;
|
||||
logic cfg_mgmt_read;
|
||||
logic [31:0] cfg_mgmt_read_data;
|
||||
logic cfg_mgmt_read_write_done;
|
||||
|
||||
logic [7:0] cfg_fc_ph;
|
||||
logic [11:0] cfg_fc_pd;
|
||||
logic [7:0] cfg_fc_nph;
|
||||
logic [11:0] cfg_fc_npd;
|
||||
logic [7:0] cfg_fc_cplh;
|
||||
logic [11:0] cfg_fc_cpld;
|
||||
logic [2:0] cfg_fc_sel;
|
||||
|
||||
logic cfg_ext_read_received;
|
||||
logic cfg_ext_write_received;
|
||||
logic [9:0] cfg_ext_register_number;
|
||||
logic [7:0] cfg_ext_function_number;
|
||||
logic [31:0] cfg_ext_write_data;
|
||||
logic [3:0] cfg_ext_write_byte_enable;
|
||||
logic [31:0] cfg_ext_read_data;
|
||||
logic cfg_ext_read_data_valid;
|
||||
|
||||
logic [3:0] cfg_interrupt_msi_enable;
|
||||
logic [11:0] cfg_interrupt_msi_mmenable;
|
||||
logic cfg_interrupt_msi_mask_update;
|
||||
logic [31:0] cfg_interrupt_msi_data;
|
||||
logic [1:0] cfg_interrupt_msi_select;
|
||||
logic [31:0] cfg_interrupt_msi_int;
|
||||
logic [31:0] cfg_interrupt_msi_pending_status;
|
||||
logic cfg_interrupt_msi_pending_status_data_enable;
|
||||
logic [1:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
logic cfg_interrupt_msi_sent;
|
||||
logic cfg_interrupt_msi_fail;
|
||||
logic [2:0] cfg_interrupt_msi_attr;
|
||||
logic cfg_interrupt_msi_tph_present;
|
||||
logic [1:0] cfg_interrupt_msi_tph_type;
|
||||
logic [7:0] cfg_interrupt_msi_tph_st_tag;
|
||||
logic [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
logic fpga_boot;
|
||||
logic qspi_clk;
|
||||
logic [3:0] qspi_dq_i;
|
||||
logic [3:0] qspi_dq_o;
|
||||
logic [3:0] qspi_dq_oe;
|
||||
logic qspi_cs;
|
||||
|
||||
fpga_core #(
|
||||
.SIM(SIM),
|
||||
.VENDOR(VENDOR),
|
||||
.FAMILY(FAMILY),
|
||||
|
||||
// FW ID
|
||||
.FPGA_ID(FPGA_ID),
|
||||
.FW_ID(FW_ID),
|
||||
.FW_VER(FW_VER),
|
||||
.BOARD_ID(BOARD_ID),
|
||||
.BOARD_VER(BOARD_VER),
|
||||
.BUILD_DATE(BUILD_DATE),
|
||||
.GIT_HASH(GIT_HASH),
|
||||
.RELEASE_INFO(RELEASE_INFO),
|
||||
|
||||
// PTP configuration
|
||||
.PTP_TS_EN(PTP_TS_EN),
|
||||
|
||||
// PCIe interface configuration
|
||||
.RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),
|
||||
|
||||
// AXI lite interface configuration (control)
|
||||
.AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W),
|
||||
.AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W),
|
||||
|
||||
// MAC configuration
|
||||
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
|
||||
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
|
||||
.MAC_DATA_W(MAC_DATA_W)
|
||||
)
|
||||
uut (
|
||||
/*
|
||||
* Clock: 125MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk_125mhz(clk_125mhz),
|
||||
.rst_125mhz(rst_125mhz),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.btn(btn),
|
||||
.led(led),
|
||||
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
.uart_rxd(uart_rxd),
|
||||
.uart_txd(uart_txd),
|
||||
|
||||
/*
|
||||
* Ethernet: SFP+
|
||||
*/
|
||||
.qsfp_rx_p('{4{1'b0}}),
|
||||
.qsfp_rx_n('{4{1'b0}}),
|
||||
.qsfp_tx_p(),
|
||||
.qsfp_tx_n(),
|
||||
.qsfp_mgt_refclk_p(qsfp_mgt_refclk_p),
|
||||
.qsfp_mgt_refclk_n(qsfp_mgt_refclk_n),
|
||||
.qsfp_modsell(qsfp_modsell),
|
||||
.qsfp_resetl(qsfp_resetl),
|
||||
.qsfp_modprsl(qsfp_modprsl),
|
||||
.qsfp_intl(qsfp_intl),
|
||||
.qsfp_lpmode(qsfp_lpmode),
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
.pcie_clk(pcie_clk),
|
||||
.pcie_rst(pcie_rst),
|
||||
.s_axis_pcie_cq(s_axis_pcie_cq),
|
||||
.m_axis_pcie_cc(m_axis_pcie_cc),
|
||||
.m_axis_pcie_rq(m_axis_pcie_rq),
|
||||
.s_axis_pcie_rc(s_axis_pcie_rc),
|
||||
|
||||
.pcie_rq_seq_num0(pcie_rq_seq_num0),
|
||||
.pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0),
|
||||
.pcie_rq_seq_num1(pcie_rq_seq_num1),
|
||||
.pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1),
|
||||
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_rcb_status(cfg_rcb_status),
|
||||
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_function_number(cfg_mgmt_function_number),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
|
||||
.cfg_fc_ph(cfg_fc_ph),
|
||||
.cfg_fc_pd(cfg_fc_pd),
|
||||
.cfg_fc_nph(cfg_fc_nph),
|
||||
.cfg_fc_npd(cfg_fc_npd),
|
||||
.cfg_fc_cplh(cfg_fc_cplh),
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_ext_read_received(cfg_ext_read_received),
|
||||
.cfg_ext_write_received(cfg_ext_write_received),
|
||||
.cfg_ext_register_number(cfg_ext_register_number),
|
||||
.cfg_ext_function_number(cfg_ext_function_number),
|
||||
.cfg_ext_write_data(cfg_ext_write_data),
|
||||
.cfg_ext_write_byte_enable(cfg_ext_write_byte_enable),
|
||||
.cfg_ext_read_data(cfg_ext_read_data),
|
||||
.cfg_ext_read_data_valid(cfg_ext_read_data_valid),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
.fpga_boot(fpga_boot),
|
||||
.qspi_clk(qspi_clk),
|
||||
.qspi_dq_i(qspi_dq_i),
|
||||
.qspi_dq_o(qspi_dq_o),
|
||||
.qspi_dq_oe(qspi_dq_oe),
|
||||
.qspi_cs(qspi_cs)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user