From d1aa3013c676b4c0afa92c07a1e99c2de2c542db Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 22 Feb 2026 16:49:55 -0800 Subject: [PATCH] cndm: Add support for Alveo AU200/VCU1525 Signed-off-by: Alex Forencich --- src/cndm/board/Alveo/fpga/README.md | 42 + src/cndm/board/Alveo/fpga/common/vivado.mk | 153 +++ src/cndm/board/Alveo/fpga/fpga_AU200/Makefile | 98 ++ .../board/Alveo/fpga/fpga_AU200/config.tcl | 131 +++ .../board/Alveo/fpga/fpga_AU200_10g/Makefile | 98 ++ .../Alveo/fpga/fpga_AU200_10g/config.tcl | 131 +++ .../board/Alveo/fpga/fpga_VCU1525/Makefile | 169 ++++ .../board/Alveo/fpga/fpga_VCU1525/config.tcl | 131 +++ .../Alveo/fpga/fpga_VCU1525_10g/Makefile | 169 ++++ .../Alveo/fpga/fpga_VCU1525_10g/config.tcl | 131 +++ src/cndm/board/Alveo/fpga/fpga_au200.xdc | 862 ++++++++++++++++ src/cndm/board/Alveo/fpga/ip/ddr4_0.tcl | 18 + .../Alveo/fpga/ip/pcie4_uscale_plus_0.tcl | 30 + src/cndm/board/Alveo/fpga/lib/taxi | 1 + src/cndm/board/Alveo/fpga/rtl/fpga_au200.sv | 950 ++++++++++++++++++ src/cndm/board/Alveo/fpga/rtl/fpga_core.sv | 851 ++++++++++++++++ .../board/Alveo/fpga/tb/fpga_core/Makefile | 86 ++ .../board/Alveo/fpga/tb/fpga_core/baser.py | 1 + .../board/Alveo/fpga/tb/fpga_core/cndm.py | 1 + .../Alveo/fpga/tb/fpga_core/test_fpga_core.py | 547 ++++++++++ .../Alveo/fpga/tb/fpga_core/test_fpga_core.sv | 339 +++++++ 21 files changed, 4939 insertions(+) create mode 100644 src/cndm/board/Alveo/fpga/README.md create mode 100644 src/cndm/board/Alveo/fpga/common/vivado.mk create mode 100644 src/cndm/board/Alveo/fpga/fpga_AU200/Makefile create mode 100644 src/cndm/board/Alveo/fpga/fpga_AU200/config.tcl create mode 100644 src/cndm/board/Alveo/fpga/fpga_AU200_10g/Makefile create mode 100644 src/cndm/board/Alveo/fpga/fpga_AU200_10g/config.tcl create mode 100644 src/cndm/board/Alveo/fpga/fpga_VCU1525/Makefile create mode 100644 src/cndm/board/Alveo/fpga/fpga_VCU1525/config.tcl create mode 100644 src/cndm/board/Alveo/fpga/fpga_VCU1525_10g/Makefile create mode 100644 src/cndm/board/Alveo/fpga/fpga_VCU1525_10g/config.tcl create mode 100644 src/cndm/board/Alveo/fpga/fpga_au200.xdc create mode 100644 src/cndm/board/Alveo/fpga/ip/ddr4_0.tcl create mode 100644 src/cndm/board/Alveo/fpga/ip/pcie4_uscale_plus_0.tcl create mode 120000 src/cndm/board/Alveo/fpga/lib/taxi create mode 100644 src/cndm/board/Alveo/fpga/rtl/fpga_au200.sv create mode 100644 src/cndm/board/Alveo/fpga/rtl/fpga_core.sv create mode 100644 src/cndm/board/Alveo/fpga/tb/fpga_core/Makefile create mode 120000 src/cndm/board/Alveo/fpga/tb/fpga_core/baser.py create mode 120000 src/cndm/board/Alveo/fpga/tb/fpga_core/cndm.py create mode 100644 src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.py create mode 100644 src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.sv diff --git a/src/cndm/board/Alveo/fpga/README.md b/src/cndm/board/Alveo/fpga/README.md new file mode 100644 index 0000000..9bc75e8 --- /dev/null +++ b/src/cndm/board/Alveo/fpga/README.md @@ -0,0 +1,42 @@ +# Corundum for Alveo + +## Introduction + +This design targets the Xilinx Alveo series. + +* USB UART + * XFCP (3 Mbaud) +* DSFP/QSFP28 + * 10GBASE-R or 25GBASE-R MACs via GTY transceivers + +## Board details + +* AU200 + * FPGA: xcu200-fsgd2104-2-e + * USB UART: FTDI FT4232H + * PCIe: gen 3 x16 (~128 Gbps) + * Reference oscillator: 156.25 MHz from Si570 + * 25GBASE-R PHY: Soft PCS with GTY transceivers +* VCU1525 + * FPGA: xcvu9p-fsgd2104-2L-e + * USB UART: FTDI FT4232H + * PCIe: gen 3 x16 (~128 Gbps) + * Reference oscillator: 156.25 MHz from Si570 + * 25GBASE-R PHY: Soft PCS with GTY transceivers + +## Licensing + +* Toolchain + * Vivado Standard (enterprise license not required) +* IP + * No licensed vendor IP or 3rd party IP + +## How to build + +Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. + +On the host system, run `make` in `modules/cndm` to build the driver. Ensure that the headers for the running kernel are installed, otherwise the driver cannot be compiled. + +## How to test + +Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod cndm.ko`. Check `dmesg` for output from driver initialization. Run `cndm_ddcmd.sh =p` to enable all debug messages. diff --git a/src/cndm/board/Alveo/fpga/common/vivado.mk b/src/cndm/board/Alveo/fpga/common/vivado.mk new file mode 100644 index 0000000..07c56e2 --- /dev/null +++ b/src/cndm/board/Alveo/fpga/common/vivado.mk @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: MIT +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016-2025 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - list of source files +# INC_FILES - list of include files +# XDC_FILES - list of timing constraint files +# XCI_FILES - list of IP XCI files +# IP_TCL_FILES - list of IP TCL files (sourced during project creation) +# CONFIG_TCL_FILES - list of config TCL files (sourced before each build) +# +# Note: both SYN_FILES and INC_FILES support file list files. File list +# files are files with a .f extension that contain a list of additional +# files to include, one path relative to the .f file location per line. +# The .f files are processed recursively, and then the complete file list +# is de-duplicated, with later files in the list taking precedence. +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include $(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) +XDC_FILES ?= $(PROJECT).xdc + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES))) +INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES))) + +################################################################### +# Main Targets +# +# all: build everything (fpga) +# fpga: build FPGA config +# vivado: open project in Vivado +# tmpclean: remove intermediate files +# clean: remove output files and project files +# distclean: remove archived output files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file + +# create fresh project if Makefile or IP files have changed +create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@ + for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +# source config TCL scripts if any source file has changed +update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# output files (including potentially bit, bin, ltx, and xsa) +$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \ + if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi diff --git a/src/cndm/board/Alveo/fpga/fpga_AU200/Makefile b/src/cndm/board/Alveo/fpga/fpga_AU200/Makefile new file mode 100644 index 0000000..60a582e --- /dev/null +++ b/src/cndm/board/Alveo/fpga/fpga_AU200/Makefile @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcu200-fsgd2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga_au200.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f + +# XDC files +XDC_FILES = ../fpga_au200.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = ../ip/pcie4_uscale_plus_0.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(PROJECT).mcs $(PROJECT).prm + echo "open_hw_manager" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/cndm/board/Alveo/fpga/fpga_AU200/config.tcl b/src/cndm/board/Alveo/fpga/fpga_AU200/config.tcl new file mode 100644 index 0000000..7eb8027 --- /dev/null +++ b/src/cndm/board/Alveo/fpga/fpga_AU200/config.tcl @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x4B37093] +set fw_id [expr 0x0000C001] +set fw_ver $tag_ver +set board_vendor_id [expr 0x10ee] +set board_device_id [expr 0x90c8] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0xC001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_device_id $board_device_id +set pcie_subsystem_vendor_id $board_vendor_id + +# FW ID +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# PTP configuration +dict set params PTP_TS_EN "1" + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_W "32" +dict set params AXIL_CTRL_ADDR_W "24" + +# MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# PCIe IP core settings +set pcie [get_ips pcie4_uscale_plus_0] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI +dict set pcie_config "CONFIG.pf0_msi_enabled" {true} + +set_property -dict $pcie_config $pcie + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/cndm/board/Alveo/fpga/fpga_AU200_10g/Makefile b/src/cndm/board/Alveo/fpga/fpga_AU200_10g/Makefile new file mode 100644 index 0000000..dcdd8a0 --- /dev/null +++ b/src/cndm/board/Alveo/fpga/fpga_AU200_10g/Makefile @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcu200-fsgd2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga_au200.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f + +# XDC files +XDC_FILES = ../fpga_au200.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = ../ip/pcie4_uscale_plus_0.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(PROJECT).mcs $(PROJECT).prm + echo "open_hw_manager" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/cndm/board/Alveo/fpga/fpga_AU200_10g/config.tcl b/src/cndm/board/Alveo/fpga/fpga_AU200_10g/config.tcl new file mode 100644 index 0000000..468611e --- /dev/null +++ b/src/cndm/board/Alveo/fpga/fpga_AU200_10g/config.tcl @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x4B37093] +set fw_id [expr 0x0000C001] +set fw_ver $tag_ver +set board_vendor_id [expr 0x10ee] +set board_device_id [expr 0x90c8] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0xC001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_device_id $board_device_id +set pcie_subsystem_vendor_id $board_vendor_id + +# FW ID +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# PTP configuration +dict set params PTP_TS_EN "1" + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_W "32" +dict set params AXIL_CTRL_ADDR_W "24" + +# MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# PCIe IP core settings +set pcie [get_ips pcie4_uscale_plus_0] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI +dict set pcie_config "CONFIG.pf0_msi_enabled" {true} + +set_property -dict $pcie_config $pcie + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/cndm/board/Alveo/fpga/fpga_VCU1525/Makefile b/src/cndm/board/Alveo/fpga/fpga_VCU1525/Makefile new file mode 100644 index 0000000..16c80d1 --- /dev/null +++ b/src/cndm/board/Alveo/fpga/fpga_VCU1525/Makefile @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu9p-fsgd2104-2L-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga_au200.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f + +# XDC files +XDC_FILES = ../fpga_au200.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = ../ip/pcie4_uscale_plus_0.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +$(PROJECT)_fallback.bit: $(PROJECT).bit + echo "open_project $*.xpr" > generate_fallback_bit.tcl + echo "open_run impl_1" >> generate_fallback_bit.tcl + echo "startgroup" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.TIMER_CFG 0x03000000 [current_design]" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT ENABLE [current_design]" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x04000000 [current_design]" >> generate_fallback_bit.tcl + echo "endgroup" >> generate_fallback_bit.tcl + echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl + echo "undo" >> generate_fallback_bit.tcl + echo "exit" >> generate_fallback_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl + mkdir -p rev + EXT=bit; COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \ + echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT"; + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x04000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +$(PROJECT)_fallback.mcs $(PROJECT)_fallback.prm: $(PROJECT)_fallback.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x00000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl + echo "exit" >> generate_fallback_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \ + echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done; + +$(PROJECT)_full.mcs $(PROJECT)_full.prm: $(PROJECT)_fallback.bit $(PROJECT).bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x00000000 $*_fallback.bit up 0x04000000 $*.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl + echo "exit" >> generate_full_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \ + echo "Output: rev/$*_full_rev$$COUNT$$x"; done; + +flash: $(PROJECT).mcs $(PROJECT).prm + echo "open_hw_manager" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + +flash%: $(PROJECT)%.mcs $(PROJECT)%.prm + echo "open_hw_manager" > flash$*.tcl + echo "connect_hw_server" >> flash$*.tcl + echo "open_hw_target" >> flash$*.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash$*.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl + echo "set_property PROGRAM.FILES [list \"$(PROJECT)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl + echo "program_hw_devices [current_hw_device]" >> flash$*.tcl + echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl + echo "boot_hw_device [current_hw_device]" >> flash$*.tcl + echo "exit" >> flash$*.tcl + vivado -nojournal -nolog -mode batch -source flash$*.tcl diff --git a/src/cndm/board/Alveo/fpga/fpga_VCU1525/config.tcl b/src/cndm/board/Alveo/fpga/fpga_VCU1525/config.tcl new file mode 100644 index 0000000..f11106b --- /dev/null +++ b/src/cndm/board/Alveo/fpga/fpga_VCU1525/config.tcl @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x4B31093] +set fw_id [expr 0x0000C001] +set fw_ver $tag_ver +set board_vendor_id [expr 0x10ee] +set board_device_id [expr 0x95f5] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0xC001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_device_id $board_device_id +set pcie_subsystem_vendor_id $board_vendor_id + +# FW ID +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# PTP configuration +dict set params PTP_TS_EN "1" + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_W "32" +dict set params AXIL_CTRL_ADDR_W "24" + +# MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "64" + +# PCIe IP core settings +set pcie [get_ips pcie4_uscale_plus_0] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI +dict set pcie_config "CONFIG.pf0_msi_enabled" {true} + +set_property -dict $pcie_config $pcie + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/cndm/board/Alveo/fpga/fpga_VCU1525_10g/Makefile b/src/cndm/board/Alveo/fpga/fpga_VCU1525_10g/Makefile new file mode 100644 index 0000000..0b47f6c --- /dev/null +++ b/src/cndm/board/Alveo/fpga/fpga_VCU1525_10g/Makefile @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu9p-fsgd2104-2L-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga_au200.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f + +# XDC files +XDC_FILES = ../fpga_au200.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl +XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = ../ip/pcie4_uscale_plus_0.tcl +IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl + +# Configuration +CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +$(PROJECT)_fallback.bit: $(PROJECT).bit + echo "open_project $*.xpr" > generate_fallback_bit.tcl + echo "open_run impl_1" >> generate_fallback_bit.tcl + echo "startgroup" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.TIMER_CFG 0x03000000 [current_design]" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT ENABLE [current_design]" >> generate_fallback_bit.tcl + echo "set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x04000000 [current_design]" >> generate_fallback_bit.tcl + echo "endgroup" >> generate_fallback_bit.tcl + echo "write_bitstream -verbose -force $*_fallback.bit" >> generate_fallback_bit.tcl + echo "undo" >> generate_fallback_bit.tcl + echo "exit" >> generate_fallback_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_fallback_bit.tcl + mkdir -p rev + EXT=bit; COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.$$EXT ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + cp $@ rev/$*_fallback_rev$$COUNT.$$EXT; \ + echo "Output: rev/$*_fallback_rev$$COUNT.$$EXT"; + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x04000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +$(PROJECT)_fallback.mcs $(PROJECT)_fallback.prm: $(PROJECT)_fallback.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x00000000 $*_fallback.bit} -checksum -file $*_fallback.mcs" > generate_fallback_mcs.tcl + echo "exit" >> generate_fallback_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_fallback_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*_fallback$$x rev/$*_fallback_rev$$COUNT$$x; \ + echo "Output: rev/$*_fallback_rev$$COUNT$$x"; done; + +$(PROJECT)_full.mcs $(PROJECT)_full.prm: $(PROJECT)_fallback.bit $(PROJECT).bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x00000000 $*_fallback.bit up 0x04000000 $*.bit} -checksum -file $*_full.mcs" > generate_full_mcs.tcl + echo "exit" >> generate_full_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_full_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*_full$$x rev/$*_full_rev$$COUNT$$x; \ + echo "Output: rev/$*_full_rev$$COUNT$$x"; done; + +flash: $(PROJECT).mcs $(PROJECT).prm + echo "open_hw_manager" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl + +flash%: $(PROJECT)%.mcs $(PROJECT)%.prm + echo "open_hw_manager" > flash$*.tcl + echo "connect_hw_server" >> flash$*.tcl + echo "open_hw_target" >> flash$*.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash$*.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash$*.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash$*.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash$*.tcl + echo "set_property PROGRAM.FILES [list \"$(PROJECT)$*.mcs\"] [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT)$*.prm\"] [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash$*.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash$*.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash$*.tcl + echo "program_hw_devices [current_hw_device]" >> flash$*.tcl + echo "refresh_hw_device [current_hw_device]" >> flash$*.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash$*.tcl + echo "boot_hw_device [current_hw_device]" >> flash$*.tcl + echo "exit" >> flash$*.tcl + vivado -nojournal -nolog -mode batch -source flash$*.tcl diff --git a/src/cndm/board/Alveo/fpga/fpga_VCU1525_10g/config.tcl b/src/cndm/board/Alveo/fpga/fpga_VCU1525_10g/config.tcl new file mode 100644 index 0000000..9374b55 --- /dev/null +++ b/src/cndm/board/Alveo/fpga/fpga_VCU1525_10g/config.tcl @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +set params [dict create] + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" + +if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } { + puts "Error running git or project not under version control" +} + +if { [catch {set git_tag [exec git describe --tags HEAD]}] } { + puts "Error running git, project not under version control, or no tag found" +} + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } { + puts "Failed to extract version from git tag" + set tag_ver 0.0.1 +} + +puts "Tag version: ${tag_ver}" + +# FW and board IDs +set fpga_id [expr 0x4B31093] +set fw_id [expr 0x0000C001] +set fw_ver $tag_ver +set board_vendor_id [expr 0x10ee] +set board_device_id [expr 0x95f5] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# PCIe IDs +set pcie_vendor_id [expr 0x1234] +set pcie_device_id [expr 0xC001] +set pcie_class_code [expr 0x020000] +set pcie_revision_id [expr 0x00] +set pcie_subsystem_device_id $board_device_id +set pcie_subsystem_vendor_id $board_vendor_id + +# FW ID +dict set params FPGA_ID [format "32'h%08x" $fpga_id] +dict set params FW_ID [format "32'h%08x" $fw_id] +dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0] +dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0] +dict set params BUILD_DATE "32'd${build_date}" +dict set params GIT_HASH "32'h${git_hash}" +dict set params RELEASE_INFO [format "32'h%08x" $release_info] + +# PTP configuration +dict set params PTP_TS_EN "1" + +# AXI lite interface configuration (control) +dict set params AXIL_CTRL_DATA_W "32" +dict set params AXIL_CTRL_ADDR_W "24" + +# MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + +# PCIe IP core settings +set pcie [get_ips pcie4_uscale_plus_0] + +# configure BAR settings +proc configure_bar {pcie pf bar aperture} { + set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes} + for { set i 0 } { $i < [llength $size_list] } { incr i } { + set scale [lindex $size_list $i] + + if {$aperture > 0 && $aperture < ($i+1)*10} { + set size [expr 1 << $aperture - ($i*10)] + + puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)" + + set pcie_config [dict create] + + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true} + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale + dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size + + set_property -dict $pcie_config $pcie + + return + } + } + puts "${pcie} PF${pf} BAR${bar}: disabled" + set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie +} + +# Control BAR (BAR 0) +configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W] + +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI +dict set pcie_config "CONFIG.pf0_msi_enabled" {true} + +set_property -dict $pcie_config $pcie + +# apply parameters to top-level +set param_list {} +dict for {name value} $params { + lappend param_list $name=$value +} + +set_property generic $param_list [get_filesets sources_1] diff --git a/src/cndm/board/Alveo/fpga/fpga_au200.xdc b/src/cndm/board/Alveo/fpga/fpga_au200.xdc new file mode 100644 index 0000000..1bb084e --- /dev/null +++ b/src/cndm/board/Alveo/fpga/fpga_au200.xdc @@ -0,0 +1,862 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# XDC constraints for Xilinx AU200/AU250/VCU1525 +# AU200 part: xcu200-fsgd2104-2-e +# AU250 part: xcu250-figd2104-2-e +# VCU1525 part: xcvu9p-fsgd2104-2L-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +set_operating_conditions -design_power_budget 160 + +# System clocks +# 300 MHz (DDR 0) +#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] +#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] +#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] + +# 300 MHz (DDR 1) +#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] +#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] +#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] + +# 300 MHz (DDR 2) +#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] +#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] +#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] + +# 300 MHz (DDR 3) +#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] +#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] +#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] + +# SI570 user clock +#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p] +#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n] +#create_clock -period 6.400 -name clk_user [get_ports clk_user_p] + +# LEDs +set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] +set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] +set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# Reset button +set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset] + +set_false_path -from [get_ports {reset}] +set_input_delay 0 [get_ports {reset}] + +# DIP switches +set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] +set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] +set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] +set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] + +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + +# UART (U27 FT4232H channel CDBUS) +set_property -dict {LOC BB20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd] ;# U27.39 CDBUS1 RXD +set_property -dict {LOC BF18 IOSTANDARD LVCMOS12} [get_ports uart_rxd] ;# U27.38 CDBUS0 TXD + +set_false_path -to [get_ports {uart_txd}] +set_output_delay 0 [get_ports {uart_txd}] +set_false_path -from [get_ports {uart_rxd}] +set_input_delay 0 [get_ports {uart_rxd}] + +# BMC +#set_property -dict {LOC AR20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}] +#set_property -dict {LOC AM20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}] +#set_property -dict {LOC AM21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[2]}] +#set_property -dict {LOC AN21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[3]}] +#set_property -dict {LOC BB19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}] +#set_property -dict {LOC BA19 IOSTANDARD LVCMOS12} [get_ports {msp_uart_rxd}] + +#set_false_path -to [get_ports {msp_uart_txd}] +#set_output_delay 0 [get_ports {msp_uart_txd}] +#set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}] +#set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}] + +# QSFP28 Interfaces +set_property -dict {LOC N4 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N3 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N9 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC N8 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M2 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M1 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M7 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M6 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L4 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L3 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L9 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC L8 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K2 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K1 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K7 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC K6 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M11 } [get_ports {qsfp0_mgt_refclk_0_p}] ;# MGTREFCLK0P_231 from U14.4 via U43.13 +set_property -dict {LOC M10 } [get_ports {qsfp0_mgt_refclk_0_n}] ;# MGTREFCLK0N_231 from U14.5 via U43.14 +#set_property -dict {LOC K11 } [get_ports {qsfp0_mgt_refclk_1_p}] ;# MGTREFCLK1P_231 from U9.18 +#set_property -dict {LOC K10 } [get_ports {qsfp0_mgt_refclk_1_n}] ;# MGTREFCLK1N_231 from U9.17 +set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_modsell}] +set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_resetl}] +set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports {qsfp0_modprsl}] +set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports {qsfp0_intl}] +set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_lpmode}] +# set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_refclk_reset}] +# set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}] +# set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}] + +# 156.25 MHz MGT reference clock (from SI570) +create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports {qsfp0_mgt_refclk_0_p}] + +# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) +#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports {qsfp0_mgt_refclk_1_p}] + +# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) +#create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports {qsfp0_mgt_refclk_1_p}] + +set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode}] +set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode}] +set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}] +set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}] +#set_false_path -to [get_ports {qsfp0_refclk_reset qsfp0_fs[*]}] +#set_output_delay 0 [get_ports {qsfp0_refclk_reset qsfp0_fs[*]}] + +set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U9 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC U8 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T2 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T1 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R4 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R3 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R9 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC R8 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P2 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P1 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 +set_property -dict {LOC T11 } [get_ports {qsfp1_mgt_refclk_0_p}] ;# MGTREFCLK0P_230 from U14.4 via U43.15 +set_property -dict {LOC T10 } [get_ports {qsfp1_mgt_refclk_0_n}] ;# MGTREFCLK0N_230 from U14.5 via U43.16 +#set_property -dict {LOC P11 } [get_ports {qsfp1_mgt_refclk_1_p}] ;# MGTREFCLK1P_230 from U12.18 +#set_property -dict {LOC P10 } [get_ports {qsfp1_mgt_refclk_1_n}] ;# MGTREFCLK1N_230 from U12.17 +set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_modsell}] +set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_resetl}] +set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports {qsfp1_modprsl}] +set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports {qsfp1_intl}] +set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_lpmode}] +# set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_refclk_reset}] +# set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}] +# set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}] + +# 156.25 MHz MGT reference clock (from SI570) +create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports {qsfp1_mgt_refclk_0_p}] + +# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01) +#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports {qsfp1_mgt_refclk_1_p}] + +# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) +#create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports {qsfp1_mgt_refclk_1_p}] + +set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] +set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] +set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] +set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] +#set_false_path -to [get_ports {qsfp1_refclk_reset qsfp1_fs[*]}] +#set_output_delay 0 [get_ports {qsfp1_refclk_reset qsfp1_fs[*]}] + +# I2C interface +#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset] +set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl] +set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda] + +set_false_path -to [get_ports {i2c_sda i2c_scl}] +set_output_delay 0 [get_ports {i2c_sda i2c_scl}] +set_false_path -from [get_ports {i2c_sda i2c_scl}] +set_input_delay 0 [get_ports {i2c_sda i2c_scl}] + +# PCIe Interface +set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AG8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AJ8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 +set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL4 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL3 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL9 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AL8 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN4 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN3 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN9 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AN8 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AR4 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AR3 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AR9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AR8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AU4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AU3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AU9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AU8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AV7 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AV6 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AW4 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AW3 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BB5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BB4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BD5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BD4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BF5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC BF4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +set_property -dict {LOC AM11 } [get_ports {pcie_refclk_p}] ;# MGTREFCLK0P_226 +set_property -dict {LOC AM10 } [get_ports {pcie_refclk_n}] ;# MGTREFCLK0N_226 +set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports {pcie_reset_n}] + +# 100 MHz MGT reference clock +create_clock -period 10 -name pcie_mgt_refclk [get_ports {pcie_refclk_p}] + +set_false_path -from [get_ports {pcie_reset_n}] +set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +#set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +#set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +#set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +#set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +#set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +#set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +#set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +#set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +#set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +#set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +#set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +#set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +#set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +#set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +#set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +#set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +#set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +#set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +#set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +#set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +#set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +#set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] +#set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] +#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] +#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] +#set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] +#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] +#set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] +#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] +#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] +#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] +#set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +#set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] +#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] +#set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +#set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] + +#set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +#set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +#set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +#set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +#set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +#set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +#set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +#set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +#set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +#set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +#set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +#set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +#set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +#set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +#set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +#set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +#set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +#set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +#set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +#set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +#set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +#set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +#set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +#set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +#set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +#set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +#set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +#set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +#set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +#set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +#set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +#set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +#set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +#set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +#set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +#set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +#set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +#set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +#set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +#set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +#set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +#set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +#set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +#set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +#set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +#set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +#set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +#set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +#set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +#set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +#set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +#set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +#set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +#set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +#set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +#set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +#set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +#set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +#set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +#set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +#set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +#set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +#set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +#set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +#set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +#set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +#set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +#set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +#set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +#set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +#set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +#set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +#set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +#set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +#set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +#set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +#set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +#set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +#set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +#set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +#set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +#set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +#set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +#set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +#set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +#set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +#set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +#set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +#set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +#set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +#set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +#set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +#set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +#set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] +#set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] +#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] +#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] +#set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] +#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] +#set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] +#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] +#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] +#set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +#set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] +#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] +#set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +#set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] + +#set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +#set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +#set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +#set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +#set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +#set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +#set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +#set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +#set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +#set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +#set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +#set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +#set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +#set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +#set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +#set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +#set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +#set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +#set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +#set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +#set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +#set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +#set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +#set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +#set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +#set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +#set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +#set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +#set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +#set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +#set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +#set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +#set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +#set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +#set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +#set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +#set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +#set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +#set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +#set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +#set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +#set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +#set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +#set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +#set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +#set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +#set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +#set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +#set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +#set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +#set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +#set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +#set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +#set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +#set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +#set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +#set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +#set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +#set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +#set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +#set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +#set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +#set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +#set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +#set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +#set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +#set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +#set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +#set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +#set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +#set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +#set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +#set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +#set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +#set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +#set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +#set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +#set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +#set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +#set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +#set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +#set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +#set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +#set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +#set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +#set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +#set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +#set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +#set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +#set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +#set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +#set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +#set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +#set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +#set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +#set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +#set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +#set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +#set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +#set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +#set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +#set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +#set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] + +# DDR4 C2 +#set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +#set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +#set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +#set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +#set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +#set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +#set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +#set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +#set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +#set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +#set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +#set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +#set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +#set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +#set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +#set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +#set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +#set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +#set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +#set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +#set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +#set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] +#set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] +#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] +#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] +#set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] +#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] +#set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] +#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] +#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] +#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] +#set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +#set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] +#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] +#set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +#set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] + +#set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +#set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +#set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +#set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +#set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +#set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +#set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +#set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +#set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +#set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +#set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +#set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +#set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +#set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +#set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +#set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +#set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +#set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +#set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +#set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +#set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +#set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +#set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +#set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +#set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +#set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +#set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +#set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +#set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +#set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +#set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +#set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +#set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +#set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +#set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +#set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +#set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +#set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +#set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +#set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +#set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +#set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +#set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +#set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +#set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +#set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +#set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +#set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +#set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +#set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +#set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +#set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +#set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +#set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +#set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +#set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +#set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +#set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +#set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +#set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +#set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +#set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +#set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +#set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +#set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +#set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +#set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +#set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +#set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +#set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +#set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +#set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +#set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +#set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +#set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +#set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +#set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +#set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +#set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +#set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +#set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +#set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +#set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +#set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +#set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +#set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +#set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +#set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +#set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +#set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +#set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] +#set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] +#set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] +#set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] +#set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] +#set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] +#set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] +#set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] +#set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] +#set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] +#set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] +#set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] +#set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] +#set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] +#set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] +#set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] +#set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] +#set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] + +# DDR4 C3 +#set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +#set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +#set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +#set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +#set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +#set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +#set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +#set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +#set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +#set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +#set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +#set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +#set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +#set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +#set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +#set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +#set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +#set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +#set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +#set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] +#set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] +#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] +#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] +#set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] +#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] +#set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] +#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] +#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] +#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] +#set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +#set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] +#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] +#set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +#set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] + +#set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +#set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +#set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +#set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +#set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +#set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +#set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +#set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +#set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +#set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +#set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +#set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +#set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +#set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +#set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +#set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +#set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +#set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +#set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +#set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +#set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +#set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +#set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +#set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +#set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +#set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +#set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +#set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +#set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +#set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +#set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +#set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +#set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +#set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +#set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +#set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +#set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +#set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +#set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +#set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +#set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +#set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +#set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +#set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +#set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +#set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +#set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +#set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +#set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +#set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +#set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +#set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +#set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +#set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +#set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +#set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +#set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +#set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +#set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +#set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] +#set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] +#set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] +#set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] +#set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] +#set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] +#set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] +#set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] +#set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] +#set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] +#set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] +#set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] +#set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] +#set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] +#set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] +#set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] +#set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] +#set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/src/cndm/board/Alveo/fpga/ip/ddr4_0.tcl b/src/cndm/board/Alveo/fpga/ip/ddr4_0.tcl new file mode 100644 index 0000000..2d5861e --- /dev/null +++ b/src/cndm/board/Alveo/fpga/ip/ddr4_0.tcl @@ -0,0 +1,18 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/src/cndm/board/Alveo/fpga/ip/pcie4_uscale_plus_0.tcl b/src/cndm/board/Alveo/fpga/ip/pcie4_uscale_plus_0.tcl new file mode 100644 index 0000000..6f2f919 --- /dev/null +++ b/src/cndm/board/Alveo/fpga/ip/pcie4_uscale_plus_0.tcl @@ -0,0 +1,30 @@ + +create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ + CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {false} \ + CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ + CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {false} \ + CONFIG.axisten_if_enable_client_tag {true} \ + CONFIG.axisten_if_width {512_bit} \ + CONFIG.extended_tag_field {true} \ + CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ + CONFIG.axisten_freq {250} \ + CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \ + CONFIG.PF0_CLASS_CODE {020000} \ + CONFIG.PF0_DEVICE_ID {C001} \ + CONFIG.PF0_SUBSYSTEM_ID {90c8} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ + CONFIG.pf0_bar0_64bit {true} \ + CONFIG.pf0_bar0_prefetchable {true} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {16} \ + CONFIG.pf0_msi_enabled {true} \ + CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ + CONFIG.en_msi_per_vec_masking {true} \ + CONFIG.legacy_ext_pcie_cfg_space_enabled {true} \ + CONFIG.vendor_id {1234} \ + CONFIG.mode_selection {Advanced} \ +] [get_ips pcie4_uscale_plus_0] diff --git a/src/cndm/board/Alveo/fpga/lib/taxi b/src/cndm/board/Alveo/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/cndm/board/Alveo/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/src/cndm/board/Alveo/fpga/rtl/fpga_au200.sv b/src/cndm/board/Alveo/fpga/rtl/fpga_au200.sv new file mode 100644 index 0000000..58d7246 --- /dev/null +++ b/src/cndm/board/Alveo/fpga/rtl/fpga_au200.sv @@ -0,0 +1,950 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2014-2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + // simulation (set to avoid vendor primitives) + parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") + parameter string VENDOR = "XILINX", + // device family + parameter string FAMILY = "virtexuplus", + + // FW ID + parameter FPGA_ID = 32'h4B37093, + parameter FW_ID = 32'h0000C001, + parameter FW_VER = 32'h000_01_000, + parameter BOARD_ID = 32'h10ee_90c8, + parameter BOARD_VER = 32'h001_00_000, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'h5f87c2e8, + parameter RELEASE_INFO = 32'h00000000, + + // PTP configuration + parameter logic PTP_TS_EN = 1'b1, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_W = 32, + parameter AXIL_CTRL_ADDR_W = 24, + + // MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 +) +( + /* + * Reset: Push button, active low + */ + input wire logic reset, + + /* + * GPIO + */ + input wire logic [3:0] sw, + output wire logic [2:0] led, + + /* + * I2C for board management + */ + inout wire logic i2c_scl, + inout wire logic i2c_sda, + + /* + * UART + */ + output wire logic uart_txd, + input wire logic uart_rxd, + + /* + * Ethernet: QSFP28 + */ + output wire logic qsfp0_tx_p[4], + output wire logic qsfp0_tx_n[4], + input wire logic qsfp0_rx_p[4], + input wire logic qsfp0_rx_n[4], + input wire logic qsfp0_mgt_refclk_0_p, + input wire logic qsfp0_mgt_refclk_0_n, + // input wire logic qsfp0_mgt_refclk_1_p, + // input wire logic qsfp0_mgt_refclk_1_n, + output wire logic qsfp0_modsell, + output wire logic qsfp0_resetl, + input wire logic qsfp0_modprsl, + input wire logic qsfp0_intl, + output wire logic qsfp0_lpmode, + // output wire logic qsfp0_refclk_reset, + // output wire logic [1:0] qsfp0_fs, + + output wire logic qsfp1_tx_p[4], + output wire logic qsfp1_tx_n[4], + input wire logic qsfp1_rx_p[4], + input wire logic qsfp1_rx_n[4], + input wire logic qsfp1_mgt_refclk_0_p, + input wire logic qsfp1_mgt_refclk_0_n, + // input wire logic qsfp1_mgt_refclk_1_p, + // input wire logic qsfp1_mgt_refclk_1_n, + output wire logic qsfp1_modsell, + output wire logic qsfp1_resetl, + input wire logic qsfp1_modprsl, + input wire logic qsfp1_intl, + output wire logic qsfp1_lpmode, + // output wire logic qsfp1_refclk_reset, + // output wire logic [1:0] qsfp1_fs, + + /* + * PCIe + */ + input wire logic [15:0] pcie_rx_p, + input wire logic [15:0] pcie_rx_n, + output wire logic [15:0] pcie_tx_p, + output wire logic [15:0] pcie_tx_n, + input wire logic pcie_refclk_p, + input wire logic pcie_refclk_n, + input wire logic pcie_reset_n +); + +// Clock and reset +wire pcie_user_clk; +wire pcie_user_rst; + +wire clk_156mhz_ref_int; + +// Internal 125 MHz clock +wire clk_125mhz_mmcm_out; +wire clk_125mhz_int; +wire rst_125mhz_int; + +wire mmcm_rst = 1'b0; +wire mmcm_locked; +wire mmcm_clkfb; + +// MMCM instance +MMCME4_BASE #( + // 156.25 MHz input + .CLKIN1_PERIOD(6.4), + .REF_JITTER1(0.010), + // 156.25 MHz input / 1 = 156.25 MHz PFD (range 10 MHz to 500 MHz) + .DIVCLK_DIVIDE(1), + // 156.25 MHz PFD * 8 = 1250 MHz VCO (range 800 MHz to 1600 MHz) + .CLKFBOUT_MULT_F(8), + .CLKFBOUT_PHASE(0), + // 1250 MHz / 10 = 125 MHz, 0 degrees + .CLKOUT0_DIVIDE_F(10), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + // Not used + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + // Not used + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + // Not used + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + // Not used + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT4_CASCADE("FALSE"), + // Not used + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + // Not used + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + + // optimized bandwidth + .BANDWIDTH("OPTIMIZED"), + // don't wait for lock during startup + .STARTUP_WAIT("FALSE") +) +clk_mmcm_inst ( + // 156.25 MHz input + .CLKIN1(clk_156mhz_ref_int), + // direct clkfb feeback + .CLKFBIN(mmcm_clkfb), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + // 125 MHz, 0 degrees + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + // Not used + .CLKOUT1(), + .CLKOUT1B(), + // Not used + .CLKOUT2(), + .CLKOUT2B(), + // Not used + .CLKOUT3(), + .CLKOUT3B(), + // Not used + .CLKOUT4(), + // Not used + .CLKOUT5(), + // Not used + .CLKOUT6(), + // reset input + .RST(mmcm_rst), + // don't power down + .PWRDWN(1'b0), + // locked output + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +taxi_sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// GPIO +wire [3:0] sw_int; + +taxi_debounce_switch #( + .WIDTH(4), + .N(4), + .RATE(156000) +) +debounce_switch_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + .in({sw}), + .out({sw_int}) +); + +// SI570 I2C +wire i2c_scl_i; +wire i2c_scl_o = 1'b1; +wire i2c_scl_t = 1'b1; +wire i2c_sda_i; +wire i2c_sda_o = 1'b1; +wire i2c_sda_t = 1'b1; + +assign i2c_scl_i = i2c_scl; +assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o; +assign i2c_sda_i = i2c_sda; +assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o; + +localparam PORT_CNT = 2; +localparam GTY_QUAD_CNT = PORT_CNT; +localparam GTY_CNT = GTY_QUAD_CNT*4; +localparam GTY_CLK_CNT = GTY_QUAD_CNT; + +wire eth_gty_tx_p[GTY_CNT]; +wire eth_gty_tx_n[GTY_CNT]; +wire eth_gty_rx_p[GTY_CNT]; +wire eth_gty_rx_n[GTY_CNT]; +wire eth_gty_mgt_refclk_p[GTY_CLK_CNT]; +wire eth_gty_mgt_refclk_n[GTY_CLK_CNT]; +wire eth_gty_mgt_refclk_out[GTY_CLK_CNT]; + +assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4]; +assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4]; +assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p; +assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n; + +assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4]; +assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4]; +assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p; +assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n; + +assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_0_p; +assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_0_n; +assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_0_p; +assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n; + +assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0]; + +// Flash +wire qspi_clk_int; +wire [3:0] qspi_dq_int; +wire [3:0] qspi_dq_i_int; +wire [3:0] qspi_dq_o_int; +wire [3:0] qspi_dq_oe_int; +wire qspi_cs_int; + +reg qspi_clk_reg; +reg [3:0] qspi_dq_o_reg; +reg [3:0] qspi_dq_oe_reg; +reg qspi_cs_reg; + +always_ff @(posedge pcie_user_clk) begin + qspi_clk_reg <= qspi_clk_int; + qspi_dq_o_reg <= qspi_dq_o_int; + qspi_dq_oe_reg <= qspi_dq_oe_int; + qspi_cs_reg <= qspi_cs_int; +end + +taxi_sync_signal #( + .WIDTH(8), + .N(2) +) +flash_sync_inst ( + .clk(pcie_user_clk), + .in({qspi_dq_int}), + .out({qspi_dq_i_int}) +); + +STARTUPE3 +startupe3_inst ( + .CFGCLK(), + .CFGMCLK(), + .DI(qspi_dq_int), + .DO(qspi_dq_o_reg), + .DTS(~qspi_dq_oe_reg), + .EOS(), + .FCSBO(qspi_cs_reg), + .FCSBTS(1'b0), + .GSR(1'b0), + .GTS(1'b0), + .KEYCLEARB(1'b1), + .PACK(1'b0), + .PREQ(), + .USRCCLKO(qspi_clk_reg), + .USRCCLKTS(1'b0), + .USRDONEO(1'b0), + .USRDONETS(1'b1) +); + +// FPGA boot +wire fpga_boot; +wire fpga_boot_sync; + +taxi_sync_signal #( + .WIDTH(1), + .N(2) +) +fpga_boot_sync_inst ( + .clk(clk_125mhz_int), + .in({fpga_boot}), + .out({fpga_boot_sync}) +); + +wire icap_avail; +logic [2:0] icap_state_reg = 0; +logic icap_csib_reg = 1'b1; +logic icap_rdwrb_reg = 1'b0; +logic [31:0] icap_di_reg = 32'hffffffff; + +wire [31:0] icap_di_rev; + +assign icap_di_rev[ 7] = icap_di_reg[ 0]; +assign icap_di_rev[ 6] = icap_di_reg[ 1]; +assign icap_di_rev[ 5] = icap_di_reg[ 2]; +assign icap_di_rev[ 4] = icap_di_reg[ 3]; +assign icap_di_rev[ 3] = icap_di_reg[ 4]; +assign icap_di_rev[ 2] = icap_di_reg[ 5]; +assign icap_di_rev[ 1] = icap_di_reg[ 6]; +assign icap_di_rev[ 0] = icap_di_reg[ 7]; + +assign icap_di_rev[15] = icap_di_reg[ 8]; +assign icap_di_rev[14] = icap_di_reg[ 9]; +assign icap_di_rev[13] = icap_di_reg[10]; +assign icap_di_rev[12] = icap_di_reg[11]; +assign icap_di_rev[11] = icap_di_reg[12]; +assign icap_di_rev[10] = icap_di_reg[13]; +assign icap_di_rev[ 9] = icap_di_reg[14]; +assign icap_di_rev[ 8] = icap_di_reg[15]; + +assign icap_di_rev[23] = icap_di_reg[16]; +assign icap_di_rev[22] = icap_di_reg[17]; +assign icap_di_rev[21] = icap_di_reg[18]; +assign icap_di_rev[20] = icap_di_reg[19]; +assign icap_di_rev[19] = icap_di_reg[20]; +assign icap_di_rev[18] = icap_di_reg[21]; +assign icap_di_rev[17] = icap_di_reg[22]; +assign icap_di_rev[16] = icap_di_reg[23]; + +assign icap_di_rev[31] = icap_di_reg[24]; +assign icap_di_rev[30] = icap_di_reg[25]; +assign icap_di_rev[29] = icap_di_reg[26]; +assign icap_di_rev[28] = icap_di_reg[27]; +assign icap_di_rev[27] = icap_di_reg[28]; +assign icap_di_rev[26] = icap_di_reg[29]; +assign icap_di_rev[25] = icap_di_reg[30]; +assign icap_di_rev[24] = icap_di_reg[31]; + +always_ff @(posedge clk_125mhz_int) begin + case (icap_state_reg) + 0: begin + icap_state_reg <= 0; + icap_csib_reg <= 1'b1; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hffffffff; // dummy word + + if (fpga_boot_sync && icap_avail) begin + icap_state_reg <= 1; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hffffffff; // dummy word + end + end + 1: begin + icap_state_reg <= 2; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'hAA995566; // sync word + end + 2: begin + icap_state_reg <= 3; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h20000000; // type 1 noop + end + 3: begin + icap_state_reg <= 4; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h30008001; // write 1 word to CMD + end + 4: begin + icap_state_reg <= 5; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h0000000F; // IPROG + end + 5: begin + icap_state_reg <= 0; + icap_csib_reg <= 1'b0; + icap_rdwrb_reg <= 1'b0; + icap_di_reg <= 32'h20000000; // type 1 noop + end + endcase +end + +ICAPE3 +icape3_inst ( + .AVAIL(icap_avail), + .CLK(clk_125mhz_int), + .CSIB(icap_csib_reg), + .I(icap_di_rev), + .O(), + .PRDONE(), + .PRERROR(), + .RDWRB(icap_rdwrb_reg) +); + +// PCIe +localparam AXIS_PCIE_DATA_W = 512; +localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32); +localparam AXIS_PCIE_RC_USER_W = AXIS_PCIE_DATA_W < 512 ? 75 : 161; +localparam AXIS_PCIE_RQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 62 : 137; +localparam AXIS_PCIE_CQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 85 : 183; +localparam AXIS_PCIE_CC_USER_W = AXIS_PCIE_DATA_W < 512 ? 33 : 81; +localparam RC_STRADDLE = 0; // AXIS_PCIE_DATA_W >= 256; +localparam RQ_STRADDLE = 0; // AXIS_PCIE_DATA_W >= 512; +localparam CQ_STRADDLE = 0; // AXIS_PCIE_DATA_W >= 512; +localparam CC_STRADDLE = 0; // AXIS_PCIE_DATA_W >= 512; + +localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6; +localparam RQ_SEQ_NUM_EN = 1; + +localparam PCIE_TAG_CNT = AXIS_PCIE_RQ_USER_W == 60 ? 64 : 256; +localparam BAR0_APERTURE = 24; + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_CQ_USER_W) +) axis_pcie_cq(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_CC_USER_W) +) axis_pcie_cc(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_RQ_USER_W) +) axis_pcie_rq(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_RC_USER_W) +) axis_pcie_rc(); + +wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0; +wire pcie_rq_seq_num_vld0; +wire [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1; +wire pcie_rq_seq_num_vld1; + +wire [2:0] cfg_max_payload; +wire [2:0] cfg_max_read_req; +wire [3:0] cfg_rcb_status; + +wire [9:0] cfg_mgmt_addr; +wire [7:0] cfg_mgmt_function_number; +wire cfg_mgmt_write; +wire [31:0] cfg_mgmt_write_data; +wire [3:0] cfg_mgmt_byte_enable; +wire cfg_mgmt_read; +wire [31:0] cfg_mgmt_read_data; +wire cfg_mgmt_read_write_done; + +wire [7:0] cfg_fc_ph; +wire [11:0] cfg_fc_pd; +wire [7:0] cfg_fc_nph; +wire [11:0] cfg_fc_npd; +wire [7:0] cfg_fc_cplh; +wire [11:0] cfg_fc_cpld; +wire [2:0] cfg_fc_sel; + +wire cfg_ext_read_received; +wire cfg_ext_write_received; +wire [9:0] cfg_ext_register_number; +wire [7:0] cfg_ext_function_number; +wire [31:0] cfg_ext_write_data; +wire [3:0] cfg_ext_write_byte_enable; +wire [31:0] cfg_ext_read_data; +wire cfg_ext_read_data_valid; + +// wire [3:0] cfg_interrupt_msix_enable; +// wire [3:0] cfg_interrupt_msix_mask; +// wire [251:0] cfg_interrupt_msix_vf_enable; +// wire [251:0] cfg_interrupt_msix_vf_mask; +// wire [63:0] cfg_interrupt_msix_address; +// wire [31:0] cfg_interrupt_msix_data; +// wire cfg_interrupt_msix_int; +// wire [1:0] cfg_interrupt_msix_vec_pending; +// wire cfg_interrupt_msix_vec_pending_status; +// wire cfg_interrupt_msix_sent; +// wire cfg_interrupt_msix_fail; +// wire [7:0] cfg_interrupt_msi_function_number; + +wire [3:0] cfg_interrupt_msi_enable; +wire [11:0] cfg_interrupt_msi_mmenable; +wire cfg_interrupt_msi_mask_update; +wire [31:0] cfg_interrupt_msi_data; +wire [1:0] cfg_interrupt_msi_select; +wire [31:0] cfg_interrupt_msi_int; +wire [31:0] cfg_interrupt_msi_pending_status; +wire cfg_interrupt_msi_pending_status_data_enable; +wire [1:0] cfg_interrupt_msi_pending_status_function_num; +wire cfg_interrupt_msi_sent; +wire cfg_interrupt_msi_fail; +wire [2:0] cfg_interrupt_msi_attr; +wire cfg_interrupt_msi_tph_present; +wire [1:0] cfg_interrupt_msi_tph_type; +wire [7:0] cfg_interrupt_msi_tph_st_tag; +wire [7:0] cfg_interrupt_msi_function_number; + +wire stat_err_cor; +wire stat_err_uncor; + +wire pcie_sys_clk; +wire pcie_sys_clk_gt; + +IBUFDS_GTE4 #( + .REFCLK_HROW_CK_SEL(2'b00) +) +ibufds_gte4_pcie_refclk_inst ( + .I (pcie_refclk_p), + .IB (pcie_refclk_n), + .CEB (1'b0), + .O (pcie_sys_clk_gt), + .ODIV2 (pcie_sys_clk) +); + +pcie4_uscale_plus_0 +pcie4_uscale_plus_inst ( + .pci_exp_txn(pcie_tx_n), + .pci_exp_txp(pcie_tx_p), + .pci_exp_rxn(pcie_rx_n), + .pci_exp_rxp(pcie_rx_p), + .user_clk(pcie_user_clk), + .user_reset(pcie_user_rst), + .user_lnk_up(), + + .s_axis_rq_tdata(axis_pcie_rq.tdata), + .s_axis_rq_tkeep(axis_pcie_rq.tkeep), + .s_axis_rq_tlast(axis_pcie_rq.tlast), + .s_axis_rq_tready(axis_pcie_rq.tready), + .s_axis_rq_tuser(axis_pcie_rq.tuser), + .s_axis_rq_tvalid(axis_pcie_rq.tvalid), + + .m_axis_rc_tdata(axis_pcie_rc.tdata), + .m_axis_rc_tkeep(axis_pcie_rc.tkeep), + .m_axis_rc_tlast(axis_pcie_rc.tlast), + .m_axis_rc_tready(axis_pcie_rc.tready), + .m_axis_rc_tuser(axis_pcie_rc.tuser), + .m_axis_rc_tvalid(axis_pcie_rc.tvalid), + + .m_axis_cq_tdata(axis_pcie_cq.tdata), + .m_axis_cq_tkeep(axis_pcie_cq.tkeep), + .m_axis_cq_tlast(axis_pcie_cq.tlast), + .m_axis_cq_tready(axis_pcie_cq.tready), + .m_axis_cq_tuser(axis_pcie_cq.tuser), + .m_axis_cq_tvalid(axis_pcie_cq.tvalid), + + .s_axis_cc_tdata(axis_pcie_cc.tdata), + .s_axis_cc_tkeep(axis_pcie_cc.tkeep), + .s_axis_cc_tlast(axis_pcie_cc.tlast), + .s_axis_cc_tready(axis_pcie_cc.tready), + .s_axis_cc_tuser(axis_pcie_cc.tuser), + .s_axis_cc_tvalid(axis_pcie_cc.tvalid), + + .pcie_rq_seq_num0(pcie_rq_seq_num0), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), + .pcie_rq_seq_num1(pcie_rq_seq_num1), + .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), + .pcie_rq_tag0(), + .pcie_rq_tag1(), + .pcie_rq_tag_av(), + .pcie_rq_tag_vld0(), + .pcie_rq_tag_vld1(), + + .pcie_tfc_nph_av(), + .pcie_tfc_npd_av(), + + .pcie_cq_np_req(1'b1), + .pcie_cq_np_req_count(), + + .cfg_phy_link_down(), + .cfg_phy_link_status(), + .cfg_negotiated_width(), + .cfg_current_speed(), + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_function_status(), + .cfg_function_power_state(), + .cfg_vf_status(), + .cfg_vf_power_state(), + .cfg_link_power_state(), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + .cfg_mgmt_debug_access(1'b0), + + .cfg_err_cor_out(), + .cfg_err_nonfatal_out(), + .cfg_err_fatal_out(), + .cfg_local_error_valid(), + .cfg_local_error_out(), + .cfg_ltssm_state(), + .cfg_rx_pm_state(), + .cfg_tx_pm_state(), + .cfg_rcb_status(cfg_rcb_status), + .cfg_obff_enable(), + .cfg_pl_status_change(), + .cfg_tph_requester_enable(), + .cfg_tph_st_mode(), + .cfg_vf_tph_requester_enable(), + .cfg_vf_tph_st_mode(), + + .cfg_msg_received(), + .cfg_msg_received_data(), + .cfg_msg_received_type(), + .cfg_msg_transmit(1'b0), + .cfg_msg_transmit_type(3'd0), + .cfg_msg_transmit_data(32'd0), + .cfg_msg_transmit_done(), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_dsn(64'd0), + + .cfg_bus_number(), + + .cfg_power_state_change_ack(1'b1), + .cfg_power_state_change_interrupt(), + + .cfg_err_cor_in(stat_err_cor), + .cfg_err_uncor_in(stat_err_uncor), + .cfg_flr_in_process(), + .cfg_flr_done(4'd0), + .cfg_vf_flr_in_process(), + .cfg_vf_flr_func_num(8'd0), + .cfg_vf_flr_done(8'd0), + + .cfg_link_training_enable(1'b1), + + .cfg_ext_read_received(cfg_ext_read_received), + .cfg_ext_write_received(cfg_ext_write_received), + .cfg_ext_register_number(cfg_ext_register_number), + .cfg_ext_function_number(cfg_ext_function_number), + .cfg_ext_write_data(cfg_ext_write_data), + .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable), + .cfg_ext_read_data(cfg_ext_read_data), + .cfg_ext_read_data_valid(cfg_ext_read_data_valid), + + .cfg_interrupt_int(4'd0), + .cfg_interrupt_pending(4'd0), + .cfg_interrupt_sent(), + // .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + // .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + // .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + // .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + // .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + // .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + // .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + // .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + // .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + // .cfg_interrupt_msi_sent(cfg_interrupt_msix_sent), + // .cfg_interrupt_msi_fail(cfg_interrupt_msix_fail), + // .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .cfg_pm_aspm_l1_entry_reject(1'b0), + .cfg_pm_aspm_tx_l0s_entry_disable(1'b0), + + .cfg_hot_reset_out(), + + .cfg_config_space_enable(1'b1), + .cfg_req_pm_transition_l23_ready(1'b0), + .cfg_hot_reset_in(1'b0), + + .cfg_ds_port_number(8'd0), + .cfg_ds_bus_number(8'd0), + .cfg_ds_device_number(5'd0), + + .sys_clk(pcie_sys_clk), + .sys_clk_gt(pcie_sys_clk_gt), + .sys_reset(pcie_reset_n), + + .phy_rdy_out() +); + +wire uart_rxd_int[1]; +wire uart_txd_int[1]; + +assign uart_txd = uart_txd_int[0]; +assign uart_rxd_int[0] = uart_rxd; + +fpga_core #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + + // Board configuration + .SW_CNT(4), + .LED_CNT(3), + .UART_CNT(1), + .PORT_CNT(PORT_CNT), + .GTY_QUAD_CNT(GTY_QUAD_CNT), + .GTY_CNT(GTY_CNT), + .GTY_CLK_CNT(GTY_CLK_CNT), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // PTP configuration + .PTP_TS_EN(PTP_TS_EN), + .PTP_CLK_PER_NS_NUM(32), + .PTP_CLK_PER_NS_DENOM(5), + + // PCIe interface configuration + .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W), + .AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W), + + // MAC configuration + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) +) +core_inst ( + /* + * Clock: 125MHz + * Synchronous reset + */ + .clk_125mhz(clk_125mhz_int), + .rst_125mhz(rst_125mhz_int), + + /* + * GPIO + */ + .sw(sw_int), + .led(led), + .port_led_act(), + .port_led_stat_r(), + .port_led_stat_g(), + .port_led_stat_b(), + .port_led_stat_y(), + + /* + * UART + */ + .uart_txd(uart_txd_int), + .uart_rxd(uart_rxd_int), + + /* + * Ethernet + */ + .eth_gty_tx_p(eth_gty_tx_p), + .eth_gty_tx_n(eth_gty_tx_n), + .eth_gty_rx_p(eth_gty_rx_p), + .eth_gty_rx_n(eth_gty_rx_n), + .eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p), + .eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n), + .eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out), + + .eth_port_modsell({qsfp1_modsell, qsfp0_modsell}), + .eth_port_resetl({qsfp1_resetl, qsfp0_resetl}), + .eth_port_modprsl({qsfp1_modprsl, qsfp0_modprsl}), + .eth_port_intl({qsfp1_intl, qsfp0_intl}), + .eth_port_lpmode({qsfp1_lpmode, qsfp0_lpmode}), + + /* + * PCIe + */ + .pcie_clk(pcie_user_clk), + .pcie_rst(pcie_user_rst), + .s_axis_pcie_cq(axis_pcie_cq), + .m_axis_pcie_cc(axis_pcie_cc), + .m_axis_pcie_rq(axis_pcie_rq), + .s_axis_pcie_rc(axis_pcie_rc), + + .pcie_rq_seq_num0(pcie_rq_seq_num0), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), + .pcie_rq_seq_num1(pcie_rq_seq_num1), + .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_ext_read_received(cfg_ext_read_received), + .cfg_ext_write_received(cfg_ext_write_received), + .cfg_ext_register_number(cfg_ext_register_number), + .cfg_ext_function_number(cfg_ext_function_number), + .cfg_ext_write_data(cfg_ext_write_data), + .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable), + .cfg_ext_read_data(cfg_ext_read_data), + .cfg_ext_read_data_valid(cfg_ext_read_data_valid), + + // .cfg_interrupt_msix_enable(cfg_interrupt_msix_enable), + // .cfg_interrupt_msix_mask(cfg_interrupt_msix_mask), + // .cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable), + // .cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask), + // .cfg_interrupt_msix_address(cfg_interrupt_msix_address), + // .cfg_interrupt_msix_data(cfg_interrupt_msix_data), + // .cfg_interrupt_msix_int(cfg_interrupt_msix_int), + // .cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending), + // .cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status), + // .cfg_interrupt_msix_sent(cfg_interrupt_msix_sent), + // .cfg_interrupt_msix_fail(cfg_interrupt_msix_fail), + // .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + /* + * QSPI flash + */ + .fpga_boot(fpga_boot), + .qspi_clk(qspi_clk_int), + .qspi_dq_i(qspi_dq_i_int), + .qspi_dq_o(qspi_dq_o_int), + .qspi_dq_oe(qspi_dq_oe_int), + .qspi_cs(qspi_cs_int) +); + +endmodule + +`resetall diff --git a/src/cndm/board/Alveo/fpga/rtl/fpga_core.sv b/src/cndm/board/Alveo/fpga/rtl/fpga_core.sv new file mode 100644 index 0000000..5f6158f --- /dev/null +++ b/src/cndm/board/Alveo/fpga/rtl/fpga_core.sv @@ -0,0 +1,851 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2014-2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core # +( + // simulation (set to avoid vendor primitives) + parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") + parameter string VENDOR = "XILINX", + // device family + parameter string FAMILY = "virtexuplus", + + // Board configuration + parameter SW_CNT = 4, + parameter LED_CNT = 3, + parameter UART_CNT = 1, + parameter PORT_CNT = 2, + parameter PORT_LED_CNT = PORT_CNT, + parameter GTY_QUAD_CNT = PORT_CNT, + parameter GTY_CNT = GTY_QUAD_CNT*4, + parameter GTY_CLK_CNT = GTY_QUAD_CNT, + + // FW ID + parameter FPGA_ID = 32'h4B37093, + parameter FW_ID = 32'h0000C001, + parameter FW_VER = 32'h000_01_000, + parameter BOARD_ID = 32'h10ee_90c8, + parameter BOARD_VER = 32'h001_00_000, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'h5f87c2e8, + parameter RELEASE_INFO = 32'h00000000, + + // PTP configuration + parameter logic PTP_TS_EN = 1'b1, + parameter PTP_CLK_PER_NS_NUM = 32, + parameter PTP_CLK_PER_NS_DENOM = 5, + + // PCIe interface configuration + parameter RQ_SEQ_NUM_W = 6, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_W = 32, + parameter AXIL_CTRL_ADDR_W = 24, + + // MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 +) +( + /* + * Clock: 125MHz + * Synchronous reset + */ + input wire logic clk_125mhz, + input wire logic rst_125mhz, + + /* + * GPIO + */ + input wire logic [SW_CNT-1:0] sw, + output wire logic [LED_CNT-1:0] led, + output wire logic [PORT_LED_CNT-1:0] port_led_act, + output wire logic [PORT_LED_CNT-1:0] port_led_stat_r, + output wire logic [PORT_LED_CNT-1:0] port_led_stat_g, + output wire logic [PORT_LED_CNT-1:0] port_led_stat_b, + output wire logic [PORT_LED_CNT-1:0] port_led_stat_y, + + /* + * UART + */ + output wire logic uart_txd[UART_CNT], + input wire logic uart_rxd[UART_CNT], + + /* + * Ethernet + */ + output wire logic eth_gty_tx_p[GTY_CNT], + output wire logic eth_gty_tx_n[GTY_CNT], + input wire logic eth_gty_rx_p[GTY_CNT], + input wire logic eth_gty_rx_n[GTY_CNT], + input wire logic eth_gty_mgt_refclk_p[GTY_CLK_CNT], + input wire logic eth_gty_mgt_refclk_n[GTY_CLK_CNT], + output wire logic eth_gty_mgt_refclk_out[GTY_CLK_CNT], + + output wire logic [PORT_CNT-1:0] eth_port_modsell, + output wire logic [PORT_CNT-1:0] eth_port_resetl, + input wire logic [PORT_CNT-1:0] eth_port_modprsl, + input wire logic [PORT_CNT-1:0] eth_port_intl, + output wire logic [PORT_CNT-1:0] eth_port_lpmode, + + /* + * PCIe + */ + input wire logic pcie_clk, + input wire logic pcie_rst, + taxi_axis_if.snk s_axis_pcie_cq, + taxi_axis_if.src m_axis_pcie_cc, + taxi_axis_if.src m_axis_pcie_rq, + taxi_axis_if.snk s_axis_pcie_rc, + + input wire logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0, + input wire logic pcie_rq_seq_num_vld0, + input wire logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1, + input wire logic pcie_rq_seq_num_vld1, + + input wire logic [2:0] cfg_max_payload, + input wire logic [2:0] cfg_max_read_req, + input wire logic [3:0] cfg_rcb_status, + + output wire logic [9:0] cfg_mgmt_addr, + output wire logic [7:0] cfg_mgmt_function_number, + output wire logic cfg_mgmt_write, + output wire logic [31:0] cfg_mgmt_write_data, + output wire logic [3:0] cfg_mgmt_byte_enable, + output wire logic cfg_mgmt_read, + output wire logic [31:0] cfg_mgmt_read_data, + input wire logic cfg_mgmt_read_write_done, + + input wire logic [7:0] cfg_fc_ph, + input wire logic [11:0] cfg_fc_pd, + input wire logic [7:0] cfg_fc_nph, + input wire logic [11:0] cfg_fc_npd, + input wire logic [7:0] cfg_fc_cplh, + input wire logic [11:0] cfg_fc_cpld, + output wire logic [2:0] cfg_fc_sel, + + input wire logic cfg_ext_read_received, + input wire logic cfg_ext_write_received, + input wire logic [9:0] cfg_ext_register_number, + input wire logic [7:0] cfg_ext_function_number, + input wire logic [31:0] cfg_ext_write_data, + input wire logic [3:0] cfg_ext_write_byte_enable, + output wire logic [31:0] cfg_ext_read_data, + output wire logic cfg_ext_read_data_valid, + + input wire logic [3:0] cfg_interrupt_msi_enable, + input wire logic [11:0] cfg_interrupt_msi_mmenable, + input wire logic cfg_interrupt_msi_mask_update, + input wire logic [31:0] cfg_interrupt_msi_data, + output wire logic [1:0] cfg_interrupt_msi_select, + output wire logic [31:0] cfg_interrupt_msi_int, + output wire logic [31:0] cfg_interrupt_msi_pending_status, + output wire logic cfg_interrupt_msi_pending_status_data_enable, + output wire logic [1:0] cfg_interrupt_msi_pending_status_function_num, + input wire logic cfg_interrupt_msi_sent, + input wire logic cfg_interrupt_msi_fail, + output wire logic [2:0] cfg_interrupt_msi_attr, + output wire logic cfg_interrupt_msi_tph_present, + output wire logic [1:0] cfg_interrupt_msi_tph_type, + output wire logic [7:0] cfg_interrupt_msi_tph_st_tag, + output wire logic [7:0] cfg_interrupt_msi_function_number, + + /* + * QSPI flash + */ + output wire logic fpga_boot, + output wire logic qspi_clk, + input wire logic [3:0] qspi_dq_i, + output wire logic [3:0] qspi_dq_o, + output wire logic [3:0] qspi_dq_oe, + output wire logic qspi_cs +); + +localparam logic PTP_TS_FMT_TOD = 1'b0; +localparam PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 48; + +// flashing via PCIe VPD +pyrite_pcie_us_vpd_qspi #( + .VPD_CAP_ID(8'h03), + .VPD_CAP_OFFSET(8'hB0), + .VPD_CAP_NEXT(8'h00), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Flash + .FLASH_SEG_COUNT(2), + .FLASH_SEG_DEFAULT(1), + .FLASH_SEG_FALLBACK(0), + .FLASH_SEG0_SIZE(32'h01002000), + .FLASH_DATA_W(4), + .FLASH_DUAL_QSPI(1'b0) +) +pyrite_inst ( + .clk(pcie_clk), + .rst(pcie_rst), + + /* + * PCIe + */ + .cfg_ext_read_received(cfg_ext_read_received), + .cfg_ext_write_received(cfg_ext_write_received), + .cfg_ext_register_number(cfg_ext_register_number), + .cfg_ext_function_number(cfg_ext_function_number), + .cfg_ext_write_data(cfg_ext_write_data), + .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable), + .cfg_ext_read_data(cfg_ext_read_data), + .cfg_ext_read_data_valid(cfg_ext_read_data_valid), + + /* + * QSPI flash + */ + .fpga_boot(fpga_boot), + .qspi_clk(qspi_clk), + .qspi_0_dq_i(qspi_dq_i), + .qspi_0_dq_o(qspi_dq_o), + .qspi_0_dq_oe(qspi_dq_oe), + .qspi_0_cs(qspi_cs), + .qspi_1_dq_i('0), + .qspi_1_dq_o(), + .qspi_1_dq_oe(), + .qspi_1_cs() +); + +// XFCP +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us(); + +taxi_xfcp_if_uart #( + .TX_FIFO_DEPTH(512), + .RX_FIFO_DEPTH(512) +) +xfcp_if_uart_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * UART interface + */ + .uart_rxd(uart_rxd[0]), + .uart_txd(uart_txd[0]), + + /* + * XFCP downstream interface + */ + .xfcp_dsp_ds(xfcp_ds), + .xfcp_dsp_us(xfcp_us), + + /* + * Configuration + */ + .prescale(16'(125000000/3000000)) +); + +localparam XFCP_PORTS = 1+GTY_QUAD_CNT; + +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[XFCP_PORTS](), xfcp_sw_us[XFCP_PORTS](); + +taxi_xfcp_switch #( + .XFCP_ID_STR("Alveo"), + .XFCP_EXT_ID(0), + .XFCP_EXT_ID_STR("Taxi example"), + .PORTS($size(xfcp_sw_us)) +) +xfcp_sw_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_ds), + .xfcp_usp_us(xfcp_us), + + /* + * XFCP downstream ports + */ + .xfcp_dsp_ds(xfcp_sw_ds), + .xfcp_dsp_us(xfcp_sw_us) +); + +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat(); + +taxi_xfcp_mod_stats #( + .XFCP_ID_STR("Statistics"), + .XFCP_EXT_ID(0), + .XFCP_EXT_ID_STR(""), + .STAT_COUNT_W(64), + .STAT_PIPELINE(2) +) +xfcp_stats_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_sw_ds[0]), + .xfcp_usp_us(xfcp_sw_us[0]), + + /* + * Statistics increment input + */ + .s_axis_stat(axis_stat) +); + +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[GTY_QUAD_CNT](); + +taxi_axis_arb_mux #( + .S_COUNT($size(axis_eth_stat)), + .UPDATE_TID(1'b0), + .ARB_ROUND_ROBIN(1'b1), + .ARB_LSB_HIGH_PRIO(1'b0) +) +stat_mux_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * AXI4-Stream inputs (sink) + */ + .s_axis(axis_eth_stat), + + /* + * AXI4-Stream output (source) + */ + .m_axis(axis_stat) +); + +// Additional UARTs +for (genvar n = 1; n < UART_CNT; n = n + 1) begin : uart_ch + + taxi_axis_if #(.DATA_W(8)) axis_uart(); + + taxi_uart + uart_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * AXI4-Stream input (sink) + */ + .s_axis_tx(axis_uart), + + /* + * AXI4-Stream output (source) + */ + .m_axis_rx(axis_uart), + + /* + * UART interface + */ + .rxd(uart_rxd[n]), + .txd(uart_txd[n]), + + /* + * Status + */ + .tx_busy(), + .rx_busy(), + .rx_overrun_error(), + .rx_frame_error(), + + /* + * Configuration + */ + .prescale(16'(125000000/115200)) + ); + +end + +// Ethernet +assign eth_port_modsell = '1; +assign eth_port_resetl = '1; +assign eth_port_lpmode = '0; + +wire eth_gty_tx_clk[GTY_CNT]; +wire eth_gty_tx_rst[GTY_CNT]; +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) eth_gty_axis_tx[GTY_CNT](); +taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT](); + +wire eth_gty_rx_clk[GTY_CNT]; +wire eth_gty_rx_rst[GTY_CNT]; +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1+PTP_TS_W)) eth_gty_axis_rx[GTY_CNT](); + +wire eth_gty_rx_status[GTY_CNT]; + +wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood; + +wire eth_gty_mgt_refclk[GTY_CLK_CNT]; +wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT]; + +wire eth_gty_rst[GTY_CLK_CNT]; + +for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk + + wire eth_gty_mgt_refclk_int; + + if (SIM) begin + + assign eth_gty_mgt_refclk[n] = eth_gty_mgt_refclk_p[n]; + assign eth_gty_mgt_refclk_int = eth_gty_mgt_refclk_p[n]; + assign eth_gty_mgt_refclk_bufg[n] = eth_gty_mgt_refclk_int; + + end else begin + + IBUFDS_GTE4 ibufds_gte4_eth_gty_mgt_refclk_inst ( + .I (eth_gty_mgt_refclk_p[n]), + .IB (eth_gty_mgt_refclk_n[n]), + .CEB (1'b0), + .O (eth_gty_mgt_refclk[n]), + .ODIV2 (eth_gty_mgt_refclk_int) + ); + + BUFG_GT bufg_gt_eth_gty_mgt_refclk_inst ( + .CE (ð_gty_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (eth_gty_mgt_refclk_int), + .O (eth_gty_mgt_refclk_bufg[n]) + ); + + end + + assign eth_gty_mgt_refclk_out[n] = eth_gty_mgt_refclk_bufg[n]; + + taxi_sync_reset #( + .N(4) + ) + qsfp_sync_reset_inst ( + .clk(eth_gty_mgt_refclk_bufg[n]), + .rst(rst_125mhz), + .out(eth_gty_rst[n]) + ); + +end + +wire ptp_clk = eth_gty_mgt_refclk_bufg[0]; +wire ptp_rst = eth_gty_rst[0]; +wire ptp_sample_clk = clk_125mhz; +wire ptp_td_sd; +wire ptp_pps; +wire ptp_pps_str; + +assign led[0] = ptp_pps_str; + +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"}; + +for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad + + localparam CLK = n; + localparam CNT = 4; + + taxi_apb_if #( + .ADDR_W(18), + .DATA_W(16) + ) + gt_apb_ctrl(); + + taxi_xfcp_mod_apb #( + .XFCP_EXT_ID_STR("GTY CTRL") + ) + xfcp_mod_apb_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_sw_ds[n+1]), + .xfcp_usp_us(xfcp_sw_us[n+1]), + + /* + * APB master interface + */ + .m_apb(gt_apb_ctrl) + ); + + taxi_eth_mac_25g_us #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + + .CNT(CNT), + + // GT config + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + + // GT type + .GT_TYPE("GTY"), + + // MAC/PHY config + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .DATA_W(MAC_DATA_W), + .PADDING_EN(1'b1), + .DIC_EN(1'b1), + .MIN_FRAME_LEN(64), + .PTP_TS_EN(PTP_TS_EN), + .PTP_TD_EN(PTP_TS_EN), + .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), + .PTP_TS_W(PTP_TS_W), + .PTP_TD_SDI_PIPELINE(2), + .PRBS31_EN(1'b0), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/6.4), + .STAT_EN(1), + .STAT_TX_LEVEL(1), + .STAT_RX_LEVEL(1), + .STAT_ID_BASE(n*CNT*(16+16)), + .STAT_UPDATE_PERIOD(1024), + .STAT_STR_EN(1), + .STAT_PREFIX_STR(n == 0 ? STAT_PREFIX_STR_QSFP1 : STAT_PREFIX_STR_QSFP2) + ) + mac_inst ( + .xcvr_ctrl_clk(clk_125mhz), + .xcvr_ctrl_rst(eth_gty_rst[CLK]), + + /* + * Transceiver control + */ + .s_apb_ctrl(gt_apb_ctrl), + + /* + * Common + */ + .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]), + .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[CLK]), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), + + /* + * Serial data + */ + .xcvr_txp(eth_gty_tx_p[n*CNT +: CNT]), + .xcvr_txn(eth_gty_tx_n[n*CNT +: CNT]), + .xcvr_rxp(eth_gty_rx_p[n*CNT +: CNT]), + .xcvr_rxn(eth_gty_rx_n[n*CNT +: CNT]), + + /* + * MAC clocks + */ + .rx_clk(eth_gty_rx_clk[n*CNT +: CNT]), + .rx_rst_in('{CNT{1'b0}}), + .rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]), + .tx_clk(eth_gty_tx_clk[n*CNT +: CNT]), + .tx_rst_in('{CNT{1'b0}}), + .tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(eth_gty_axis_tx[n*CNT +: CNT]), + .m_axis_tx_cpl(eth_gty_axis_tx_cpl[n*CNT +: CNT]), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]), + + /* + * PTP clock + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sdi(ptp_td_sd), + .tx_ptp_ts_in('{CNT{'0}}), + .tx_ptp_ts_out(), + .tx_ptp_ts_step_out(), + .tx_ptp_locked(), + .rx_ptp_ts_in('{CNT{'0}}), + .rx_ptp_ts_out(), + .rx_ptp_ts_step_out(), + .rx_ptp_locked(), + + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + .tx_lfc_req('{CNT{1'b0}}), + .tx_lfc_resend('{CNT{1'b0}}), + .rx_lfc_en('{CNT{1'b0}}), + .rx_lfc_req(), + .rx_lfc_ack('{CNT{1'b0}}), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + .tx_pfc_req('{CNT{'0}}), + .tx_pfc_resend('{CNT{1'b0}}), + .rx_pfc_en('{CNT{'0}}), + .rx_pfc_req(), + .rx_pfc_ack('{CNT{'0}}), + + /* + * Pause interface + */ + .tx_lfc_pause_en('{CNT{1'b0}}), + .tx_pause_req('{CNT{1'b0}}), + .tx_pause_ack(), + + /* + * Statistics + */ + .stat_clk(clk_125mhz), + .stat_rst(rst_125mhz), + .m_axis_stat(axis_eth_stat[n]), + + /* + * Status + */ + .tx_start_packet(), + .stat_tx_byte(), + .stat_tx_pkt_len(), + .stat_tx_pkt_ucast(), + .stat_tx_pkt_mcast(), + .stat_tx_pkt_bcast(), + .stat_tx_pkt_vlan(), + .stat_tx_pkt_good(), + .stat_tx_pkt_bad(), + .stat_tx_err_oversize(), + .stat_tx_err_user(), + .stat_tx_err_underflow(), + .rx_start_packet(), + .rx_error_count(), + .rx_block_lock(), + .rx_high_ber(), + .rx_status(eth_gty_rx_status[n*CNT +: CNT]), + .stat_rx_byte(), + .stat_rx_pkt_len(), + .stat_rx_pkt_fragment(), + .stat_rx_pkt_jabber(), + .stat_rx_pkt_ucast(), + .stat_rx_pkt_mcast(), + .stat_rx_pkt_bcast(), + .stat_rx_pkt_vlan(), + .stat_rx_pkt_good(), + .stat_rx_pkt_bad(), + .stat_rx_err_oversize(), + .stat_rx_err_bad_fcs(), + .stat_rx_err_bad_block(), + .stat_rx_err_framing(), + .stat_rx_err_preamble(), + .stat_rx_fifo_drop('{CNT{1'b0}}), + .stat_tx_mcf(), + .stat_rx_mcf(), + .stat_tx_lfc_pkt(), + .stat_tx_lfc_xon(), + .stat_tx_lfc_xoff(), + .stat_tx_lfc_paused(), + .stat_tx_pfc_pkt(), + .stat_tx_pfc_xon(), + .stat_tx_pfc_xoff(), + .stat_tx_pfc_paused(), + .stat_rx_lfc_pkt(), + .stat_rx_lfc_xon(), + .stat_rx_lfc_xoff(), + .stat_rx_lfc_paused(), + .stat_rx_pfc_pkt(), + .stat_rx_pfc_xon(), + .stat_rx_pfc_xoff(), + .stat_rx_pfc_paused(), + + /* + * Configuration + */ + .cfg_tx_max_pkt_len('{CNT{16'd9218}}), + .cfg_tx_ifg('{CNT{8'd12}}), + .cfg_tx_enable('{CNT{1'b1}}), + .cfg_rx_max_pkt_len('{CNT{16'd9218}}), + .cfg_rx_enable('{CNT{1'b1}}), + .cfg_tx_prbs31_enable('{CNT{1'b0}}), + .cfg_rx_prbs31_enable('{CNT{1'b0}}), + .cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}), + .cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}), + .cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}), + .cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}), + .cfg_mcf_rx_eth_src('{CNT{48'd0}}), + .cfg_mcf_rx_check_eth_src('{CNT{1'b0}}), + .cfg_mcf_rx_eth_type('{CNT{16'h8808}}), + .cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}), + .cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}), + .cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}), + .cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}), + .cfg_mcf_rx_forward('{CNT{1'b0}}), + .cfg_mcf_rx_enable('{CNT{1'b0}}), + .cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}), + .cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}), + .cfg_tx_lfc_eth_type('{CNT{16'h8808}}), + .cfg_tx_lfc_opcode('{CNT{16'h0001}}), + .cfg_tx_lfc_en('{CNT{1'b0}}), + .cfg_tx_lfc_quanta('{CNT{16'hffff}}), + .cfg_tx_lfc_refresh('{CNT{16'h7fff}}), + .cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}), + .cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}), + .cfg_tx_pfc_eth_type('{CNT{16'h8808}}), + .cfg_tx_pfc_opcode('{CNT{16'h0101}}), + .cfg_tx_pfc_en('{CNT{1'b0}}), + .cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}), + .cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}), + .cfg_rx_lfc_opcode('{CNT{16'h0001}}), + .cfg_rx_lfc_en('{CNT{1'b0}}), + .cfg_rx_pfc_opcode('{CNT{16'h0101}}), + .cfg_rx_pfc_en('{CNT{1'b0}}) + ); + +end + +cndm_micro_pcie_us #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // Structural configuration + .PORTS(GTY_CNT), + + // PTP configuration + .PTP_TS_EN(PTP_TS_EN), + .PTP_TS_FMT_TOD(1'b0), + .PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM), + .PTP_CLK_PER_NS_DENOM(PTP_CLK_PER_NS_DENOM), + + // PCIe interface configuration + .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W), + .AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W) +) +cndm_inst ( + /* + * PCIe + */ + .pcie_clk(pcie_clk), + .pcie_rst(pcie_rst), + .s_axis_pcie_cq(s_axis_pcie_cq), + .m_axis_pcie_cc(m_axis_pcie_cc), + .m_axis_pcie_rq(m_axis_pcie_rq), + .s_axis_pcie_rc(s_axis_pcie_rc), + + .pcie_rq_seq_num0(pcie_rq_seq_num0), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), + .pcie_rq_seq_num1(pcie_rq_seq_num1), + .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + /* + * PTP + */ + .ptp_clk(ptp_clk), + .ptp_rst(ptp_rst), + .ptp_sample_clk(ptp_sample_clk), + .ptp_td_sdo(ptp_td_sd), + .ptp_pps(ptp_pps), + .ptp_pps_str(ptp_pps_str), + .ptp_sync_locked(), + .ptp_sync_ts_rel(), + .ptp_sync_ts_rel_step(), + .ptp_sync_ts_tod(), + .ptp_sync_ts_tod_step(), + .ptp_sync_pps(), + .ptp_sync_pps_str(), + + /* + * Ethernet + */ + .mac_tx_clk(eth_gty_tx_clk), + .mac_tx_rst(eth_gty_tx_rst), + .mac_axis_tx(eth_gty_axis_tx), + .mac_axis_tx_cpl(eth_gty_axis_tx_cpl), + + .mac_rx_clk(eth_gty_rx_clk), + .mac_rx_rst(eth_gty_rx_rst), + .mac_axis_rx(eth_gty_axis_rx) +); + +endmodule + +`resetall diff --git a/src/cndm/board/Alveo/fpga/tb/fpga_core/Makefile b/src/cndm/board/Alveo/fpga/tb/fpga_core/Makefile new file mode 100644 index 0000000..15638e3 --- /dev/null +++ b/src/cndm/board/Alveo/fpga/tb/fpga_core/Makefile @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2020-2026 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = fpga_core +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vpd_qspi.f + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_SIM := "1'b1" +export PARAM_VENDOR := "\"XILINX\"" +export PARAM_FAMILY := "\"virtexuplus\"" + +export PARAM_SW_CNT := 4 +export PARAM_LED_CNT := 3 +export PARAM_UART_CNT := 1 +export PARAM_PORT_CNT := 2 +export PARAM_PORT_LED_CNT := $(PARAM_PORT_CNT) +export PARAM_GTY_QUAD_CNT := $(PARAM_PORT_CNT) +export PARAM_GTY_CNT := $(shell echo $$(( 4 * $(PARAM_GTY_QUAD_CNT) ))) +export PARAM_GTY_CLK_CNT := $(PARAM_GTY_QUAD_CNT) + +# PTP configuration +export PARAM_PTP_TS_EN := 1 +export PARAM_PTP_CLK_PER_NS_NUM := 32 +export PARAM_PTP_CLK_PER_NS_DENOM := 5 + +# AXI lite interface configuration (control) +export PARAM_AXIL_CTRL_DATA_W := 32 +export PARAM_AXIL_CTRL_ADDR_W := 24 + +# MAC configuration +export PARAM_CFG_LOW_LATENCY := 1 +export PARAM_COMBINED_MAC_PCS := 1 +export PARAM_MAC_DATA_W := "64" + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/cndm/board/Alveo/fpga/tb/fpga_core/baser.py b/src/cndm/board/Alveo/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/cndm/board/Alveo/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/src/cndm/board/Alveo/fpga/tb/fpga_core/cndm.py b/src/cndm/board/Alveo/fpga/tb/fpga_core/cndm.py new file mode 120000 index 0000000..c693df0 --- /dev/null +++ b/src/cndm/board/Alveo/fpga/tb/fpga_core/cndm.py @@ -0,0 +1 @@ +../../lib/taxi/src/cndm/tb/cndm.py \ No newline at end of file diff --git a/src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.py b/src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.py new file mode 100644 index 0000000..93bd8ad --- /dev/null +++ b/src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,547 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: MIT +""" + +Copyright (c) 2020-2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import logging +import os +import sys + +import pytest +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, FallingEdge, Timer + +from cocotbext.axi import AxiStreamBus +from cocotbext.eth import XgmiiFrame +from cocotbext.uart import UartSource, UartSink +from cocotbext.pcie.core import RootComplex +from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice + +try: + from baser import BaseRSerdesSource, BaseRSerdesSink + import cndm +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + from baser import BaseRSerdesSource, BaseRSerdesSink + import cndm + finally: + del sys.path[0] + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + # Clocks + cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start()) + + # PCIe + self.rc = RootComplex() + + self.rc.max_payload_size = 0x1 # 256 bytes + self.rc.max_read_request_size = 0x2 # 512 bytes + + self.dev = UltraScalePlusPcieDevice( + # configuration options + pcie_generation=3, + pcie_link_width=16, + user_clk_frequency=250e6, + alignment="dword", + cq_straddle=False, + cc_straddle=False, + rq_straddle=False, + rc_straddle=False, + rc_4tlp_straddle=False, + pf_count=1, + max_payload_size=1024, + enable_client_tag=True, + enable_extended_tag=True, + enable_parity=False, + enable_rx_msg_interface=False, + enable_sriov=False, + enable_extended_configuration=False, + + pf0_msi_enable=True, + pf0_msi_count=32, + pf1_msi_enable=False, + pf1_msi_count=1, + pf2_msi_enable=False, + pf2_msi_count=1, + pf3_msi_enable=False, + pf3_msi_count=1, + pf0_msix_enable=False, + pf0_msix_table_size=31, + pf0_msix_table_bir=4, + pf0_msix_table_offset=0x00000000, + pf0_msix_pba_bir=4, + pf0_msix_pba_offset=0x00008000, + pf1_msix_enable=False, + pf1_msix_table_size=0, + pf1_msix_table_bir=0, + pf1_msix_table_offset=0x00000000, + pf1_msix_pba_bir=0, + pf1_msix_pba_offset=0x00000000, + pf2_msix_enable=False, + pf2_msix_table_size=0, + pf2_msix_table_bir=0, + pf2_msix_table_offset=0x00000000, + pf2_msix_pba_bir=0, + pf2_msix_pba_offset=0x00000000, + pf3_msix_enable=False, + pf3_msix_table_size=0, + pf3_msix_table_bir=0, + pf3_msix_table_offset=0x00000000, + pf3_msix_pba_bir=0, + pf3_msix_pba_offset=0x00000000, + + # signals + # Clock and Reset Interface + user_clk=dut.pcie_clk, + user_reset=dut.pcie_rst, + # user_lnk_up + # sys_clk + # sys_clk_gt + # sys_reset + # phy_rdy_out + + # Requester reQuest Interface + rq_bus=AxiStreamBus.from_entity(dut.m_axis_pcie_rq), + pcie_rq_seq_num0=dut.pcie_rq_seq_num0, + pcie_rq_seq_num_vld0=dut.pcie_rq_seq_num_vld0, + pcie_rq_seq_num1=dut.pcie_rq_seq_num1, + pcie_rq_seq_num_vld1=dut.pcie_rq_seq_num_vld1, + # pcie_rq_tag0 + # pcie_rq_tag1 + # pcie_rq_tag_av + # pcie_rq_tag_vld0 + # pcie_rq_tag_vld1 + + # Requester Completion Interface + rc_bus=AxiStreamBus.from_entity(dut.s_axis_pcie_rc), + + # Completer reQuest Interface + cq_bus=AxiStreamBus.from_entity(dut.s_axis_pcie_cq), + # pcie_cq_np_req + # pcie_cq_np_req_count + + # Completer Completion Interface + cc_bus=AxiStreamBus.from_entity(dut.m_axis_pcie_cc), + + # Transmit Flow Control Interface + # pcie_tfc_nph_av=dut.pcie_tfc_nph_av, + # pcie_tfc_npd_av=dut.pcie_tfc_npd_av, + + # Configuration Management Interface + cfg_mgmt_addr=dut.cfg_mgmt_addr, + cfg_mgmt_function_number=dut.cfg_mgmt_function_number, + cfg_mgmt_write=dut.cfg_mgmt_write, + cfg_mgmt_write_data=dut.cfg_mgmt_write_data, + cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable, + cfg_mgmt_read=dut.cfg_mgmt_read, + cfg_mgmt_read_data=dut.cfg_mgmt_read_data, + cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done, + # cfg_mgmt_debug_access + + # Configuration Status Interface + # cfg_phy_link_down + # cfg_phy_link_status + # cfg_negotiated_width + # cfg_current_speed + # cfg_max_payload=dut.cfg_max_payload, + # cfg_max_read_req=dut.cfg_max_read_req, + # cfg_function_status + # cfg_vf_status + # cfg_function_power_state + # cfg_vf_power_state + # cfg_link_power_state + # cfg_err_cor_out + # cfg_err_nonfatal_out + # cfg_err_fatal_out + # cfg_local_error_out + # cfg_local_error_valid + # cfg_rx_pm_state + # cfg_tx_pm_state + # cfg_ltssm_state + # cfg_rcb_status=dut.cfg_rcb_status, + # cfg_obff_enable + # cfg_pl_status_change + # cfg_tph_requester_enable + # cfg_tph_st_mode + # cfg_vf_tph_requester_enable + # cfg_vf_tph_st_mode + + # Configuration Received Message Interface + # cfg_msg_received + # cfg_msg_received_data + # cfg_msg_received_type + + # Configuration Transmit Message Interface + # cfg_msg_transmit + # cfg_msg_transmit_type + # cfg_msg_transmit_data + # cfg_msg_transmit_done + + # Configuration Flow Control Interface + cfg_fc_ph=dut.cfg_fc_ph, + cfg_fc_pd=dut.cfg_fc_pd, + cfg_fc_nph=dut.cfg_fc_nph, + cfg_fc_npd=dut.cfg_fc_npd, + cfg_fc_cplh=dut.cfg_fc_cplh, + cfg_fc_cpld=dut.cfg_fc_cpld, + cfg_fc_sel=dut.cfg_fc_sel, + + # Configuration Control Interface + # cfg_hot_reset_in + # cfg_hot_reset_out + # cfg_config_space_enable + # cfg_dsn + # cfg_bus_number + # cfg_ds_port_number + # cfg_ds_bus_number + # cfg_ds_device_number + # cfg_ds_function_number + # cfg_power_state_change_ack + # cfg_power_state_change_interrupt + # cfg_err_cor_in=dut.status_error_cor, + # cfg_err_uncor_in=dut.status_error_uncor, + # cfg_flr_in_process + # cfg_flr_done + # cfg_vf_flr_in_process + # cfg_vf_flr_func_num + # cfg_vf_flr_done + # cfg_pm_aspm_l1_entry_reject + # cfg_pm_aspm_tx_l0s_entry_disable + # cfg_req_pm_transition_l23_ready + # cfg_link_training_enable + + # Configuration Interrupt Controller Interface + # cfg_interrupt_int + # cfg_interrupt_sent + # cfg_interrupt_pending + cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable, + cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable, + cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update, + cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data, + cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select, + cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int, + cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status, + cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable, + cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num, + cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent, + cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail, + # cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable, + # cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask, + # cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable, + # cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask, + # cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address, + # cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data, + # cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int, + # cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending, + # cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status, + # cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent, + # cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail, + cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr, + cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present, + cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type, + cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag, + cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number, + + # Configuration Extend Interface + # cfg_ext_read_received + # cfg_ext_write_received + # cfg_ext_register_number + # cfg_ext_function_number + # cfg_ext_write_data + # cfg_ext_write_byte_enable + # cfg_ext_read_data + # cfg_ext_read_data_valid + ) + + # self.dev.log.setLevel(logging.DEBUG) + + self.rc.make_port().connect(self.dev) + + self.dev.functions[0].configure_bar(0, 2**int(dut.uut.cndm_inst.axil_ctrl_bar.ADDR_W)) + + # UART + self.uart_sources = [] + self.uart_sinks = [] + + for sig in dut.uart_rxd: + self.uart_sources.append(UartSource(sig, baud=3000000, bits=8, stop_bits=1)) + for sig in dut.uart_txd: + self.uart_sinks.append(UartSink(sig, baud=3000000, bits=8, stop_bits=1)) + + # Ethernet + for clk in dut.eth_gty_mgt_refclk_p: + cocotb.start_soon(Clock(clk, 6.4, units="ns").start()) + + self.qsfp_sources = [] + self.qsfp_sinks = [] + + for inst in dut.uut.gty_quad: + for ch in inst.mac_inst.ch: + gt_inst = ch.ch_inst.gt.gt_inst + + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) + else: + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None + + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) + + dut.sw.setimmediatevalue(0) + dut.eth_port_modprsl.setimmediatevalue(0) + dut.eth_port_intl.setimmediatevalue(0) + + self.loopback_enable = False + cocotb.start_soon(self._run_loopback()) + + async def init(self): + + self.dut.rst_125mhz.setimmediatevalue(0) + + await FallingEdge(self.dut.pcie_rst) + await Timer(100, 'ns') + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + self.dut.rst_125mhz.value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + self.dut.rst_125mhz.value = 0 + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + await self.rc.enumerate() + + async def _run_loopback(self): + while True: + await RisingEdge(self.dut.pcie_clk) + + if self.loopback_enable: + for src, snk in zip(self.qsfp_sources, self.qsfp_sinks): + while not snk.empty(): + await src.send(await snk.recv()) + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("Init driver model") + driver = cndm.Driver() + await driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id)) + + tb.log.info("Init complete") + + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + + for snk in tb.qsfp_sinks: + snk.clear() + + tb.log.info("Send and receive single packet on each port") + + for k in range(len(driver.ports)): + data = f"Corundum rocks on port {k}!".encode('ascii') + + await driver.ports[k].start_xmit(data) + + pkt = await tb.qsfp_sinks[k].recv() + tb.log.info("Got TX packet: %s", pkt) + + assert pkt.get_payload() == data.ljust(60, b'\x00') + assert pkt.check_fcs() + + await tb.qsfp_sources[k].send(pkt) + + pkt = await driver.ports[k].recv() + tb.log.info("Got RX packet: %s", pkt) + + assert bytes(pkt) == data.ljust(60, b'\x00') + + tb.log.info("Multiple small packets") + + count = 64 + pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await driver.ports[0].start_xmit(p) + + for k in range(count): + pkt = await driver.ports[0].recv() + + tb.log.info("Got RX packet: %s", pkt) + + assert bytes(pkt) == pkts[k].ljust(60, b'\x00') + + tb.loopback_enable = False + + tb.log.info("Multiple large packets") + + count = 64 + pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] + + tb.loopback_enable = True + + for p in pkts: + await driver.ports[0].start_xmit(p) + + for k in range(count): + pkt = await driver.ports[0].recv() + + tb.log.info("Got RX packet: %s", pkt) + + assert bytes(pkt) == pkts[k].ljust(60, b'\x00') + + tb.loopback_enable = False + + await RisingEdge(dut.clk_125mhz) + await RisingEdge(dut.clk_125mhz) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize("mac_data_w", [32, 64]) +def test_fpga_core(request, mac_data_w): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(taxi_src_dir, "cndm", "rtl", "cndm_micro_pcie_us.f"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_apb.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), + os.path.join(taxi_src_dir, "pyrite", "rtl", "pyrite_pcie_us_vpd_qspi.f"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['SIM'] = "1'b1" + parameters['VENDOR'] = "\"XILINX\"" + parameters['FAMILY'] = "\"virtexuplus\"" + + parameters['SW_CNT'] = 4 + parameters['LED_CNT'] = 3 + parameters['UART_CNT'] = 1 + parameters['PORT_CNT'] = 2 + parameters['PORT_LED_CNT'] = parameters['PORT_CNT'] + parameters['GTY_QUAD_CNT'] = parameters['PORT_CNT'] + parameters['GTY_CNT'] = parameters['GTY_QUAD_CNT']*4 + parameters['GTY_CLK_CNT'] = parameters['GTY_QUAD_CNT'] + + # PTP configuration + parameters['PTP_TS_EN'] = 1 + parameters['PTP_CLK_PER_NS_NUM'] = 32 + parameters['PTP_CLK_PER_NS_DENOM'] = 5 + + # AXI lite interface configuration (control) + parameters['AXIL_CTRL_DATA_W'] = 32 + parameters['AXIL_CTRL_ADDR_W'] = 24 + + # MAC configuration + parameters['CFG_LOW_LATENCY'] = 1 + parameters['COMBINED_MAC_PCS'] = 1 + parameters['MAC_DATA_W'] = mac_data_w + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.sv b/src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.sv new file mode 100644 index 0000000..6b25fda --- /dev/null +++ b/src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.sv @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2026 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic testbench + */ +module test_fpga_core # +( + /* verilator lint_off WIDTHTRUNC */ + parameter logic SIM = 1'b0, + parameter string VENDOR = "XILINX", + parameter string FAMILY = "virtexuplus", + + // Board configuration + parameter SW_CNT = 4, + parameter LED_CNT = 3, + parameter UART_CNT = 1, + parameter PORT_CNT = 2, + parameter PORT_LED_CNT = PORT_CNT, + parameter GTY_QUAD_CNT = PORT_CNT, + parameter GTY_CNT = GTY_QUAD_CNT*4, + parameter GTY_CLK_CNT = GTY_QUAD_CNT, + + // FW ID + parameter FPGA_ID = 32'h4B37093, + parameter FW_ID = 32'h0000C001, + parameter FW_VER = 32'h000_01_000, + parameter BOARD_ID = 32'h10ee_90c8, + parameter BOARD_VER = 32'h001_00_000, + parameter BUILD_DATE = 32'd602976000, + parameter GIT_HASH = 32'h5f87c2e8, + parameter RELEASE_INFO = 32'h00000000, + + // PTP configuration + parameter logic PTP_TS_EN = 1'b1, + parameter PTP_CLK_PER_NS_NUM = 32, + parameter PTP_CLK_PER_NS_DENOM = 5, + + // PCIe interface configuration + parameter AXIS_PCIE_DATA_W = 512, + parameter AXIS_PCIE_RC_USER_W = AXIS_PCIE_DATA_W < 512 ? 75 : 161, + parameter AXIS_PCIE_RQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 62 : 137, + parameter AXIS_PCIE_CQ_USER_W = AXIS_PCIE_DATA_W < 512 ? 85 : 183, + parameter AXIS_PCIE_CC_USER_W = AXIS_PCIE_DATA_W < 512 ? 33 : 81, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_W = 32, + parameter AXIL_CTRL_ADDR_W = 24, + + // MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = 64 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32); +localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6; + +logic clk_125mhz; +logic rst_125mhz; + +logic [SW_CNT-1:0] sw; +logic [LED_CNT-1:0] led; +logic [PORT_LED_CNT-1:0] port_led_act; +logic [PORT_LED_CNT-1:0] port_led_stat_r; +logic [PORT_LED_CNT-1:0] port_led_stat_g; +logic [PORT_LED_CNT-1:0] port_led_stat_b; +logic [PORT_LED_CNT-1:0] port_led_stat_y; + +logic uart_txd[UART_CNT-1:0]; +logic uart_rxd[UART_CNT-1:0]; + +logic eth_gty_mgt_refclk_p[GTY_CLK_CNT]; +logic eth_gty_mgt_refclk_n[GTY_CLK_CNT]; +logic eth_gty_mgt_refclk_out[GTY_CLK_CNT]; + +logic [PORT_CNT-1:0] eth_port_modsell; +logic [PORT_CNT-1:0] eth_port_resetl; +logic [PORT_CNT-1:0] eth_port_modprsl; +logic [PORT_CNT-1:0] eth_port_intl; +logic [PORT_CNT-1:0] eth_port_lpmode; + +logic pcie_clk; +logic pcie_rst; + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_CQ_USER_W) +) s_axis_pcie_cq(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_CC_USER_W) +) m_axis_pcie_cc(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_RQ_USER_W) +) m_axis_pcie_rq(); + +taxi_axis_if #( + .DATA_W(AXIS_PCIE_DATA_W), + .KEEP_EN(1), + .KEEP_W(AXIS_PCIE_KEEP_W), + .USER_EN(1), + .USER_W(AXIS_PCIE_RC_USER_W) +) s_axis_pcie_rc(); + +logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num0; +logic pcie_rq_seq_num_vld0; +logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num1; +logic pcie_rq_seq_num_vld1; + +logic [2:0] cfg_max_payload; +logic [2:0] cfg_max_read_req; +logic [3:0] cfg_rcb_status; + +logic [9:0] cfg_mgmt_addr; +logic [7:0] cfg_mgmt_function_number; +logic cfg_mgmt_write; +logic [31:0] cfg_mgmt_write_data; +logic [3:0] cfg_mgmt_byte_enable; +logic cfg_mgmt_read; +logic [31:0] cfg_mgmt_read_data; +logic cfg_mgmt_read_write_done; + +logic [7:0] cfg_fc_ph; +logic [11:0] cfg_fc_pd; +logic [7:0] cfg_fc_nph; +logic [11:0] cfg_fc_npd; +logic [7:0] cfg_fc_cplh; +logic [11:0] cfg_fc_cpld; +logic [2:0] cfg_fc_sel; + +logic cfg_ext_read_received; +logic cfg_ext_write_received; +logic [9:0] cfg_ext_register_number; +logic [7:0] cfg_ext_function_number; +logic [31:0] cfg_ext_write_data; +logic [3:0] cfg_ext_write_byte_enable; +logic [31:0] cfg_ext_read_data; +logic cfg_ext_read_data_valid; + +logic [3:0] cfg_interrupt_msi_enable; +logic [11:0] cfg_interrupt_msi_mmenable; +logic cfg_interrupt_msi_mask_update; +logic [31:0] cfg_interrupt_msi_data; +logic [1:0] cfg_interrupt_msi_select; +logic [31:0] cfg_interrupt_msi_int; +logic [31:0] cfg_interrupt_msi_pending_status; +logic cfg_interrupt_msi_pending_status_data_enable; +logic [1:0] cfg_interrupt_msi_pending_status_function_num; +logic cfg_interrupt_msi_sent; +logic cfg_interrupt_msi_fail; +logic [2:0] cfg_interrupt_msi_attr; +logic cfg_interrupt_msi_tph_present; +logic [1:0] cfg_interrupt_msi_tph_type; +logic [7:0] cfg_interrupt_msi_tph_st_tag; +logic [7:0] cfg_interrupt_msi_function_number; + +logic fpga_boot; +logic qspi_clk; +logic [3:0] qspi_dq_i; +logic [3:0] qspi_dq_o; +logic [3:0] qspi_dq_oe; +logic qspi_cs; + +fpga_core #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + + // FW ID + .FPGA_ID(FPGA_ID), + .FW_ID(FW_ID), + .FW_VER(FW_VER), + .BOARD_ID(BOARD_ID), + .BOARD_VER(BOARD_VER), + .BUILD_DATE(BUILD_DATE), + .GIT_HASH(GIT_HASH), + .RELEASE_INFO(RELEASE_INFO), + + // PTP configuration + .PTP_TS_EN(PTP_TS_EN), + .PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM), + .PTP_CLK_PER_NS_DENOM(PTP_CLK_PER_NS_DENOM), + + // PCIe interface configuration + .RQ_SEQ_NUM_W(RQ_SEQ_NUM_W), + + // AXI lite interface configuration (control) + .AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W), + .AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W), + + // MAC configuration + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) +) +uut ( + /* + * Clock: 125MHz + * Synchronous reset + */ + .clk_125mhz(clk_125mhz), + .rst_125mhz(rst_125mhz), + + /* + * GPIO + */ + .sw(sw), + .led(led), + .port_led_act(port_led_act), + .port_led_stat_r(port_led_stat_r), + .port_led_stat_g(port_led_stat_g), + .port_led_stat_b(port_led_stat_b), + .port_led_stat_y(port_led_stat_y), + + /* + * UART + */ + .uart_txd(uart_txd), + .uart_rxd(uart_rxd), + + /* + * Ethernet + */ + .eth_gty_tx_p(), + .eth_gty_tx_n(), + .eth_gty_rx_p('{GTY_CNT{1'b0}}), + .eth_gty_rx_n('{GTY_CNT{1'b0}}), + .eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p), + .eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n), + .eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out), + + .eth_port_modsell(eth_port_modsell), + .eth_port_resetl(eth_port_resetl), + .eth_port_modprsl(eth_port_modprsl), + .eth_port_intl(eth_port_intl), + .eth_port_lpmode(eth_port_lpmode), + + /* + * PCIe + */ + .pcie_clk(pcie_clk), + .pcie_rst(pcie_rst), + .s_axis_pcie_cq(s_axis_pcie_cq), + .m_axis_pcie_cc(m_axis_pcie_cc), + .m_axis_pcie_rq(m_axis_pcie_rq), + .s_axis_pcie_rc(s_axis_pcie_rc), + + .pcie_rq_seq_num0(pcie_rq_seq_num0), + .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0), + .pcie_rq_seq_num1(pcie_rq_seq_num1), + .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1), + + .cfg_max_payload(cfg_max_payload), + .cfg_max_read_req(cfg_max_read_req), + .cfg_rcb_status(cfg_rcb_status), + + .cfg_mgmt_addr(cfg_mgmt_addr), + .cfg_mgmt_function_number(cfg_mgmt_function_number), + .cfg_mgmt_write(cfg_mgmt_write), + .cfg_mgmt_write_data(cfg_mgmt_write_data), + .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable), + .cfg_mgmt_read(cfg_mgmt_read), + .cfg_mgmt_read_data(cfg_mgmt_read_data), + .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done), + + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + + .cfg_ext_read_received(cfg_ext_read_received), + .cfg_ext_write_received(cfg_ext_write_received), + .cfg_ext_register_number(cfg_ext_register_number), + .cfg_ext_function_number(cfg_ext_function_number), + .cfg_ext_write_data(cfg_ext_write_data), + .cfg_ext_write_byte_enable(cfg_ext_write_byte_enable), + .cfg_ext_read_data(cfg_ext_read_data), + .cfg_ext_read_data_valid(cfg_ext_read_data_valid), + + .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable), + .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable), + .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update), + .cfg_interrupt_msi_data(cfg_interrupt_msi_data), + .cfg_interrupt_msi_select(cfg_interrupt_msi_select), + .cfg_interrupt_msi_int(cfg_interrupt_msi_int), + .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status), + .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable), + .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num), + .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent), + .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail), + .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr), + .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present), + .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type), + .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag), + .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number), + + /* + * QSPI flash + */ + .fpga_boot(fpga_boot), + .qspi_clk(qspi_clk), + .qspi_dq_i(qspi_dq_i), + .qspi_dq_o(qspi_dq_o), + .qspi_dq_oe(qspi_dq_oe), + .qspi_cs(qspi_cs) +); + +endmodule + +`resetall