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cndm: Initial commit of corundum-micro
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
369
src/cndm/rtl/cndm_micro_core.sv
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369
src/cndm/rtl/cndm_micro_core.sv
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@@ -0,0 +1,369 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Corundum-micro core logic
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*/
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module cndm_micro_core #(
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parameter PORTS = 2//,
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// parameter logic PTP_TS_EN = 1'b1,
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// parameter PTP_CLK_PER_NS_NUM = 512,
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// parameter PTP_CLK_PER_NS_DENOM = 165
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* Control register interface
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*/
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taxi_axil_if.wr_slv s_axil_wr,
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taxi_axil_if.rd_slv s_axil_rd,
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/*
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* DMA
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*/
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taxi_dma_desc_if.req_src dma_rd_desc_req,
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taxi_dma_desc_if.sts_snk dma_rd_desc_sts,
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taxi_dma_desc_if.req_src dma_wr_desc_req,
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taxi_dma_desc_if.sts_snk dma_wr_desc_sts,
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taxi_dma_ram_if.wr_slv dma_ram_wr,
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taxi_dma_ram_if.rd_slv dma_ram_rd,
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output wire logic [PORTS-1:0] irq,
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/*
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* PTP
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*/
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// input wire logic ptp_clk = 1'b0,
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// input wire logic ptp_rst = 1'b0,
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// input wire logic ptp_sample_clk = 1'b0,
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// output wire logic ptp_td_sdo,
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// output wire logic ptp_pps,
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// output wire logic ptp_pps_str,
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// output wire logic ptp_sync_locked,
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// output wire logic [63:0] ptp_sync_ts_rel,
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// output wire logic ptp_sync_ts_rel_step,
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// output wire logic [95:0] ptp_sync_ts_tod,
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// output wire logic ptp_sync_ts_tod_step,
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// output wire logic ptp_sync_pps,
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// output wire logic ptp_sync_pps_str,
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/*
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* Ethernet
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*/
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input wire logic mac_tx_clk[PORTS],
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input wire logic mac_tx_rst[PORTS],
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taxi_axis_if.src mac_axis_tx[PORTS],
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taxi_axis_if.snk mac_axis_tx_cpl[PORTS],
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input wire logic mac_rx_clk[PORTS],
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input wire logic mac_rx_rst[PORTS],
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taxi_axis_if.snk mac_axis_rx[PORTS]
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);
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localparam CL_PORTS = $clog2(PORTS);
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localparam AXIL_ADDR_W = s_axil_wr.ADDR_W;
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localparam AXIL_DATA_W = s_axil_wr.DATA_W;
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localparam RAM_SEGS = dma_ram_wr.SEGS;
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localparam RAM_SEG_ADDR_W = dma_ram_wr.SEG_ADDR_W;
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localparam RAM_SEG_DATA_W = dma_ram_wr.SEG_DATA_W;
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localparam RAM_SEG_BE_W = dma_ram_wr.SEG_BE_W;
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localparam RAM_SEL_W = dma_ram_wr.SEL_W;
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localparam PORT_OFFSET = 1;
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// localparam PORT_OFFSET = PTP_TS_EN ? 2 : 1;
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taxi_axil_if #(
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.DATA_W(s_axil_wr.DATA_W),
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.ADDR_W(16),
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.STRB_W(s_axil_wr.STRB_W),
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.AWUSER_EN(s_axil_wr.AWUSER_EN),
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.AWUSER_W(s_axil_wr.AWUSER_W),
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.WUSER_EN(s_axil_wr.WUSER_EN),
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.WUSER_W(s_axil_wr.WUSER_W),
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.BUSER_EN(s_axil_wr.BUSER_EN),
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.BUSER_W(s_axil_wr.BUSER_W),
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.ARUSER_EN(s_axil_wr.ARUSER_EN),
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.ARUSER_W(s_axil_wr.ARUSER_W),
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.RUSER_EN(s_axil_wr.RUSER_EN),
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.RUSER_W(s_axil_wr.RUSER_W)
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)
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s_axil_ctrl[PORTS+PORT_OFFSET]();
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taxi_axil_interconnect_1s #(
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.M_COUNT($size(s_axil_ctrl)),
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.ADDR_W(s_axil_wr.ADDR_W),
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.M_REGIONS(1),
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.M_BASE_ADDR('0),
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.M_ADDR_W({$size(s_axil_ctrl){{1{32'd16}}}}),
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.M_SECURE({$size(s_axil_ctrl){1'b0}})
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)
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port_intercon_inst (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-lite slave interface
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*/
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.s_axil_wr(s_axil_wr),
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.s_axil_rd(s_axil_rd),
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/*
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* AXI4-lite master interfaces
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*/
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.m_axil_wr(s_axil_ctrl),
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.m_axil_rd(s_axil_ctrl)
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);
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logic s_axil_awready_reg = 1'b0;
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logic s_axil_wready_reg = 1'b0;
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logic s_axil_bvalid_reg = 1'b0;
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logic s_axil_arready_reg = 1'b0;
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logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = '0;
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logic s_axil_rvalid_reg = 1'b0;
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assign s_axil_ctrl[0].awready = s_axil_awready_reg;
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assign s_axil_ctrl[0].wready = s_axil_wready_reg;
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assign s_axil_ctrl[0].bresp = '0;
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assign s_axil_ctrl[0].buser = '0;
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assign s_axil_ctrl[0].bvalid = s_axil_bvalid_reg;
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assign s_axil_ctrl[0].arready = s_axil_arready_reg;
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assign s_axil_ctrl[0].rdata = s_axil_rdata_reg;
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assign s_axil_ctrl[0].rresp = '0;
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assign s_axil_ctrl[0].ruser = '0;
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assign s_axil_ctrl[0].rvalid = s_axil_rvalid_reg;
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always_ff @(posedge clk) begin
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s_axil_awready_reg <= 1'b0;
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s_axil_wready_reg <= 1'b0;
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s_axil_bvalid_reg <= s_axil_bvalid_reg && !s_axil_ctrl[0].bready;
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s_axil_arready_reg <= 1'b0;
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s_axil_rvalid_reg <= s_axil_rvalid_reg && !s_axil_ctrl[0].rready;
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if (s_axil_ctrl[0].awvalid && s_axil_ctrl[0].wvalid && !s_axil_bvalid_reg) begin
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s_axil_awready_reg <= 1'b1;
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s_axil_wready_reg <= 1'b1;
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s_axil_bvalid_reg <= 1'b1;
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case ({s_axil_ctrl[0].awaddr[15:2], 2'b00})
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// 16'h0100: begin
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// txq_en_reg <= s_axil_ctrl[0].wdata[0];
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// txq_size_reg <= s_axil_ctrl[0].wdata[19:16];
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// end
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// 16'h0104: txq_prod_reg <= s_axil_ctrl[0].wdata[15:0];
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// 16'h0108: txq_base_addr_reg[31:0] <= s_axil_ctrl[0].wdata;
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// 16'h010c: txq_base_addr_reg[63:32] <= s_axil_ctrl[0].wdata;
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default: begin end
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endcase
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end
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if (s_axil_ctrl[0].arvalid && !s_axil_rvalid_reg) begin
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s_axil_rdata_reg <= '0;
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s_axil_arready_reg <= 1'b1;
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s_axil_rvalid_reg <= 1'b1;
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case ({s_axil_ctrl[0].araddr[15:2], 2'b00})
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16'h0100: s_axil_rdata_reg <= PORTS; // port count
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16'h0104: s_axil_rdata_reg <= 32'h00010000; // port offset
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// 16'h0104: s_axil_rdata_reg <= PTP_TS_EN ? 32'h00020000 : 32'h00010000; // port offset
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16'h0108: s_axil_rdata_reg <= 32'h00010000; // port stride
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default: begin end
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endcase
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end
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if (rst) begin
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s_axil_awready_reg <= 1'b0;
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s_axil_wready_reg <= 1'b0;
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s_axil_bvalid_reg <= 1'b0;
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s_axil_arready_reg <= 1'b0;
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s_axil_rvalid_reg <= 1'b0;
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end
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end
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// if (PTP_TS_EN) begin : ptp
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// cndm_micro_ptp #(
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// .PTP_CLK_PER_NS_NUM(PTP_CLK_PER_NS_NUM),
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// .PTP_CLK_PER_NS_DENOM(PTP_CLK_PER_NS_DENOM)
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// )
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// ptp_inst (
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// .clk(clk),
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// .rst(rst),
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// /*
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// * Control register interface
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// */
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// .s_axil_wr(s_axil_ctrl[1]),
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// .s_axil_rd(s_axil_ctrl[1]),
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// /*
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// * PTP
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// */
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// .ptp_clk(ptp_clk),
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// .ptp_rst(ptp_rst),
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// .ptp_sample_clk(ptp_sample_clk),
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// .ptp_td_sdo(ptp_td_sdo),
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// .ptp_pps(ptp_pps),
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// .ptp_pps_str(ptp_pps_str),
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// .ptp_sync_locked(ptp_sync_locked),
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// .ptp_sync_ts_rel(ptp_sync_ts_rel),
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// .ptp_sync_ts_rel_step(ptp_sync_ts_rel_step),
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// .ptp_sync_ts_tod(ptp_sync_ts_tod),
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// .ptp_sync_ts_tod_step(ptp_sync_ts_tod_step),
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// .ptp_sync_pps(ptp_sync_pps),
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// .ptp_sync_pps_str(ptp_sync_pps_str)
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// );
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// end else begin : ptp
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// assign ptp_td_sdo = 1'b0;
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// assign ptp_pps = 1'b0;
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// assign ptp_pps_str = 1'b0;
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// end
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taxi_dma_desc_if #(
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.SRC_ADDR_W(dma_rd_desc_req.SRC_ADDR_W),
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.SRC_SEL_EN(dma_rd_desc_req.SRC_SEL_EN),
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.SRC_SEL_W(dma_rd_desc_req.SRC_SEL_W),
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.SRC_ASID_EN(dma_rd_desc_req.SRC_ASID_EN),
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.DST_ADDR_W(dma_rd_desc_req.DST_ADDR_W),
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.DST_SEL_EN(dma_rd_desc_req.DST_SEL_EN),
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.DST_SEL_W(dma_rd_desc_req.DST_SEL_W-CL_PORTS),
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.DST_ASID_EN(dma_rd_desc_req.DST_ASID_EN),
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.IMM_EN(dma_rd_desc_req.IMM_EN),
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.LEN_W(dma_rd_desc_req.LEN_W),
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.TAG_W(dma_rd_desc_req.TAG_W-CL_PORTS),
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.ID_EN(dma_rd_desc_req.ID_EN),
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.DEST_EN(dma_rd_desc_req.DEST_EN),
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.USER_EN(dma_rd_desc_req.USER_EN)
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) dma_rd_desc_int[PORTS]();
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taxi_dma_desc_if #(
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.SRC_ADDR_W(dma_wr_desc_req.SRC_ADDR_W),
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.SRC_SEL_EN(dma_wr_desc_req.SRC_SEL_EN),
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.SRC_SEL_W(dma_wr_desc_req.SRC_SEL_W-CL_PORTS),
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.SRC_ASID_EN(dma_wr_desc_req.SRC_ASID_EN),
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.DST_ADDR_W(dma_wr_desc_req.DST_ADDR_W),
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.DST_SEL_EN(dma_wr_desc_req.DST_SEL_EN),
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.DST_SEL_W(dma_wr_desc_req.DST_SEL_W),
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.DST_ASID_EN(dma_wr_desc_req.DST_ASID_EN),
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.IMM_EN(dma_wr_desc_req.IMM_EN),
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.IMM_W(dma_wr_desc_req.IMM_W),
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.LEN_W(dma_wr_desc_req.LEN_W),
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.TAG_W(dma_wr_desc_req.TAG_W-CL_PORTS),
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.ID_EN(dma_wr_desc_req.ID_EN),
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.DEST_EN(dma_wr_desc_req.DEST_EN),
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.USER_EN(dma_wr_desc_req.USER_EN)
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) dma_wr_desc_int[PORTS]();
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taxi_dma_ram_if #(
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.SEGS(RAM_SEGS),
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.SEG_ADDR_W(RAM_SEG_ADDR_W),
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.SEG_DATA_W(RAM_SEG_DATA_W),
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.SEG_BE_W(RAM_SEG_BE_W),
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.SEL_W(RAM_SEL_W-CL_PORTS)
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) dma_ram_int[PORTS]();
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taxi_dma_if_mux #(
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.PORTS(PORTS),
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.ARB_ROUND_ROBIN(1),
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.ARB_LSB_HIGH_PRIO(1)
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)
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dma_mux_inst (
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.clk(clk),
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.rst(rst),
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/*
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* DMA descriptors from clients
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*/
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.client_rd_req(dma_rd_desc_int),
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.client_rd_sts(dma_rd_desc_int),
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.client_wr_req(dma_wr_desc_int),
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.client_wr_sts(dma_wr_desc_int),
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/*
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* DMA descriptors to DMA engines
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*/
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.dma_rd_req(dma_rd_desc_req),
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.dma_rd_sts(dma_rd_desc_sts),
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.dma_wr_req(dma_wr_desc_req),
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.dma_wr_sts(dma_wr_desc_sts),
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/*
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* RAM interface (from DMA interface)
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*/
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.dma_ram_wr(dma_ram_wr),
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.dma_ram_rd(dma_ram_rd),
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/*
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* RAM interface (towards RAM)
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*/
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.client_ram_wr(dma_ram_int),
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.client_ram_rd(dma_ram_int)
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);
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for (genvar p = 0; p < PORTS; p = p + 1) begin : port
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cndm_micro_port #(
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// .PTP_TS_EN(PTP_TS_EN)
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)
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port_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Control register interface
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*/
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.s_axil_wr(s_axil_ctrl[PORT_OFFSET+p]),
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.s_axil_rd(s_axil_ctrl[PORT_OFFSET+p]),
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/*
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* DMA
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*/
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.dma_rd_desc_req(dma_rd_desc_int[p]),
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.dma_rd_desc_sts(dma_rd_desc_int[p]),
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.dma_wr_desc_req(dma_wr_desc_int[p]),
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.dma_wr_desc_sts(dma_wr_desc_int[p]),
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.dma_ram_wr(dma_ram_int[p]),
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.dma_ram_rd(dma_ram_int[p]),
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.irq(irq[p]),
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/*
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* Ethernet
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*/
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.mac_tx_clk(mac_tx_clk[p]),
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.mac_tx_rst(mac_tx_rst[p]),
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.mac_axis_tx(mac_axis_tx[p]),
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.mac_axis_tx_cpl(mac_axis_tx_cpl[p]),
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.mac_rx_clk(mac_rx_clk[p]),
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.mac_rx_rst(mac_rx_rst[p]),
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.mac_axis_rx(mac_axis_rx[p])
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);
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end
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endmodule
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`resetall
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