diff --git a/README.md b/README.md index cfd71ac..19d8383 100644 --- a/README.md +++ b/README.md @@ -130,6 +130,7 @@ Example designs are provided for several different FPGA boards, showcasing many * Cisco Nexus K3P-Q/ExaNIC X100 (Xilinx Kintex UltraScale+ XCKU3P) * Digilent Arty A7 (Xilinx Artix 7 XC7A35T) * HiTech Global HTG-940 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P) +* HiTech Global HTG-9200 (Xilinx Virtex UltraScale+ XCVU9P/XCVU13P) * Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P) * Xilinx Alveo U45N/SN1000 (Xilinx Virtex UltraScale+ XCU26) * Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50) diff --git a/src/eth/example/HTG9200/fpga/README.md b/src/eth/example/HTG9200/fpga/README.md new file mode 100644 index 0000000..0671294 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/README.md @@ -0,0 +1,67 @@ +# Taxi Example Design for HTG-9200 + +## Introduction + +This example design targets the HiTech Global HTG-9200 FPGA board. + +The design places looped-back MACs on the Ethernet ports, as well as XFCP on the USB UART for monitoring and control. + +* USB UART + * XFCP (921600 baud) +* QSFP28 + * Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers + +## Board details + +* FPGA: xcvu9p-flgb2104-2-e +* USB UART: Silicon Labs CP2103 +* 1000BASE-T PHY: TI DP83867IRPAP via RGMII + +## Licensing + +* Toolchain + * Vivado Enterprise (requires license) +* IP + * No licensed vendor IP or 3rd party IP + +## How to build + +Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. + +## Board configuration + +For correct operation, several DIP switches need to be set correctly. Additionally, some other component-level modifications may be required. + +DIP switch settings: + +* S2.1: off (enable EMCCLK, if needed to boot from flash) +* S3.2: off (enable U24 ref_clk) +* S4.5: off (enable U47 osc_gty2) +* S4.8: on (enable U48 outputs) + +Note that S4.8 has no effect if R441 is not installed (which appears to be the default configuration) as U48 has an internal pull-down on OEb. The PLL configuration in this design also ignores the IN_SEL pins, so S4.6 and S4.7 have no effect. The other DIP switches do not affect the operation of this design. + +When using optical modules or active optical cables, it is necessary to pull the lpmode pins low to enable the lasers. On the HTG-9200, the lpmode pins are not connected to the FPGA, so it is necessary to pull the pins low on the board. The board has footprints for pull-down resistors on the lpmode pins, which are not populated by default. These are R414, R392, R336, R316, R276, R475, R471, R473, and R477 (respectively for QSFP1-9). Shorting across these footprints or installing pull-down resistors of around 150 ohms will bring installed modules out of low power mode. + +The HTG-9200 was originally designed for Virtex UltraScale, so by default some of the power supply voltages are too high for an UltraScale+ device. In particular, the Avcc supplies for the GTY transceivers are set to 1.0 V, which is not only outside of the recommended range of 0.873-0.927 V but it also matches the absolute max of 1.0 V. Additionally, Vccint and Vccbram are set to 0.95V, which is outside of the recommended range of 0.825-0.876 V for standard speed grades but below the absolute max of 1.0 V. Checking the supply voltages and swapping out the feedback resistors on the Vccint, Vccbram and MGT Avcc power supplies is therefore highly recommended. Note that the supplies labeled GTH feed the MGT banks on the right side of the device, which are GTH transceivers on UltraScale and GTY transceivers on UltraScale+. + +The table below contains the power rail test points and feedback resistor values for the power supply rails in question for several different speed grades of Virtex UltraScale and UltraScale+ devices. + +| Rail | VCCINT | VCCBRAM | GTY_AVCC | GTH_AVCC | +| ----------- | ------------ | ------------ | ------------ | ------------ | +| Test point | P6 | P8 | P9 | P1 | +| Regulator | U4, U56 | U11 | U13 | U20 | +| Part | 4/2 LTM4650 | LTM4625 | 4/4 LTM4644 | 4/4 LTM4644 | +| Current | 100A | 5A | 16A | 16A | +| FB resistor | R354 | R494 | R38 | R61 | +| US -3, -1H | 90.9K (1.0V) | 90.9K (1.0V) | 22.6K (1.0V) | 22.6K (1.0V) | +| US -2, -1 | 105K (0.95V) | 105K (0.95V) | 22.6K (1.0V) | 22.6K (1.0V) | +| US+ -3 | 121K (0.90V) | 121K (0.90V) | 30.1K (0.9V) | 30.1K (0.9V) | +| US+ -2, -1 | 147K (0.85V) | 147K (0.85V) | 30.1K (0.9V) | 30.1K (0.9V) | +| US+ -2L | 301K (0.72V) | 147K (0.85V) | 30.1K (0.9V) | 30.1K (0.9V) | + +## How to test + +Run `make program` to program the board with Vivado. + +To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. diff --git a/src/eth/example/HTG9200/fpga/common/vivado.mk b/src/eth/example/HTG9200/fpga/common/vivado.mk new file mode 100644 index 0000000..07c56e2 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/common/vivado.mk @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: MIT +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016-2025 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - list of source files +# INC_FILES - list of include files +# XDC_FILES - list of timing constraint files +# XCI_FILES - list of IP XCI files +# IP_TCL_FILES - list of IP TCL files (sourced during project creation) +# CONFIG_TCL_FILES - list of config TCL files (sourced before each build) +# +# Note: both SYN_FILES and INC_FILES support file list files. File list +# files are files with a .f extension that contain a list of additional +# files to include, one path relative to the .f file location per line. +# The .f files are processed recursively, and then the complete file list +# is de-duplicated, with later files in the list taking precedence. +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include $(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) +XDC_FILES ?= $(PROJECT).xdc + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES))) +INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES))) + +################################################################### +# Main Targets +# +# all: build everything (fpga) +# fpga: build FPGA config +# vivado: open project in Vivado +# tmpclean: remove intermediate files +# clean: remove output files and project files +# distclean: remove archived output files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file + +# create fresh project if Makefile or IP files have changed +create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@ + for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +# source config TCL scripts if any source file has changed +update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# output files (including potentially bit, bin, ltx, and xsa) +$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \ + if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi diff --git a/src/eth/example/HTG9200/fpga/fpga.xdc b/src/eth/example/HTG9200/fpga/fpga.xdc new file mode 100644 index 0000000..9bd9e3f --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga.xdc @@ -0,0 +1,1089 @@ +# XDC constraints for the HiTech Global HTG-9200 board +# part: xcvu9p-flgb2104-2-e +# part: xcvu13p-fhgb2104-2-e + +# General configuration +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + +# System clocks +# DDR4 clocks from U5 (200 MHz) +#set_property -dict {LOC C36 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_p] +#set_property -dict {LOC C37 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_a_n] +#create_clock -period 5.000 -name sys_clk_ddr4_a [get_ports sys_clk_ddr4_a_p] + +#set_property -dict {LOC BA34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_b_p] +#set_property -dict {LOC BB34 IOSTANDARD DIFF_SSTL12} [get_ports sys_clk_ddr4_b_n] +#create_clock -period 5.000 -name sys_clk_ddr4_b [get_ports sys_clk_ddr4_b_p] + +# refclk from U24 (200 MHz) +set_property -dict {LOC AV26 IOSTANDARD LVDS} [get_ports ref_clk_p] +set_property -dict {LOC AW26 IOSTANDARD LVDS} [get_ports ref_clk_n] +create_clock -period 5.000 -name ref_clk [get_ports ref_clk_p] + +# 80 MHz EMCCLK +#set_property -dict {LOC AL27 IOSTANDARD LVCMOS18} [get_ports emc_clk] +#create_clock -period 12.5 -name emc_clk [get_ports emc_clk] + +# PLL control +set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_fdec}] +set_property -dict {LOC K25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_finc}] +set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_intr_n}] +set_property -dict {LOC L25 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_lol_n}] +set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_oe_n}] +set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_sync_n}] +set_property -dict {LOC K22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_rst_n}] + +#set_property -dict {LOC BE20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_sd_oe}] +#set_property -dict {LOC BD20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_out0_sel_i2cb}] + +set_false_path -to [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}] +set_output_delay 0 [get_ports {clk_gty2_fdec clk_gty2_finc clk_gty2_oe_n clk_gty2_sync_n clk_gty2_rst_n}] +set_false_path -from [get_ports {clk_gty2_intr_n clk_gty2_lol_n}] +set_input_delay 0 [get_ports {clk_gty2_intr_n clk_gty2_lol_n}] + +# LEDs +set_property -dict {LOC BA24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] +set_property -dict {LOC BB24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] +set_property -dict {LOC BC24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[2]}] +set_property -dict {LOC BD24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[3]}] +set_property -dict {LOC AP25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[4]}] +set_property -dict {LOC BD25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[5]}] +set_property -dict {LOC BC26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[6]}] +set_property -dict {LOC BC27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[7]}] + +set_false_path -to [get_ports {led[*]}] +set_output_delay 0 [get_ports {led[*]}] + +# Push buttons +set_property -dict {LOC B31 IOSTANDARD LVCMOS12} [get_ports {btn[0]}] +set_property -dict {LOC C31 IOSTANDARD LVCMOS12} [get_ports {btn[1]}] + +set_false_path -from [get_ports {btn[*]}] +set_input_delay 0 [get_ports {btn[*]}] + +# DIP switches +set_property -dict {LOC P33 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] +set_property -dict {LOC K34 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] +set_property -dict {LOC E35 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] +set_property -dict {LOC H38 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] +set_property -dict {LOC D35 IOSTANDARD LVCMOS12} [get_ports {sw[4]}] +set_property -dict {LOC D36 IOSTANDARD LVCMOS12} [get_ports {sw[5]}] +set_property -dict {LOC E37 IOSTANDARD LVCMOS12} [get_ports {sw[6]}] +set_property -dict {LOC F38 IOSTANDARD LVCMOS12} [get_ports {sw[7]}] + +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + +# GPIO +#set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports {gpio[0]}] +#set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {gpio[1]}] +#set_property -dict {LOC AU26 IOSTANDARD LVCMOS18} [get_ports {gpio[2]}] +#set_property -dict {LOC BD26 IOSTANDARD LVCMOS18} [get_ports {gpio[3]}] +#set_property -dict {LOC BE27 IOSTANDARD LVCMOS18} [get_ports {gpio[4]}] +#set_property -dict {LOC BE26 IOSTANDARD LVCMOS18} [get_ports {gpio[5]}] +#set_property -dict {LOC AU25 IOSTANDARD LVCMOS18} [get_ports {gpio[6]}] +#set_property -dict {LOC AR26 IOSTANDARD LVCMOS18} [get_ports {gpio[7]}] + +#set_false_path -to [get_ports {gpio[*]}] +#set_output_delay 0 [get_ports {gpio[*]}] + +# UART +set_property -dict {LOC BB27 IOSTANDARD LVCMOS18} [get_ports uart_txd] +set_property -dict {LOC AY27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rxd] +set_property -dict {LOC BC28 IOSTANDARD LVCMOS18} [get_ports uart_rts] +set_property -dict {LOC AY28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_cts] +set_property -dict {LOC AY26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rst_n] +set_property -dict {LOC BB26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_suspend_n] +#set_property -dict {LOC AW28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[0]}] +#set_property -dict {LOC AV28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[1]}] +#set_property -dict {LOC AV27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[2]}] +#set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_gpio[3]}] + +set_false_path -to [get_ports {uart_rxd uart_cts uart_rst_n uart_suspend_n}] +set_output_delay 0 [get_ports {uart_rxd uart_cts uart_rst_n uart_suspend_n}] +set_false_path -from [get_ports {uart_txd uart_rts}] +set_input_delay 0 [get_ports {uart_txd uart_rts}] + +# I2C +set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_scl] +set_property -dict {LOC BC21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_sda] +set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_main_rst_n] + +set_false_path -to [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}] +set_output_delay 0 [get_ports {i2c_main_sda i2c_main_scl i2c_main_rst_n}] +set_false_path -from [get_ports {i2c_main_sda i2c_main_scl}] +set_input_delay 0 [get_ports {i2c_main_sda i2c_main_scl}] + +# QSPI flash +#set_property -dict {LOC AM26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[0]}] +#set_property -dict {LOC AN26 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[1]}] +#set_property -dict {LOC AL25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[2]}] +#set_property -dict {LOC AM25 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_dq[3]}] +#set_property -dict {LOC BF27 IOSTANDARD LVCMOS18 DRIVE 8} [get_ports {qspi_1_cs_n}] + +#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}] +#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}] +#set_false_path -from [get_ports {qspi_1_dq}] +#set_input_delay 0 [get_ports {qspi_1_dq}] + +# DDR4 A +# set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[0]}] +# set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[1]}] +# set_property -dict {LOC D34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[2]}] +# set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[3]}] +# set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[4]}] +# set_property -dict {LOC D38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[5]}] +# set_property -dict {LOC A39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[6]}] +# set_property -dict {LOC C38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[7]}] +# set_property -dict {LOC B39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[8]}] +# set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[9]}] +# set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[10]}] +# set_property -dict {LOC D39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[11]}] +# set_property -dict {LOC C34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[12]}] +# set_property -dict {LOC A38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[13]}] +# set_property -dict {LOC A40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[14]}] +# set_property -dict {LOC E36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[15]}] +# set_property -dict {LOC E38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_a[16]}] + +# set_property -dict {LOC B34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_act_n}] +# set_property -dict {LOC A37 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_alert_n}] + +# set_property -dict {LOC C39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_ba[0]}] +# set_property -dict {LOC E39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_ba[1]}] +# set_property -dict {LOC B40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_bg[0]}] + +# set_property -dict {LOC D40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_cke}] +# set_property -dict {LOC A32 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_a_ck_t}] +# set_property -dict {LOC A33 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_a_ck_c}] +# set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_a_cs_n}] + +# set_property -dict {LOC N28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[0]}] +# set_property -dict {LOC N26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[1]}] +# set_property -dict {LOC R27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[2]}] +# set_property -dict {LOC P26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[3]}] +# set_property -dict {LOC P28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[4]}] +# set_property -dict {LOC R26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[5]}] +# set_property -dict {LOC T27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[6]}] +# set_property -dict {LOC T26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[7]}] +# set_property -dict {LOC H29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[8]}] +# set_property -dict {LOC G27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[9]}] +# set_property -dict {LOC D28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[10]}] +# set_property -dict {LOC F27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[11]}] +# set_property -dict {LOC G29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[12]}] +# set_property -dict {LOC G26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[13]}] +# set_property -dict {LOC E28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[14]}] +# set_property -dict {LOC E27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[15]}] +# set_property -dict {LOC H28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[16]}] +# set_property -dict {LOC L27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[17]}] +# set_property -dict {LOC J28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[18]}] +# set_property -dict {LOC H27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[19]}] +# set_property -dict {LOC J29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[20]}] +# set_property -dict {LOC M27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[21]}] +# set_property -dict {LOC K28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[22]}] +# set_property -dict {LOC J28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[23]}] +# set_property -dict {LOC E30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[24]}] +# set_property -dict {LOC B29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[25]}] +# set_property -dict {LOC A29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[26]}] +# set_property -dict {LOC C29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[27]}] +# set_property -dict {LOC D30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[28]}] +# set_property -dict {LOC B30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[29]}] +# set_property -dict {LOC A30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[30]}] +# set_property -dict {LOC D29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[31]}] +# set_property -dict {LOC T32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[32]}] +# set_property -dict {LOC T33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[33]}] +# set_property -dict {LOC U31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[34]}] +# set_property -dict {LOC U32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[35]}] +# set_property -dict {LOC V31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[36]}] +# set_property -dict {LOC R33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[37]}] +# set_property -dict {LOC U30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[38]}] +# set_property -dict {LOC T30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[39]}] +# set_property -dict {LOC F32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[40]}] +# set_property -dict {LOC E33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[41]}] +# set_property -dict {LOC E32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[42]}] +# set_property -dict {LOC F33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[43]}] +# set_property -dict {LOC G31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[44]}] +# set_property -dict {LOC H32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[45]}] +# set_property -dict {LOC H31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[46]}] +# set_property -dict {LOC G32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[47]}] +# set_property -dict {LOC R32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[48]}] +# set_property -dict {LOC P32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[49]}] +# set_property -dict {LOC R31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[50]}] +# set_property -dict {LOC N32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[51]}] +# set_property -dict {LOC N31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[52]}] +# set_property -dict {LOC N34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[53]}] +# set_property -dict {LOC P31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[54]}] +# set_property -dict {LOC N33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[55]}] +# set_property -dict {LOC L30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[56]}] +# set_property -dict {LOC K32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[57]}] +# set_property -dict {LOC M30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[58]}] +# set_property -dict {LOC K33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[59]}] +# set_property -dict {LOC J31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[60]}] +# set_property -dict {LOC L33 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[61]}] +# set_property -dict {LOC K31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[62]}] +# set_property -dict {LOC L32 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[63]}] +# set_property -dict {LOC J35 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[64]}] +# set_property -dict {LOC G34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[65]}] +# set_property -dict {LOC G37 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[66]}] +# set_property -dict {LOC H34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[67]}] +# set_property -dict {LOC J36 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[68]}] +# set_property -dict {LOC F35 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[69]}] +# set_property -dict {LOC F37 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[70]}] +# set_property -dict {LOC F34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dq[71]}] + +# set_property -dict {LOC P29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[0]}] +# set_property -dict {LOC N29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[0]}] +# set_property -dict {LOC F28 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[1]}] +# set_property -dict {LOC F29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[1]}] +# set_property -dict {LOC K26 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[2]}] +# set_property -dict {LOC K27 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[2]}] +# set_property -dict {LOC A27 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[3]}] +# set_property -dict {LOC A28 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[3]}] +# set_property -dict {LOC V32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[4]}] +# set_property -dict {LOC V33 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[4]}] +# set_property -dict {LOC J33 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[5]}] +# set_property -dict {LOC H33 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[5]}] +# set_property -dict {LOC M34 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[6]}] +# set_property -dict {LOC L34 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[6]}] +# set_property -dict {LOC K30 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[7]}] +# set_property -dict {LOC J30 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[7]}] +# set_property -dict {LOC H36 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_t[8]}] +# set_property -dict {LOC G36 IOSTANDARD DIFF_POD12} [get_ports {ddr4_a_dqs_c[8]}] + +# set_property -dict {LOC T28 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[0]}] +# set_property -dict {LOC J26 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[1]}] +# set_property -dict {LOC M29 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[2]}] +# set_property -dict {LOC C27 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[3]}] +# set_property -dict {LOC U34 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[4]}] +# set_property -dict {LOC G30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[5]}] +# set_property -dict {LOC R30 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[6]}] +# set_property -dict {LOC M31 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[7]}] +# set_property -dict {LOC H37 IOSTANDARD POD12_DCI} [get_ports {ddr4_a_dm_dbi_n[8]}] + +# set_property -dict {LOC A34 IOSTANDARD LVCMOS12} [get_ports {ddr4_a_odt}] +# set_property -dict {LOC E40 IOSTANDARD LVCMOS12} [get_ports {ddr4_a_rst_n}] +# set_property -dict {LOC D31 IOSTANDARD LVCMOS12} [get_ports {ddr4_a_par}] +# set_property -dict {LOC B37 IOSTANDARD LVCMOS12} [get_ports {ddr4_a_ten}] + +# DDR4 B +# set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[0]}] +# set_property -dict {LOC BA35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[1]}] +# set_property -dict {LOC AV34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[2]}] +# set_property -dict {LOC BD34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[3]}] +# set_property -dict {LOC BC34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[4]}] +# set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[5]}] +# set_property -dict {LOC BE37 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[6]}] +# set_property -dict {LOC BF38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[7]}] +# set_property -dict {LOC BF37 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[8]}] +# set_property -dict {LOC AW34 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[9]}] +# set_property -dict {LOC BD35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[10]}] +# set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[11]}] +# set_property -dict {LOC BD36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[12]}] +# set_property -dict {LOC BE38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[13]}] +# set_property -dict {LOC BB36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[14]}] +# set_property -dict {LOC BF40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[15]}] +# set_property -dict {LOC BE40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_a[16]}] + +# set_property -dict {LOC BF35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_act_n}] +# set_property -dict {LOC BD39 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_alert_n}] + +# set_property -dict {LOC BB38 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_ba[0]}] +# set_property -dict {LOC BD40 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_ba[1]}] +# set_property -dict {LOC BC36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_bg[0]}] + +# set_property -dict {LOC BB35 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_cke}] +# set_property -dict {LOC BB37 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_b_ck_t}] +# set_property -dict {LOC BC37 IOSTANDARD DIFF_SSTL2_DCI} [get_ports {ddr4_b_ck_c}] +# set_property -dict {LOC BE36 IOSTANDARD SSTL12_DCI} [get_ports {ddr4_b_cs_n}] + +# set_property -dict {LOC AP29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[0]}] +# set_property -dict {LOC AR30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[1]}] +# set_property -dict {LOC AN29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[2]}] +# set_property -dict {LOC AP30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[3]}] +# set_property -dict {LOC AL29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[4]}] +# set_property -dict {LOC AN31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[5]}] +# set_property -dict {LOC AL30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[6]}] +# set_property -dict {LOC AM31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[7]}] +# set_property -dict {LOC AT29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[8]}] +# set_property -dict {LOC AU32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[9]}] +# set_property -dict {LOC AU30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[10]}] +# set_property -dict {LOC AV31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[11]}] +# set_property -dict {LOC AT30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[12]}] +# set_property -dict {LOC AW31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[13]}] +# set_property -dict {LOC AU31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[14]}] +# set_property -dict {LOC AV32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[15]}] +# set_property -dict {LOC BB30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[16]}] +# set_property -dict {LOC AY32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[17]}] +# set_property -dict {LOC BA30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[18]}] +# set_property -dict {LOC AY30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[19]}] +# set_property -dict {LOC BA29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[20]}] +# set_property -dict {LOC AY31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[21]}] +# set_property -dict {LOC BB29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[22]}] +# set_property -dict {LOC BB31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[23]}] +# set_property -dict {LOC BF30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[24]}] +# set_property -dict {LOC BE32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[25]}] +# set_property -dict {LOC BD29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[26]}] +# set_property -dict {LOC BD33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[27]}] +# set_property -dict {LOC BE30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[28]}] +# set_property -dict {LOC BE33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[29]}] +# set_property -dict {LOC BC29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[30]}] +# set_property -dict {LOC BE31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[31]}] +# set_property -dict {LOC Y33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[32]}] +# set_property -dict {LOC W30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[33]}] +# set_property -dict {LOC W34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[34]}] +# set_property -dict {LOC Y32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[35]}] +# set_property -dict {LOC AA34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[36]}] +# set_property -dict {LOC Y30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[37]}] +# set_property -dict {LOC AB34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[38]}] +# set_property -dict {LOC W33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[39]}] +# set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[40]}] +# set_property -dict {LOC AG30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[41]}] +# set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[42]}] +# set_property -dict {LOC AK28 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[43]}] +# set_property -dict {LOC AK31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[44]}] +# set_property -dict {LOC AG29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[45]}] +# set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[46]}] +# set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[47]}] +# set_property -dict {LOC AC32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[48]}] +# set_property -dict {LOC AE33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[49]}] +# set_property -dict {LOC AC33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[50]}] +# set_property -dict {LOC AD34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[51]}] +# set_property -dict {LOC AC34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[52]}] +# set_property -dict {LOC AD33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[53]}] +# set_property -dict {LOC AE30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[54]}] +# set_property -dict {LOC AF30 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[55]}] +# set_property -dict {LOC AF34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[56]}] +# set_property -dict {LOC AJ33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[57]}] +# set_property -dict {LOC AH33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[58]}] +# set_property -dict {LOC AG32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[59]}] +# set_property -dict {LOC AF33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[60]}] +# set_property -dict {LOC AG31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[61]}] +# set_property -dict {LOC AF32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[62]}] +# set_property -dict {LOC AG34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[63]}] +# set_property -dict {LOC AN34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[64]}] +# set_property -dict {LOC AL34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[65]}] +# set_property -dict {LOC AP34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[66]}] +# set_property -dict {LOC AM32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[67]}] +# set_property -dict {LOC AR33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[68]}] +# set_property -dict {LOC AL32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[69]}] +# set_property -dict {LOC AP33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[70]}] +# set_property -dict {LOC AM34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dq[71]}] + +# set_property -dict {LOC AM29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[0]}] +# set_property -dict {LOC AM30 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[0]}] +# set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[1]}] +# set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[1]}] +# set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[2]}] +# set_property -dict {LOC BB32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[2]}] +# set_property -dict {LOC BD30 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[3]}] +# set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[3]}] +# set_property -dict {LOC W31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[4]}] +# set_property -dict {LOC Y31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[4]}] +# set_property -dict {LOC AH28 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[5]}] +# set_property -dict {LOC AH29 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[5]}] +# set_property -dict {LOC AC31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[6]}] +# set_property -dict {LOC AD31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[6]}] +# set_property -dict {LOC AH31 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[7]}] +# set_property -dict {LOC AH32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[7]}] +# set_property -dict {LOC AN32 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_t[8]}] +# set_property -dict {LOC AN33 IOSTANDARD DIFF_POD12} [get_ports {ddr4_b_dqs_c[8]}] + +# set_property -dict {LOC AP31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[0]}] +# set_property -dict {LOC AW29 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[1]}] +# set_property -dict {LOC BC31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[2]}] +# set_property -dict {LOC BF32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[3]}] +# set_property -dict {LOC AA32 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[4]}] +# set_property -dict {LOC AJ27 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[5]}] +# set_property -dict {LOC AE31 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[6]}] +# set_property -dict {LOC AH34 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[7]}] +# set_property -dict {LOC AT33 IOSTANDARD POD12_DCI} [get_ports {ddr4_b_dm_dbi_n[8]}] + +# set_property -dict {LOC BE35 IOSTANDARD LVCMOS12} [get_ports {ddr4_b_odt}] +# set_property -dict {LOC AY36 IOSTANDARD LVCMOS12} [get_ports {ddr4_b_rst_n}] +# set_property -dict {LOC AV33 IOSTANDARD LVCMOS12} [get_ports {ddr4_b_par}] +# set_property -dict {LOC BF39 IOSTANDARD LVCMOS12} [get_ports {ddr4_b_ten}] + +# QSFP28 Interfaces + +# QSFP 1 +set_property -dict {LOC G40 } [get_ports {qsfp_1_tx_p[1]}] ;# MGTYTXP0_133 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC G41 } [get_ports {qsfp_1_tx_n[1]}] ;# MGTYTXN0_133 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC J45 } [get_ports {qsfp_1_rx_p[1]}] ;# MGTYRXP0_133 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC J46 } [get_ports {qsfp_1_rx_n[1]}] ;# MGTYRXN0_133 GTYE4_CHANNEL_X0Y36 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC E42 } [get_ports {qsfp_1_tx_p[2]}] ;# MGTYTXP1_133 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC E43 } [get_ports {qsfp_1_tx_n[2]}] ;# MGTYTXN1_133 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC H43 } [get_ports {qsfp_1_rx_p[2]}] ;# MGTYRXP1_133 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC H44 } [get_ports {qsfp_1_rx_n[2]}] ;# MGTYRXN1_133 GTYE4_CHANNEL_X0Y37 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC C42 } [get_ports {qsfp_1_tx_p[0]}] ;# MGTYTXP2_133 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC C43 } [get_ports {qsfp_1_tx_n[0]}] ;# MGTYTXN2_133 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC F45 } [get_ports {qsfp_1_rx_p[0]}] ;# MGTYRXP2_133 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC F46 } [get_ports {qsfp_1_rx_n[0]}] ;# MGTYRXN2_133 GTYE4_CHANNEL_X0Y38 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC A42 } [get_ports {qsfp_1_tx_p[3]}] ;# MGTYTXP3_133 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC A43 } [get_ports {qsfp_1_tx_n[3]}] ;# MGTYTXN3_133 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC D45 } [get_ports {qsfp_1_rx_p[3]}] ;# MGTYRXP3_133 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC D46 } [get_ports {qsfp_1_rx_n[3]}] ;# MGTYRXN3_133 GTYE4_CHANNEL_X0Y39 / GTYE4_COMMON_X0Y9 +set_property -dict {LOC K38 } [get_ports qsfp_1_mgt_refclk_p] ;# MGTREFCLK1P_133 from U48.28 OUT1_P +set_property -dict {LOC K39 } [get_ports qsfp_1_mgt_refclk_n] ;# MGTREFCLK1N_133 from U48.27 OUT1_N +set_property -dict {LOC BB20 IOSTANDARD LVCMOS18} [get_ports qsfp_1_resetl] +set_property -dict {LOC BE21 IOSTANDARD LVCMOS18} [get_ports qsfp_1_modprsl] +set_property -dict {LOC BA20 IOSTANDARD LVCMOS18} [get_ports qsfp_1_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p] + +# QSFP 2 +set_property -dict {LOC N40 } [get_ports {qsfp_2_tx_p[1]}] ;# MGTYTXP0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N41 } [get_ports {qsfp_2_tx_n[1]}] ;# MGTYTXN0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N45 } [get_ports {qsfp_2_rx_p[1]}] ;# MGTYRXP0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC N46 } [get_ports {qsfp_2_rx_n[1]}] ;# MGTYRXN0_132 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M38 } [get_ports {qsfp_2_tx_p[2]}] ;# MGTYTXP1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M39 } [get_ports {qsfp_2_tx_n[2]}] ;# MGTYTXN1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M43 } [get_ports {qsfp_2_rx_p[2]}] ;# MGTYRXP1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC M44 } [get_ports {qsfp_2_rx_n[2]}] ;# MGTYRXN1_132 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L40 } [get_ports {qsfp_2_tx_p[0]}] ;# MGTYTXP2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L41 } [get_ports {qsfp_2_tx_n[0]}] ;# MGTYTXN2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L45 } [get_ports {qsfp_2_rx_p[0]}] ;# MGTYRXP2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC L46 } [get_ports {qsfp_2_rx_n[0]}] ;# MGTYRXN2_132 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC J40 } [get_ports {qsfp_2_tx_p[3]}] ;# MGTYTXP3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC J41 } [get_ports {qsfp_2_tx_n[3]}] ;# MGTYTXN3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC K43 } [get_ports {qsfp_2_rx_p[3]}] ;# MGTYRXP3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC K44 } [get_ports {qsfp_2_rx_n[3]}] ;# MGTYRXN3_132 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 +set_property -dict {LOC R36 } [get_ports qsfp_2_mgt_refclk_p] ;# MGTREFCLK0P_132 from U48.35 OUT3_P +set_property -dict {LOC R37 } [get_ports qsfp_2_mgt_refclk_n] ;# MGTREFCLK0N_132 from U48.34 OUT3_N +set_property -dict {LOC BE22 IOSTANDARD LVCMOS18} [get_ports qsfp_2_resetl] +set_property -dict {LOC BD21 IOSTANDARD LVCMOS18} [get_ports qsfp_2_modprsl] +set_property -dict {LOC BF22 IOSTANDARD LVCMOS18} [get_ports qsfp_2_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_2_mgt_refclk [get_ports qsfp_2_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_2_mgt_refclk [get_ports qsfp_2_mgt_refclk_p] + +# QSFP 3 +set_property -dict {LOC U40 } [get_ports {qsfp_3_tx_p[1]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC U41 } [get_ports {qsfp_3_tx_n[1]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC U45 } [get_ports {qsfp_3_rx_p[1]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC U46 } [get_ports {qsfp_3_rx_n[1]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T38 } [get_ports {qsfp_3_tx_p[2]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T39 } [get_ports {qsfp_3_tx_n[2]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T43 } [get_ports {qsfp_3_rx_p[2]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC T44 } [get_ports {qsfp_3_rx_n[2]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R40 } [get_ports {qsfp_3_tx_p[0]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R41 } [get_ports {qsfp_3_tx_n[0]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R45 } [get_ports {qsfp_3_rx_p[0]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC R46 } [get_ports {qsfp_3_rx_n[0]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P38 } [get_ports {qsfp_3_tx_p[3]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P39 } [get_ports {qsfp_3_tx_n[3]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P43 } [get_ports {qsfp_3_rx_p[3]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC P44 } [get_ports {qsfp_3_rx_n[3]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 +set_property -dict {LOC W36 } [get_ports qsfp_3_mgt_refclk_p] ;# MGTREFCLK0P_131 from U48.38 OUT4_P +set_property -dict {LOC W37 } [get_ports qsfp_3_mgt_refclk_n] ;# MGTREFCLK0N_131 from U48.37 OUT4_N +set_property -dict {LOC AY23 IOSTANDARD LVCMOS18} [get_ports qsfp_3_resetl] +set_property -dict {LOC AY22 IOSTANDARD LVCMOS18} [get_ports qsfp_3_modprsl] +set_property -dict {LOC BA22 IOSTANDARD LVCMOS18} [get_ports qsfp_3_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_3_mgt_refclk [get_ports qsfp_3_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_3_mgt_refclk [get_ports qsfp_3_mgt_refclk_p] + +# QSFP 4 +set_property -dict {LOC AA40} [get_ports {qsfp_4_tx_p[1]}] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA41} [get_ports {qsfp_4_tx_n[1]}] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA45} [get_ports {qsfp_4_rx_p[1]}] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AA46} [get_ports {qsfp_4_rx_n[1]}] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y38 } [get_ports {qsfp_4_tx_p[2]}] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y39 } [get_ports {qsfp_4_tx_n[2]}] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y43 } [get_ports {qsfp_4_rx_p[2]}] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC Y44 } [get_ports {qsfp_4_rx_n[2]}] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W40 } [get_ports {qsfp_4_tx_p[0]}] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W41 } [get_ports {qsfp_4_tx_n[0]}] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W45 } [get_ports {qsfp_4_rx_p[0]}] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC W46 } [get_ports {qsfp_4_rx_n[0]}] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V38 } [get_ports {qsfp_4_tx_p[3]}] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V39 } [get_ports {qsfp_4_tx_n[3]}] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V43 } [get_ports {qsfp_4_rx_p[3]}] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC V44 } [get_ports {qsfp_4_rx_n[3]}] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 +set_property -dict {LOC AC36} [get_ports qsfp_4_mgt_refclk_p] ;# MGTREFCLK0P_130 from U48.42 OUT5_P +set_property -dict {LOC AC37} [get_ports qsfp_4_mgt_refclk_n] ;# MGTREFCLK0N_130 from U48.41 OUT5_N +set_property -dict {LOC BC22 IOSTANDARD LVCMOS18} [get_ports qsfp_4_resetl] +set_property -dict {LOC BB22 IOSTANDARD LVCMOS18} [get_ports qsfp_4_modprsl] +set_property -dict {LOC BA23 IOSTANDARD LVCMOS18} [get_ports qsfp_4_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_4_mgt_refclk [get_ports qsfp_4_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_4_mgt_refclk [get_ports qsfp_4_mgt_refclk_p] + +# QSFP 5 +set_property -dict {LOC AE40} [get_ports {qsfp_5_tx_p[1]}] ;# MGTYTXP0_129 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AE41} [get_ports {qsfp_5_tx_n[1]}] ;# MGTYTXN0_129 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AE45} [get_ports {qsfp_5_rx_p[1]}] ;# MGTYRXP0_129 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AE46} [get_ports {qsfp_5_rx_n[1]}] ;# MGTYRXN0_129 GTYE4_CHANNEL_X0Y20 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD38} [get_ports {qsfp_5_tx_p[2]}] ;# MGTYTXP1_129 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD39} [get_ports {qsfp_5_tx_n[2]}] ;# MGTYTXN1_129 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD43} [get_ports {qsfp_5_rx_p[2]}] ;# MGTYRXP1_129 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AD44} [get_ports {qsfp_5_rx_n[2]}] ;# MGTYRXN1_129 GTYE4_CHANNEL_X0Y21 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC40} [get_ports {qsfp_5_tx_p[3]}] ;# MGTYTXP2_129 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC41} [get_ports {qsfp_5_tx_n[3]}] ;# MGTYTXN2_129 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC45} [get_ports {qsfp_5_rx_p[3]}] ;# MGTYRXP2_129 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AC46} [get_ports {qsfp_5_rx_n[3]}] ;# MGTYRXN2_129 GTYE4_CHANNEL_X0Y22 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB38} [get_ports {qsfp_5_tx_p[0]}] ;# MGTYTXP3_129 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB39} [get_ports {qsfp_5_tx_n[0]}] ;# MGTYTXN3_129 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB43} [get_ports {qsfp_5_rx_p[0]}] ;# MGTYRXP3_129 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AB44} [get_ports {qsfp_5_rx_n[0]}] ;# MGTYRXN3_129 GTYE4_CHANNEL_X0Y23 / GTYE4_COMMON_X0Y5 +set_property -dict {LOC AG36} [get_ports qsfp_5_mgt_refclk_p] ;# MGTREFCLK0P_129 from U48.24 OUT0_P +set_property -dict {LOC AG37} [get_ports qsfp_5_mgt_refclk_n] ;# MGTREFCLK0N_129 from U48.23 OUT0_N +set_property -dict {LOC BD23 IOSTANDARD LVCMOS18} [get_ports qsfp_5_resetl] +set_property -dict {LOC BE23 IOSTANDARD LVCMOS18} [get_ports qsfp_5_modprsl] +set_property -dict {LOC BF23 IOSTANDARD LVCMOS18} [get_ports qsfp_5_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_5_mgt_refclk [get_ports qsfp_5_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_5_mgt_refclk [get_ports qsfp_5_mgt_refclk_p] + +# QSFP 6 +set_property -dict {LOC AJ40} [get_ports {qsfp_6_tx_p[1]}] ;# MGTYTXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ41} [get_ports {qsfp_6_tx_n[1]}] ;# MGTYTXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ45} [get_ports {qsfp_6_rx_p[1]}] ;# MGTYRXP0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AJ46} [get_ports {qsfp_6_rx_n[1]}] ;# MGTYRXN0_128 GTYE4_CHANNEL_X0Y16 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH38} [get_ports {qsfp_6_tx_p[2]}] ;# MGTYTXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH39} [get_ports {qsfp_6_tx_n[2]}] ;# MGTYTXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH43} [get_ports {qsfp_6_rx_p[2]}] ;# MGTYRXP1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AH44} [get_ports {qsfp_6_rx_n[2]}] ;# MGTYRXN1_128 GTYE4_CHANNEL_X0Y17 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG40} [get_ports {qsfp_6_tx_p[0]}] ;# MGTYTXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG41} [get_ports {qsfp_6_tx_n[0]}] ;# MGTYTXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG45} [get_ports {qsfp_6_rx_p[0]}] ;# MGTYRXP2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AG46} [get_ports {qsfp_6_rx_n[0]}] ;# MGTYRXN2_128 GTYE4_CHANNEL_X0Y18 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF38} [get_ports {qsfp_6_tx_p[3]}] ;# MGTYTXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF39} [get_ports {qsfp_6_tx_n[3]}] ;# MGTYTXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF43} [get_ports {qsfp_6_rx_p[3]}] ;# MGTYRXP3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AF44} [get_ports {qsfp_6_rx_n[3]}] ;# MGTYRXN3_128 GTYE4_CHANNEL_X0Y19 / GTYE4_COMMON_X0Y4 +set_property -dict {LOC AL36} [get_ports qsfp_6_mgt_refclk_p] ;# MGTREFCLK0P_128 from U48.59 OUT9_P +set_property -dict {LOC AL37} [get_ports qsfp_6_mgt_refclk_n] ;# MGTREFCLK0N_128 from U48.58 OUT9_N +set_property -dict {LOC AW24 IOSTANDARD LVCMOS18} [get_ports qsfp_6_resetl] +set_property -dict {LOC AR23 IOSTANDARD LVCMOS18} [get_ports qsfp_6_modprsl] +set_property -dict {LOC AV24 IOSTANDARD LVCMOS18} [get_ports qsfp_6_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_6_mgt_refclk [get_ports qsfp_6_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_6_mgt_refclk [get_ports qsfp_6_mgt_refclk_p] + +# QSFP 7 +set_property -dict {LOC AN40} [get_ports {qsfp_7_tx_p[1]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN41} [get_ports {qsfp_7_tx_n[1]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN45} [get_ports {qsfp_7_rx_p[1]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AN46} [get_ports {qsfp_7_rx_n[1]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM38} [get_ports {qsfp_7_tx_p[2]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM39} [get_ports {qsfp_7_tx_n[2]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM43} [get_ports {qsfp_7_rx_p[2]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AM44} [get_ports {qsfp_7_rx_n[2]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL40} [get_ports {qsfp_7_tx_p[0]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL41} [get_ports {qsfp_7_tx_n[0]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL45} [get_ports {qsfp_7_rx_p[0]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AL46} [get_ports {qsfp_7_rx_n[0]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK38} [get_ports {qsfp_7_tx_p[3]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK39} [get_ports {qsfp_7_tx_n[3]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK43} [get_ports {qsfp_7_rx_p[3]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AK44} [get_ports {qsfp_7_rx_n[3]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 +set_property -dict {LOC AR36} [get_ports qsfp_7_mgt_refclk_p] ;# MGTREFCLK0P_127 from U48.54 OUT8_P +set_property -dict {LOC AR37} [get_ports qsfp_7_mgt_refclk_n] ;# MGTREFCLK0N_127 from U48.53 OUT8_N +set_property -dict {LOC AU24 IOSTANDARD LVCMOS18} [get_ports qsfp_7_resetl] +set_property -dict {LOC AN23 IOSTANDARD LVCMOS18} [get_ports qsfp_7_modprsl] +set_property -dict {LOC AT24 IOSTANDARD LVCMOS18} [get_ports qsfp_7_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_7_mgt_refclk [get_ports qsfp_7_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_7_mgt_refclk [get_ports qsfp_7_mgt_refclk_p] + +# QSFP 8 +set_property -dict {LOC AU40} [get_ports {qsfp_8_tx_p[1]}] ;# MGTYTXP0_126 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU41} [get_ports {qsfp_8_tx_n[1]}] ;# MGTYTXN0_126 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU45} [get_ports {qsfp_8_rx_p[1]}] ;# MGTYRXP0_126 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AU46} [get_ports {qsfp_8_rx_n[1]}] ;# MGTYRXN0_126 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT38} [get_ports {qsfp_8_tx_p[2]}] ;# MGTYTXP1_126 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT39} [get_ports {qsfp_8_tx_n[2]}] ;# MGTYTXN1_126 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT43} [get_ports {qsfp_8_rx_p[2]}] ;# MGTYRXP1_126 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AT44} [get_ports {qsfp_8_rx_n[2]}] ;# MGTYRXN1_126 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR40} [get_ports {qsfp_8_tx_p[0]}] ;# MGTYTXP2_126 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR41} [get_ports {qsfp_8_tx_n[0]}] ;# MGTYTXN2_126 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR45} [get_ports {qsfp_8_rx_p[0]}] ;# MGTYRXP2_126 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AR46} [get_ports {qsfp_8_rx_n[0]}] ;# MGTYRXN2_126 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP38} [get_ports {qsfp_8_tx_p[3]}] ;# MGTYTXP3_126 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP39} [get_ports {qsfp_8_tx_n[3]}] ;# MGTYTXN3_126 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP43} [get_ports {qsfp_8_rx_p[3]}] ;# MGTYRXP3_126 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AP44} [get_ports {qsfp_8_rx_n[3]}] ;# MGTYRXN3_126 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 +set_property -dict {LOC AV38} [get_ports qsfp_8_mgt_refclk_p] ;# MGTREFCLK0P_126 from U48.45 OUT6_P +set_property -dict {LOC AV39} [get_ports qsfp_8_mgt_refclk_n] ;# MGTREFCLK0N_126 from U48.44 OUT6_N +set_property -dict {LOC AN24 IOSTANDARD LVCMOS18} [get_ports qsfp_8_resetl] +set_property -dict {LOC AP24 IOSTANDARD LVCMOS18} [get_ports qsfp_8_modprsl] +set_property -dict {LOC AP23 IOSTANDARD LVCMOS18} [get_ports qsfp_8_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_8_mgt_refclk [get_ports qsfp_8_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_8_mgt_refclk [get_ports qsfp_8_mgt_refclk_p] + +# QSFP 9 +set_property -dict {LOC BF42} [get_ports {qsfp_9_tx_p[1]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BF43} [get_ports {qsfp_9_tx_n[1]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BC45} [get_ports {qsfp_9_rx_p[1]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BC46} [get_ports {qsfp_9_rx_n[1]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BD42} [get_ports {qsfp_9_tx_p[2]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BD43} [get_ports {qsfp_9_tx_n[2]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA45} [get_ports {qsfp_9_rx_p[2]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA46} [get_ports {qsfp_9_rx_n[2]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BB42} [get_ports {qsfp_9_tx_p[0]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BB43} [get_ports {qsfp_9_tx_n[0]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW45} [get_ports {qsfp_9_rx_p[0]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW46} [get_ports {qsfp_9_rx_n[0]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW40} [get_ports {qsfp_9_tx_p[3]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AW41} [get_ports {qsfp_9_tx_n[3]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AV43} [get_ports {qsfp_9_rx_p[3]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC AV44} [get_ports {qsfp_9_rx_n[3]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 +set_property -dict {LOC BA40} [get_ports qsfp_9_mgt_refclk_p] ;# MGTREFCLK0P_125 from U48.51 OUT7_P +set_property -dict {LOC BA41} [get_ports qsfp_9_mgt_refclk_n] ;# MGTREFCLK0N_125 from U48.50 OUT7_N +set_property -dict {LOC AM24 IOSTANDARD LVCMOS18} [get_ports qsfp_9_resetl] +set_property -dict {LOC AM22 IOSTANDARD LVCMOS18} [get_ports qsfp_9_modprsl] +set_property -dict {LOC AL24 IOSTANDARD LVCMOS18} [get_ports qsfp_9_intl] + +# 156.25 MHz MGT reference clock +# create_clock -period 6.400 -name qsfp_9_mgt_refclk [get_ports qsfp_9_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +create_clock -period 6.206 -name qsfp_9_mgt_refclk [get_ports qsfp_9_mgt_refclk_p] + +# SMA (GTY) +#set_property -dict {LOC E9 } [get_ports {sma_tx_p[0]}] ;# MGTYTXP0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC E8 } [get_ports {sma_tx_n[0]}] ;# MGTYTXN0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC E4 } [get_ports {sma_rx_p[0]}] ;# MGTYRXP0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC E3 } [get_ports {sma_rx_n[0]}] ;# MGTYRXN0_233 GTYE4_CHANNEL_X1Y56 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D7 } [get_ports {sma_tx_p[1]}] ;# MGTYTXP1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D6 } [get_ports {sma_tx_n[1]}] ;# MGTYTXN1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D2 } [get_ports {sma_rx_p[1]}] ;# MGTYRXP1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D1 } [get_ports {sma_rx_n[1]}] ;# MGTYRXN1_233 GTYE4_CHANNEL_X1Y57 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC C9 } [get_ports {sma_tx_p[2]}] ;# MGTYTXP2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC C8 } [get_ports {sma_tx_n[2]}] ;# MGTYTXN2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC C4 } [get_ports {sma_rx_p[2]}] ;# MGTYRXP2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC C3 } [get_ports {sma_rx_n[2]}] ;# MGTYRXN2_233 GTYE4_CHANNEL_X1Y58 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC A9 } [get_ports {sma_tx_p[3]}] ;# MGTYTXP3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC A8 } [get_ports {sma_tx_n[3]}] ;# MGTYTXN3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC A5 } [get_ports {sma_rx_p[3]}] ;# MGTYRXP3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC A4 } [get_ports {sma_rx_n[3]}] ;# MGTYRXN3_233 GTYE4_CHANNEL_X1Y59 / GTYE4_COMMON_X1Y14 +#set_property -dict {LOC D11 } [get_ports sma_mgt_refclk_p] ;# MGTREFCLK0P_233 from X20 SMA CLKP +#set_property -dict {LOC D10 } [get_ports sma_mgt_refclk_n] ;# MGTREFCLK0N_233 from X19 SMA CLKN + +# 156.25 MHz MGT reference clock +#create_clock -period 6.400 -name sma_mgt_refclk [get_ports sma_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +#create_clock -period 6.206 -name sma_mgt_refclk [get_ports sma_mgt_refclk_p] + +# FireFly +#set_property -dict {LOC BF5 } [get_ports {ff_tx_p[0]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BF4 } [get_ports {ff_tx_n[0]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BC2 } [get_ports {ff_rx_p[0]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BC1 } [get_ports {ff_rx_n[0]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BD5 } [get_ports {ff_tx_p[2]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BD4 } [get_ports {ff_tx_n[2]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BA2 } [get_ports {ff_rx_p[2]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BA1 } [get_ports {ff_rx_n[2]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BB5 } [get_ports {ff_tx_p[1]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC BB4 } [get_ports {ff_tx_n[1]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AW4 } [get_ports {ff_rx_p[1]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AW3 } [get_ports {ff_rx_n[1]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AV7 } [get_ports {ff_tx_p[3]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AV6 } [get_ports {ff_tx_n[3]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AV2 } [get_ports {ff_rx_p[3]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AV1 } [get_ports {ff_rx_n[3]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 +#set_property -dict {LOC AU9 } [get_ports {ff_tx_p[5]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU8 } [get_ports {ff_tx_n[5]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU4 } [get_ports {ff_rx_p[5]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AU3 } [get_ports {ff_rx_n[5]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT7 } [get_ports {ff_tx_p[7]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT6 } [get_ports {ff_tx_n[7]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT2 } [get_ports {ff_rx_p[7]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AT1 } [get_ports {ff_rx_n[7]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR9 } [get_ports {ff_tx_p[4]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR8 } [get_ports {ff_tx_n[4]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR4 } [get_ports {ff_rx_p[4]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AR3 } [get_ports {ff_rx_n[4]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP7 } [get_ports {ff_tx_p[6]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP6 } [get_ports {ff_tx_n[6]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP2 } [get_ports {ff_rx_p[6]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AP1 } [get_ports {ff_rx_n[6]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 +#set_property -dict {LOC AN9 } [get_ports {ff_tx_p[11]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AN8 } [get_ports {ff_tx_n[11]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AN4 } [get_ports {ff_rx_p[11]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AN3 } [get_ports {ff_rx_n[11]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM7 } [get_ports {ff_tx_p[9]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM6 } [get_ports {ff_tx_n[9]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM2 } [get_ports {ff_rx_p[9]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AM1 } [get_ports {ff_rx_n[9]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AL9 } [get_ports {ff_tx_p[10]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AL8 } [get_ports {ff_tx_n[10]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AL4 } [get_ports {ff_rx_p[10]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AL3 } [get_ports {ff_rx_n[10]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AK7 } [get_ports {ff_tx_p[8]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AK6 } [get_ports {ff_tx_n[8]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AK2 } [get_ports {ff_rx_p[8]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AK1 } [get_ports {ff_rx_n[8]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 +#set_property -dict {LOC AP11} [get_ports ff_mgt_refclk_p] ;# MGTREFCLK1P_225 from U48.31 OUT2_P +#set_property -dict {LOC AP10} [get_ports ff_mgt_refclk_n] ;# MGTREFCLK1N_225 from U48.30 OUT2_N +#set_property -dict {LOC M22 IOSTANDARD LVCMOS18} [get_ports ff_tx_int_l] +#set_property -dict {LOC P21 IOSTANDARD LVCMOS18} [get_ports ff_tx_gpio] +#set_property -dict {LOC N23 IOSTANDARD LVCMOS18} [get_ports ff_tx_prsnt_l] +#set_property -dict {LOC N22 IOSTANDARD LVCMOS18} [get_ports ff_rx_int_l] +#set_property -dict {LOC R21 IOSTANDARD LVCMOS18} [get_ports ff_rx_gpio] +#set_property -dict {LOC P23 IOSTANDARD LVCMOS18} [get_ports ff_rx_prsnt_l] + +# 100 MHz MGT reference clock +#create_clock -period 10.000 -name ff_mgt_refclk [get_ports ff_mgt_refclk_p] + +# 156.25 MHz MGT reference clock +#create_clock -period 6.400 -name ff_mgt_refclk [get_ports ff_mgt_refclk_p] + +# 161.1328125 MHz MGT reference clock +#create_clock -period 6.206 -name ff_mgt_refclk [get_ports ff_mgt_refclk_p] + +# FMC+ J9 +#set_property -dict {LOC BA15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[0]}] ;# J9.G9 LA00_P_CC +#set_property -dict {LOC BA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[0]}] ;# J9.G10 LA00_N_CC +#set_property -dict {LOC AY13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[1]}] ;# J9.D8 LA01_P_CC +#set_property -dict {LOC BA13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[1]}] ;# J9.D9 LA01_N_CC +#set_property -dict {LOC AL15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[2]}] ;# J9.H7 LA02_P +#set_property -dict {LOC AM15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[2]}] ;# J9.H8 LA02_N +#set_property -dict {LOC AN14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[3]}] ;# J9.G12 LA03_P +#set_property -dict {LOC AN13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[3]}] ;# J9.G13 LA03_N +#set_property -dict {LOC AL14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[4]}] ;# J9.H10 LA04_P +#set_property -dict {LOC AM14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[4]}] ;# J9.H11 LA04_N +#set_property -dict {LOC AP13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[5]}] ;# J9.D11 LA05_P +#set_property -dict {LOC AR13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[5]}] ;# J9.D12 LA05_N +#set_property -dict {LOC AP15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[6]}] ;# J9.C10 LA06_P +#set_property -dict {LOC AP14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[6]}] ;# J9.C11 LA06_N +#set_property -dict {LOC AU16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[7]}] ;# J9.H13 LA07_P +#set_property -dict {LOC AV16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[7]}] ;# J9.H14 LA07_N +#set_property -dict {LOC AR16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[8]}] ;# J9.G12 LA08_P +#set_property -dict {LOC AR15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[8]}] ;# J9.G13 LA08_N +#set_property -dict {LOC AT15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[9]}] ;# J9.D14 LA09_P +#set_property -dict {LOC AU15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[9]}] ;# J9.D15 LA09_N +#set_property -dict {LOC AU14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[10]}] ;# J9.C14 LA10_P +#set_property -dict {LOC AV14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[10]}] ;# J9.C15 LA10_N +#set_property -dict {LOC BD15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[11]}] ;# J9.H16 LA11_P +#set_property -dict {LOC BD14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[11]}] ;# J9.H17 LA11_N +#set_property -dict {LOC AY12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[12]}] ;# J9.G15 LA12_P +#set_property -dict {LOC AY11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[12]}] ;# J9.G16 LA12_N +#set_property -dict {LOC BA12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[13]}] ;# J9.D17 LA13_P +#set_property -dict {LOC BB12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[13]}] ;# J9.D18 LA13_N +#set_property -dict {LOC BB15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[14]}] ;# J9.C18 LA14_P +#set_property -dict {LOC BB14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[14]}] ;# J9.C19 LA14_N +#set_property -dict {LOC BF14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[15]}] ;# J9.H19 LA15_P +#set_property -dict {LOC BF13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[15]}] ;# J9.H20 LA15_N +#set_property -dict {LOC BD16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[16]}] ;# J9.G18 LA16_P +#set_property -dict {LOC BE16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[16]}] ;# J9.G19 LA16_N +#set_property -dict {LOC AT20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[17]}] ;# J9.D20 LA17_P_CC +#set_property -dict {LOC AU20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[17]}] ;# J9.D21 LA17_N_CC +#set_property -dict {LOC AV19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[18]}] ;# J9.C22 LA18_P_CC +#set_property -dict {LOC AW19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[18]}] ;# J9.C23 LA18_N_CC +#set_property -dict {LOC AR17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[19]}] ;# J9.H22 LA19_P +#set_property -dict {LOC AT17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[19]}] ;# J9.H23 LA19_N +#set_property -dict {LOC AN18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[20]}] ;# J9.G21 LA20_P +#set_property -dict {LOC AN17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[20]}] ;# J9.G22 LA20_N +#set_property -dict {LOC AW20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[21]}] ;# J9.H25 LA21_P +#set_property -dict {LOC AY20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[21]}] ;# J9.H26 LA21_N +#set_property -dict {LOC AT19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[22]}] ;# J9.G24 LA22_P +#set_property -dict {LOC AU19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[22]}] ;# J9.G25 LA22_N +#set_property -dict {LOC AL17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[23]}] ;# J9.D23 LA23_P +#set_property -dict {LOC AM17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[23]}] ;# J9.D24 LA23_N +#set_property -dict {LOC AY17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[24]}] ;# J9.H28 LA24_P +#set_property -dict {LOC BA17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[24]}] ;# J9.H29 LA24_N +#set_property -dict {LOC AY18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[25]}] ;# J9.G27 LA25_P +#set_property -dict {LOC BA18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[25]}] ;# J9.G28 LA25_N +#set_property -dict {LOC AP20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[26]}] ;# J9.D26 LA26_P +#set_property -dict {LOC AP20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[26]}] ;# J9.D27 LA26_N +#set_property -dict {LOC AN19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[27]}] ;# J9.C26 LA27_P +#set_property -dict {LOC AP19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[27]}] ;# J9.C27 LA27_N +#set_property -dict {LOC BB17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[28]}] ;# J9.H31 LA28_P +#set_property -dict {LOC BC17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[28]}] ;# J9.H32 LA28_N +#set_property -dict {LOC BB19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[29]}] ;# J9.G30 LA29_P +#set_property -dict {LOC BC18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[29]}] ;# J9.G31 LA29_N +#set_property -dict {LOC BD18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[30]}] ;# J9.H34 LA30_P +#set_property -dict {LOC BE18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[30]}] ;# J9.H35 LA30_N +#set_property -dict {LOC BC19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[31]}] ;# J9.G33 LA31_P +#set_property -dict {LOC BD19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[31]}] ;# J9.G34 LA31_N +#set_property -dict {LOC BF19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[32]}] ;# J9.H37 LA32_P +#set_property -dict {LOC BF18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[32]}] ;# J9.H38 LA32_N +#set_property -dict {LOC BE17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_p[33]}] ;# J9.G36 LA33_P +#set_property -dict {LOC BF17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_la_n[33]}] ;# J9.G37 LA33_N + +#set_property -dict {LOC G14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[0]}] ;# J9.F4 HA00_P_CC +#set_property -dict {LOC F14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[0]}] ;# J9.F5 HA00_N_CC +#set_property -dict {LOC G15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[1]}] ;# J9.E2 HA01_P_CC +#set_property -dict {LOC F15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[1]}] ;# J9.E3 HA01_N_CC +#set_property -dict {LOC A14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[2]}] ;# J9.K7 HA02_P +#set_property -dict {LOC A13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[2]}] ;# J9.K8 HA02_N +#set_property -dict {LOC B17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[3]}] ;# J9.J6 HA03_P +#set_property -dict {LOC A17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[3]}] ;# J9.J7 HA03_N +#set_property -dict {LOC C16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[4]}] ;# J9.F7 HA04_P +#set_property -dict {LOC B16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[4]}] ;# J9.F8 HA04_N +#set_property -dict {LOC B15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[5]}] ;# J9.E6 HA05_P +#set_property -dict {LOC A15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[5]}] ;# J9.E7 HA05_N +#set_property -dict {LOC G17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[6]}] ;# J9.K10 HA06_P +#set_property -dict {LOC G16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[6]}] ;# J9.K11 HA06_N +#set_property -dict {LOC D13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[7]}] ;# J9.J9 HA07_P +#set_property -dict {LOC C13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[7]}] ;# J9.J10 HA07_N +#set_property -dict {LOC E15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[8]}] ;# J9.F10 HA08_P +#set_property -dict {LOC D15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[8]}] ;# J9.F11 HA08_N +#set_property -dict {LOC E16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[9]}] ;# J9.E9 HA09_P +#set_property -dict {LOC D16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[9]}] ;# J9.E10 HA09_N +#set_property -dict {LOC R16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[10]}] ;# J9.K13 HA10_P +#set_property -dict {LOC P16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[10]}] ;# J9.K14 HA10_N +#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[11]}] ;# J9.J12 HA11_P +#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[11]}] ;# J9.J13 HA11_N +#set_property -dict {LOC H17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[12]}] ;# J9.F13 HA12_P +#set_property -dict {LOC H16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[12]}] ;# J9.F14 HA12_N +#set_property -dict {LOC J13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[13]}] ;# J9.E12 HA13_P +#set_property -dict {LOC H13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[13]}] ;# J9.E13 HA13_N +#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[14]}] ;# J9.J15 HA14_P +#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[14]}] ;# J9.J16 HA14_N +#set_property -dict {LOC N16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[15]}] ;# J9.F14 HA15_P +#set_property -dict {LOC M16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[15]}] ;# J9.F16 HA15_N +#set_property -dict {LOC M14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[16]}] ;# J9.E15 HA16_P +#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[16]}] ;# J9.E16 HA16_N +#set_property -dict {LOC J14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[17]}] ;# J9.K16 HA17_P_CC +#set_property -dict {LOC H14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[17]}] ;# J9.K17 HA17_N_CC +#set_property -dict {LOC J16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[18]}] ;# J9.J18 HA18_P_CC +#set_property -dict {LOC J15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[18]}] ;# J9.J19 HA18_N_CC +#set_property -dict {LOC F13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[19]}] ;# J9.F19 HA19_P +#set_property -dict {LOC E13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[19]}] ;# J9.F20 HA19_N +#set_property -dict {LOC K16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[20]}] ;# J9.E18 HA20_P +#set_property -dict {LOC K15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[20]}] ;# J9.E19 HA20_N +#set_property -dict {LOC C14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[21]}] ;# J9.K19 HA21_P +#set_property -dict {LOC B14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[21]}] ;# J9.K20 HA21_N +#set_property -dict {LOC R15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[22]}] ;# J9.J21 HA22_P +#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[22]}] ;# J9.J22 HA22_N +#set_property -dict {LOC P13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_p[23]}] ;# J9.K22 HA23_P +#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_ha_n[23]}] ;# J9.K23 HA23_N + +#set_property -dict {LOC H19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[0]}] ;# J9.K25 HB00_P_CC +#set_property -dict {LOC H18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[0]}] ;# J9.K26 HB00_N_CC +#set_property -dict {LOC D18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[1]}] ;# J9.J24 HB01_P +#set_property -dict {LOC C18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[1]}] ;# J9.J25 HB01_N +#set_property -dict {LOC D19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[2]}] ;# J9.F22 HB02_P +#set_property -dict {LOC C19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[2]}] ;# J9.F23 HB02_N +#set_property -dict {LOC B20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[3]}] ;# J9.E21 HB03_P +#set_property -dict {LOC A20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[3]}] ;# J9.E22 HB03_N +#set_property -dict {LOC F18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[4]}] ;# J9.F25 HB04_P +#set_property -dict {LOC F17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[4]}] ;# J9.F26 HB04_N +#set_property -dict {LOC E18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[5]}] ;# J9.E24 HB05_P +#set_property -dict {LOC E17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[5]}] ;# J9.E25 HB05_N +#set_property -dict {LOC J20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[6]}] ;# J9.K28 HB06_P_CC +#set_property -dict {LOC J19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[6]}] ;# J9.K29 HB06_N_CC +#set_property -dict {LOC F20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[7]}] ;# J9.J27 HB07_P +#set_property -dict {LOC F19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[7]}] ;# J9.J28 HB07_N +#set_property -dict {LOC J21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[8]}] ;# J9.F28 HB08_P +#set_property -dict {LOC H21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[8]}] ;# J9.F29 HB08_N +#set_property -dict {LOC G20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[9]}] ;# J9.E27 HB09_P +#set_property -dict {LOC G19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[9]}] ;# J9.E28 HB09_N +#set_property -dict {LOC P19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[10]}] ;# J9.K31 HB10_P +#set_property -dict {LOC N19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[10]}] ;# J9.K32 HB10_N +#set_property -dict {LOC L17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[11]}] ;# J9.J30 HB11_P +#set_property -dict {LOC K17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[11]}] ;# J9.J31 HB11_N +#set_property -dict {LOC L19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[12]}] ;# J9.F31 HB12_P +#set_property -dict {LOC L18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[12]}] ;# J9.F32 HB12_N +#set_property -dict {LOC N17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[13]}] ;# J9.E30 HB13_P +#set_property -dict {LOC M17 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[13]}] ;# J9.E31 HB13_N +#set_property -dict {LOC N21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[14]}] ;# J9.K34 HB14_P +#set_property -dict {LOC M21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[14]}] ;# J9.K35 HB14_N +#set_property -dict {LOC R20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[15]}] ;# J9.J33 HB15_P +#set_property -dict {LOC P20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[15]}] ;# J9.J34 HB15_N +#set_property -dict {LOC L20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[16]}] ;# J9.F34 HB16_P +#set_property -dict {LOC K20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[16]}] ;# J9.F35 HB16_N +#set_property -dict {LOC K18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[17]}] ;# J9.K37 HB17_P_CC +#set_property -dict {LOC J18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[17]}] ;# J9.K38 HB17_N_CC +#set_property -dict {LOC C21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[18]}] ;# J9.J36 HB18_P +#set_property -dict {LOC B21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[18]}] ;# J9.J37 HB18_N +#set_property -dict {LOC E21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[19]}] ;# J9.E33 HB19_P +#set_property -dict {LOC E20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[19]}] ;# J9.E34 HB19_N +#set_property -dict {LOC B19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[20]}] ;# J9.F37 HB20_P +#set_property -dict {LOC A19 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[20]}] ;# J9.F38 HB20_N +#set_property -dict {LOC D21 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_p[21]}] ;# J9.E36 HB21_P +#set_property -dict {LOC D20 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hb_n[21]}] ;# J9.E37 HB21_N + +#set_property -dict {LOC AW14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_p}] ;# J9.H4 CLK0_M2C_P +#set_property -dict {LOC AW13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk0_m2c_n}] ;# J9.H5 CLK0_M2C_N +#set_property -dict {LOC AV18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk1_m2c_p}] ;# J9.G2 CLK1_M2C_P +#set_property -dict {LOC AW18 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_clk1_m2c_n}] ;# J9.G3 CLK1_M2C_N + +#set_property -dict {LOC G25 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_user_def0_p}] ;# J9.L32 USER_DEF0_P +#set_property -dict {LOC G24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_user_def0_n}] ;# J9.L33 USER_DEF0_N +#set_property -dict {LOC F24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_p}] ;# J9.L24 REFCLK_M2C_P +#set_property -dict {LOC F23 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_refclk_m2c_n}] ;# J9.L25 REFCLK_M2C_N +#set_property -dict {LOC E23 IOSTANDARD LVDS } [get_ports {fmc_sync_c2m_p}] ;# J9.L16 SYNC_C2M_P +#set_property -dict {LOC E22 IOSTANDARD LVDS } [get_ports {fmc_sync_c2m_n}] ;# J9.L17 SYNC_C2M_N +#set_property -dict {LOC J24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_sync_m2c_p}] ;# J9.L28 SYNC_M2C_P +#set_property -dict {LOC H24 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_sync_m2c_n}] ;# J9.L29 SYNC_M2C_N + +#set_property -dict {LOC AV23 IOSTANDARD LVCMOS18} [get_ports {fmc_pg_m2c}] ;# J9.F1 PG_M2C +#set_property -dict {LOC AW23 IOSTANDARD LVCMOS18} [get_ports {fmc_prsnt_m2c_l}] ;# J9.H2 PRSNT_M2C_L +#set_property -dict {LOC BC23 IOSTANDARD LVCMOS18} [get_ports {fmc_hspc_prsnt_m2c_l}] ;# J9.Z1 HSPC_PRSNT_M2C_L + +#set_property -dict {LOC Y7 } [get_ports {fmc_dp_c2m_p[0]}] ;# MGTYTXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C2 DP0_C2M_P +#set_property -dict {LOC Y6 } [get_ports {fmc_dp_c2m_n[0]}] ;# MGTYTXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C3 DP0_C2M_N +#set_property -dict {LOC Y2 } [get_ports {fmc_dp_m2c_p[0]}] ;# MGTYRXP1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C6 DP0_M2C_P +#set_property -dict {LOC Y1 } [get_ports {fmc_dp_m2c_n[0]}] ;# MGTYRXN1_229 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10 from J9.C7 DP0_M2C_N +#set_property -dict {LOC V7 } [get_ports {fmc_dp_c2m_p[1]}] ;# MGTYTXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A22 DP1_C2M_P +#set_property -dict {LOC V6 } [get_ports {fmc_dp_c2m_n[1]}] ;# MGTYTXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A23 DP1_C2M_N +#set_property -dict {LOC V2 } [get_ports {fmc_dp_m2c_p[1]}] ;# MGTYRXP3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A2 DP1_M2C_P +#set_property -dict {LOC V1 } [get_ports {fmc_dp_m2c_n[1]}] ;# MGTYRXN3_229 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10 from J9.A3 DP1_M2C_N +#set_property -dict {LOC W9 } [get_ports {fmc_dp_c2m_p[2]}] ;# MGTYTXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A26 DP2_C2M_P +#set_property -dict {LOC W8 } [get_ports {fmc_dp_c2m_n[2]}] ;# MGTYTXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A27 DP2_C2M_N +#set_property -dict {LOC W4 } [get_ports {fmc_dp_m2c_p[2]}] ;# MGTYRXP2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A6 DP2_M2C_P +#set_property -dict {LOC W3 } [get_ports {fmc_dp_m2c_n[2]}] ;# MGTYRXN2_229 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10 from J9.A7 DP2_M2C_N +#set_property -dict {LOC AA9 } [get_ports {fmc_dp_c2m_p[3]}] ;# MGTYTXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A30 DP3_C2M_P +#set_property -dict {LOC AA8 } [get_ports {fmc_dp_c2m_n[3]}] ;# MGTYTXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A31 DP3_C2M_N +#set_property -dict {LOC AA4 } [get_ports {fmc_dp_m2c_p[3]}] ;# MGTYRXP0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A10 DP3_M2C_P +#set_property -dict {LOC AA3 } [get_ports {fmc_dp_m2c_n[3]}] ;# MGTYRXN0_229 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10 from J9.A11 DP3_M2C_N +#set_property -dict {LOC Y11 } [get_ports fmc_mgt_refclk_0_0_p] ;# MGTREFCLK0P_229 from J9.D4 GBTCLK0_M2C_P +#set_property -dict {LOC Y10 } [get_ports fmc_mgt_refclk_0_0_n] ;# MGTREFCLK0N_229 from J9.D5 GBTCLK0_M2C_N +#set_property -dict {LOC V11 } [get_ports fmc_mgt_refclk_0_1_p] ;# MGTREFCLK1P_229 from U27.14 OUT3 +#set_property -dict {LOC V10 } [get_ports fmc_mgt_refclk_0_1_n] ;# MGTREFCLK1N_229 from U27.13 OUT3B + +# reference clock +#create_clock -period 6.400 -name fmc_mgt_refclk_0_0 [get_ports fmc_mgt_refclk_0_0_p] +#create_clock -period 6.400 -name fmc_mgt_refclk_0_1 [get_ports fmc_mgt_refclk_0_1_p] + +#set_property -dict {LOC AC9 } [get_ports {fmc_dp_c2m_p[4]}] ;# MGTYTXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A34 DP4_C2M_P +#set_property -dict {LOC AC8 } [get_ports {fmc_dp_c2m_n[4]}] ;# MGTYTXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A35 DP4_C2M_N +#set_property -dict {LOC AC4 } [get_ports {fmc_dp_m2c_p[4]}] ;# MGTYRXP2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A14 DP4_M2C_P +#set_property -dict {LOC AC3 } [get_ports {fmc_dp_m2c_n[4]}] ;# MGTYRXN2_228 GTYE4_CHANNEL_X1Y38 / GTYE4_COMMON_X1Y9 from J22.A15 DP4_M2C_N +#set_property -dict {LOC AE9 } [get_ports {fmc_dp_c2m_p[5]}] ;# MGTYTXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A38 DP5_C2M_P +#set_property -dict {LOC AE8 } [get_ports {fmc_dp_c2m_n[5]}] ;# MGTYTXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A39 DP5_C2M_N +#set_property -dict {LOC AE4 } [get_ports {fmc_dp_m2c_p[5]}] ;# MGTYRXP0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A18 DP5_M2C_P +#set_property -dict {LOC AE3 } [get_ports {fmc_dp_m2c_n[5]}] ;# MGTYRXN0_228 GTYE4_CHANNEL_X1Y36 / GTYE4_COMMON_X1Y9 from J22.A19 DP5_M2C_N +#set_property -dict {LOC AD7 } [get_ports {fmc_dp_c2m_p[6]}] ;# MGTYTXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B36 DP6_C2M_P +#set_property -dict {LOC AD6 } [get_ports {fmc_dp_c2m_n[6]}] ;# MGTYTXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B37 DP6_C2M_N +#set_property -dict {LOC AD2 } [get_ports {fmc_dp_m2c_p[6]}] ;# MGTYRXP1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B16 DP6_M2C_P +#set_property -dict {LOC AD1 } [get_ports {fmc_dp_m2c_n[6]}] ;# MGTYRXN1_228 GTYE4_CHANNEL_X1Y37 / GTYE4_COMMON_X1Y9 from J22.B17 DP6_M2C_N +#set_property -dict {LOC AB7 } [get_ports {fmc_dp_c2m_p[7]}] ;# MGTYTXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B32 DP7_C2M_P +#set_property -dict {LOC AB6 } [get_ports {fmc_dp_c2m_n[7]}] ;# MGTYTXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B33 DP7_C2M_N +#set_property -dict {LOC AB2 } [get_ports {fmc_dp_m2c_p[7]}] ;# MGTYRXP3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B12 DP7_M2C_P +#set_property -dict {LOC AB1 } [get_ports {fmc_dp_m2c_n[7]}] ;# MGTYRXN3_228 GTYE4_CHANNEL_X1Y39 / GTYE4_COMMON_X1Y9 from J22.B13 DP7_M2C_N +#set_property -dict {LOC AD11} [get_ports fmc_mgt_refclk_1_0_p] ;# MGTREFCLK0P_228 from J9.B20 GBTCLK1_M2C_P +#set_property -dict {LOC AD10} [get_ports fmc_mgt_refclk_1_0_n] ;# MGTREFCLK0N_228 from J9.B21 GBTCLK1_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmc_mgt_refclk_1_0 [get_ports fmc_mgt_refclk_1_0_p] + +#set_property -dict {LOC L9 } [get_ports {fmc_dp_c2m_p[8]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B28 DP8_C2M_P +#set_property -dict {LOC L8 } [get_ports {fmc_dp_c2m_n[8]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B29 DP8_C2M_N +#set_property -dict {LOC L4 } [get_ports {fmc_dp_m2c_p[8]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B8 DP8_M2C_P +#set_property -dict {LOC L3 } [get_ports {fmc_dp_m2c_n[8]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 from J22.B9 DP8_M2C_N +#set_property -dict {LOC K7 } [get_ports {fmc_dp_c2m_p[9]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B24 DP9_C2M_P +#set_property -dict {LOC K6 } [get_ports {fmc_dp_c2m_n[9]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B25 DP9_C2M_N +#set_property -dict {LOC K2 } [get_ports {fmc_dp_m2c_p[9]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B4 DP9_M2C_P +#set_property -dict {LOC K1 } [get_ports {fmc_dp_m2c_n[9]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 from J22.B5 DP9_M2C_N +#set_property -dict {LOC M7 } [get_ports {fmc_dp_c2m_p[10]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Z24 DP10_C2M_P +#set_property -dict {LOC M6 } [get_ports {fmc_dp_c2m_n[10]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Z25 DP10_C2M_N +#set_property -dict {LOC M2 } [get_ports {fmc_dp_m2c_p[10]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Y10 DP10_M2C_P +#set_property -dict {LOC M1 } [get_ports {fmc_dp_m2c_n[10]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 from J22.Y11 DP10_M2C_N +#set_property -dict {LOC N9 } [get_ports {fmc_dp_c2m_p[11]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Y26 DP11_C2M_P +#set_property -dict {LOC N8 } [get_ports {fmc_dp_c2m_n[11]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Y27 DP11_C2M_N +#set_property -dict {LOC N4 } [get_ports {fmc_dp_m2c_p[11]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Z12 DP11_M2C_P +#set_property -dict {LOC N3 } [get_ports {fmc_dp_m2c_n[11]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 from J22.Z13 DP11_M2C_N +#set_property -dict {LOC M11 } [get_ports fmc_mgt_refclk_2_0_p] ;# MGTREFCLK0P_231 from J9.L12 GBTCLK2_M2C_P +#set_property -dict {LOC M10 } [get_ports fmc_mgt_refclk_2_0_n] ;# MGTREFCLK0N_231 from J9.L13 GBTCLK2_M2C_N +#set_property -dict {LOC K11 } [get_ports fmc_mgt_refclk_2_1_p] ;# MGTREFCLK1P_231 from U27.17 OUT2 +#set_property -dict {LOC K10 } [get_ports fmc_mgt_refclk_2_1_n] ;# MGTREFCLK1N_231 from U27.16 OUT2B + +# reference clock +#create_clock -period 6.400 -name fmc_mgt_refclk_2_0 [get_ports fmc_mgt_refclk_2_0_p] +#create_clock -period 6.400 -name fmc_mgt_refclk_2_1 [get_ports fmc_mgt_refclk_2_1_p] + +#set_property -dict {LOC P7 } [get_ports {fmc_dp_c2m_p[12]}] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Z28 DP12_C2M_P +#set_property -dict {LOC P6 } [get_ports {fmc_dp_c2m_n[12]}] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Z29 DP12_C2M_N +#set_property -dict {LOC P2 } [get_ports {fmc_dp_m2c_p[12]}] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Y14 DP12_M2C_P +#set_property -dict {LOC P1 } [get_ports {fmc_dp_m2c_n[12]}] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 from J22.Y15 DP12_M2C_N +#set_property -dict {LOC R9 } [get_ports {fmc_dp_c2m_p[13]}] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Y30 DP13_C2M_P +#set_property -dict {LOC R8 } [get_ports {fmc_dp_c2m_n[13]}] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Y31 DP13_C2M_N +#set_property -dict {LOC R4 } [get_ports {fmc_dp_m2c_p[13]}] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Z16 DP13_M2C_P +#set_property -dict {LOC R3 } [get_ports {fmc_dp_m2c_n[13]}] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11 from J22.Z17 DP13_M2C_N +#set_property -dict {LOC T7 } [get_ports {fmc_dp_c2m_p[14]}] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.M18 DP14_C2M_P +#set_property -dict {LOC T6 } [get_ports {fmc_dp_c2m_n[14]}] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.M19 DP14_C2M_N +#set_property -dict {LOC T2 } [get_ports {fmc_dp_m2c_p[14]}] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.Y18 DP14_M2C_P +#set_property -dict {LOC T1 } [get_ports {fmc_dp_m2c_n[14]}] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11 from J22.Y19 DP14_M2C_N +#set_property -dict {LOC U9 } [get_ports {fmc_dp_c2m_p[15]}] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.M22 DP15_C2M_P +#set_property -dict {LOC U8 } [get_ports {fmc_dp_c2m_n[15]}] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.M23 DP15_C2M_N +#set_property -dict {LOC U4 } [get_ports {fmc_dp_m2c_p[15]}] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.Y22 DP15_M2C_P +#set_property -dict {LOC U3 } [get_ports {fmc_dp_m2c_n[15]}] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11 from J22.Y23 DP15_M2C_N +#set_property -dict {LOC T11 } [get_ports fmc_mgt_refclk_3_0_p] ;# MGTREFCLK0P_230 from J9.L8 GBTCLK3_M2C_P +#set_property -dict {LOC T10 } [get_ports fmc_mgt_refclk_3_0_n] ;# MGTREFCLK0N_230 from J9.L9 GBTCLK3_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmc_mgt_refclk_3_0 [get_ports fmc_mgt_refclk_3_0_p] + +#set_property -dict {LOC AF7 } [get_ports {fmc_dp_c2m_p[16]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.M26 DP16_C2M_P +#set_property -dict {LOC AF6 } [get_ports {fmc_dp_c2m_n[16]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.M27 DP16_C2M_N +#set_property -dict {LOC AF2 } [get_ports {fmc_dp_m2c_p[16]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.Z32 DP16_M2C_P +#set_property -dict {LOC AF1 } [get_ports {fmc_dp_m2c_n[16]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 from J22.Z33 DP16_M2C_N +#set_property -dict {LOC AG9 } [get_ports {fmc_dp_c2m_p[17]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.M30 DP17_C2M_P +#set_property -dict {LOC AG8 } [get_ports {fmc_dp_c2m_n[17]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.M31 DP17_C2M_N +#set_property -dict {LOC AG4 } [get_ports {fmc_dp_m2c_p[17]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.Y34 DP17_M2C_P +#set_property -dict {LOC AG3 } [get_ports {fmc_dp_m2c_n[17]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 from J22.Y35 DP17_M2C_N +#set_property -dict {LOC AH7 } [get_ports {fmc_dp_c2m_p[18]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.M34 DP18_C2M_P +#set_property -dict {LOC AH6 } [get_ports {fmc_dp_c2m_n[18]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.M35 DP18_C2M_N +#set_property -dict {LOC AH2 } [get_ports {fmc_dp_m2c_p[18]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.Z36 DP18_M2C_P +#set_property -dict {LOC AH1 } [get_ports {fmc_dp_m2c_n[18]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 from J22.Z37 DP18_M2C_N +#set_property -dict {LOC AJ9 } [get_ports {fmc_dp_c2m_p[19]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.M38 DP19_C2M_P +#set_property -dict {LOC AJ8 } [get_ports {fmc_dp_c2m_n[19]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.M39 DP19_C2M_N +#set_property -dict {LOC AJ4 } [get_ports {fmc_dp_m2c_p[19]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.Y38 DP19_M2C_P +#set_property -dict {LOC AJ3 } [get_ports {fmc_dp_m2c_n[19]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 from J22.Y39 DP19_M2C_N +#set_property -dict {LOC AH11} [get_ports fmc_mgt_refclk_4_0_p] ;# MGTREFCLK0P_227 from J9.L4 GBTCLK4_M2C_P +#set_property -dict {LOC AH10} [get_ports fmc_mgt_refclk_4_0_n] ;# MGTREFCLK0N_227 from J9.L5 GBTCLK4_M2C_N +#set_property -dict {LOC AF11} [get_ports fmc_mgt_refclk_4_1_p] ;# MGTREFCLK1P_227 from U27.11 OUT4 +#set_property -dict {LOC AF10} [get_ports fmc_mgt_refclk_4_1_n] ;# MGTREFCLK1N_227 from U27.12 OUT4B + +# reference clock +#create_clock -period 6.400 -name fmc_mgt_refclk_4_0 [get_ports fmc_mgt_refclk_4_0_p] +#create_clock -period 6.400 -name fmc_mgt_refclk_4_1 [get_ports fmc_mgt_refclk_4_1_p] + +#set_property -dict {LOC J9 } [get_ports {fmc_dp_c2m_p[20]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.Z8 DP20_C2M_P +#set_property -dict {LOC J8 } [get_ports {fmc_dp_c2m_n[20]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.Z9 DP20_C2M_N +#set_property -dict {LOC J4 } [get_ports {fmc_dp_m2c_p[20]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.M14 DP20_M2C_P +#set_property -dict {LOC J3 } [get_ports {fmc_dp_m2c_n[20]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 from J22.M15 DP20_M2C_N +#set_property -dict {LOC H7 } [get_ports {fmc_dp_c2m_p[21]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.Y6 DP21_C2M_P +#set_property -dict {LOC H6 } [get_ports {fmc_dp_c2m_n[21]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.Y7 DP21_C2M_N +#set_property -dict {LOC H2 } [get_ports {fmc_dp_m2c_p[21]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.M10 DP21_M2C_P +#set_property -dict {LOC H1 } [get_ports {fmc_dp_m2c_n[21]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 from J22.M11 DP21_M2C_N +#set_property -dict {LOC G9 } [get_ports {fmc_dp_c2m_p[22]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.Z4 DP22_C2M_P +#set_property -dict {LOC G8 } [get_ports {fmc_dp_c2m_n[22]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.Z5 DP22_C2M_N +#set_property -dict {LOC G4 } [get_ports {fmc_dp_m2c_p[22]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.M6 DP22_M2C_P +#set_property -dict {LOC G3 } [get_ports {fmc_dp_m2c_n[22]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 from J22.M7 DP22_M2C_N +#set_property -dict {LOC F7 } [get_ports {fmc_dp_c2m_p[23]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.Y2 DP23_C2M_P +#set_property -dict {LOC F6 } [get_ports {fmc_dp_c2m_n[23]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.Y3 DP23_C2M_N +#set_property -dict {LOC F2 } [get_ports {fmc_dp_m2c_p[23]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.M2 DP23_M2C_P +#set_property -dict {LOC F1 } [get_ports {fmc_dp_m2c_n[23]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 from J22.M3 DP23_M2C_N +#set_property -dict {LOC H11 } [get_ports fmc_mgt_refclk_5_0_p] ;# MGTREFCLK0P_232 from J9.Z20 GBTCLK5_M2C_P +#set_property -dict {LOC H10 } [get_ports fmc_mgt_refclk_5_0_n] ;# MGTREFCLK0N_232 from J9.Z21 GBTCLK5_M2C_N + +# reference clock +#create_clock -period 6.400 -name fmc_mgt_refclk_5_0 [get_ports fmc_mgt_refclk_5_0_p] diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_vu13p/Makefile b/src/eth/example/HTG9200/fpga/fpga_10g_vu13p/Makefile new file mode 100644 index 0000000..baf9e78 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_10g_vu13p/Makefile @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu13p-fhgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/eth/example/HTG9200/fpga/fpga_10g_vu9p/Makefile b/src/eth/example/HTG9200/fpga/fpga_10g_vu9p/Makefile new file mode 100644 index 0000000..da75cdd --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_10g_vu9p/Makefile @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/eth/example/HTG9200/fpga/fpga_vu13p/Makefile b/src/eth/example/HTG9200/fpga/fpga_vu13p/Makefile new file mode 100644 index 0000000..b9e110f --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_vu13p/Makefile @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu13p-fhgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/eth/example/HTG9200/fpga/fpga_vu9p/Makefile b/src/eth/example/HTG9200/fpga/fpga_vu9p/Makefile new file mode 100644 index 0000000..8949799 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/fpga_vu9p/Makefile @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xcvu9p-flgb2104-2-e +FPGA_TOP = fpga +FPGA_ARCH = virtexuplus + +RTL_DIR = ../rtl +LIB_DIR = ../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +# Files for synthesis +SYN_FILES = $(RTL_DIR)/fpga.sv +SYN_FILES += $(RTL_DIR)/fpga_core.sv +SYN_FILES += $(RTL_DIR)/../pll/si5341_i2c_init.sv +SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl +XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl + +# IP +IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl + +# Configuration +# CONFIG_TCL_FILES = ./config.tcl + +include ../common/vivado.mk + +program: $(FPGA_TOP).bit + echo "open_hw" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit + echo "write_cfgmem -force -format mcs -size 128 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm + echo "open_hw" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s25fl512s-spi-x1_x2_x4_x8}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/src/eth/example/HTG9200/fpga/lib/taxi b/src/eth/example/HTG9200/fpga/lib/taxi new file mode 120000 index 0000000..477cbaa --- /dev/null +++ b/src/eth/example/HTG9200/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../../../ \ No newline at end of file diff --git a/src/eth/example/HTG9200/fpga/pll/HTG9200_161-9k2_161-Registers.txt b/src/eth/example/HTG9200/fpga/pll/HTG9200_161-9k2_161-Registers.txt new file mode 100644 index 0000000..a999c1d --- /dev/null +++ b/src/eth/example/HTG9200/fpga/pll/HTG9200_161-9k2_161-Registers.txt @@ -0,0 +1,412 @@ +# Si534x/7x/8x/9x Registers Script +# +# Part: Si5341 +# Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_25g\pll\HTG9200_161-9k2_161.slabtimeproj +# Design ID: 9k2_161 +# Includes Pre/Post Download Control Register Writes: Yes +# Die Revision: B1 +# Creator: ClockBuilder Pro v4.1 [2021-09-22] +# Created On: 2023-07-19 01:51:06 GMT-07:00 +Address,Data +# +# Start configuration preamble +0x0B24,0xC0 +0x0B25,0x00 +# Rev D stuck divider fix +0x0502,0x01 +0x0505,0x03 +0x0957,0x17 +0x0B4E,0x1A +# End configuration preamble +# +# Delay 300 msec +# Delay is worst case time for device to complete any calibration +# that is running due to device state change previous to this script +# being processed. +# +# Start configuration registers +0x0006,0x00 +0x0007,0x00 +0x0008,0x00 +0x000B,0x74 +0x0017,0xD0 +0x0018,0xFF +0x0021,0x0B +0x0022,0x00 +0x002B,0x02 +0x002C,0x33 +0x002D,0x05 +0x002E,0xAE +0x002F,0x00 +0x0030,0xAE +0x0031,0x00 +0x0032,0x00 +0x0033,0x00 +0x0034,0x00 +0x0035,0x00 +0x0036,0xAE +0x0037,0x00 +0x0038,0xAE +0x0039,0x00 +0x003A,0x00 +0x003B,0x00 +0x003C,0x00 +0x003D,0x00 +0x0041,0x07 +0x0042,0x07 +0x0043,0x00 +0x0044,0x00 +0x009E,0x00 +0x0102,0x01 +0x0108,0x06 +0x0109,0x09 +0x010A,0x3B +0x010B,0x28 +0x010D,0x06 +0x010E,0x09 +0x010F,0x3B +0x0110,0x28 +0x0112,0x02 +0x0113,0x09 +0x0114,0x3B +0x0115,0x29 +0x0117,0x06 +0x0118,0x09 +0x0119,0x3B +0x011A,0x28 +0x011C,0x06 +0x011D,0x09 +0x011E,0x3B +0x011F,0x28 +0x0121,0x06 +0x0122,0x09 +0x0123,0x3B +0x0124,0x28 +0x0126,0x06 +0x0127,0x09 +0x0128,0x3B +0x0129,0x28 +0x012B,0x06 +0x012C,0x09 +0x012D,0x3B +0x012E,0x28 +0x0130,0x06 +0x0131,0x09 +0x0132,0x3B +0x0133,0x28 +0x013A,0x06 +0x013B,0x09 +0x013C,0x3B +0x013D,0x28 +0x013F,0x00 +0x0140,0x00 +0x0141,0x40 +0x0206,0x00 +0x0208,0x02 +0x0209,0x00 +0x020A,0x00 +0x020B,0x00 +0x020C,0x00 +0x020D,0x00 +0x020E,0x01 +0x020F,0x00 +0x0210,0x00 +0x0211,0x00 +0x0212,0x02 +0x0213,0x00 +0x0214,0x00 +0x0215,0x00 +0x0216,0x00 +0x0217,0x00 +0x0218,0x01 +0x0219,0x00 +0x021A,0x00 +0x021B,0x00 +0x021C,0x00 +0x021D,0x00 +0x021E,0x00 +0x021F,0x00 +0x0220,0x00 +0x0221,0x00 +0x0222,0x00 +0x0223,0x00 +0x0224,0x00 +0x0225,0x00 +0x0226,0x00 +0x0227,0x00 +0x0228,0x00 +0x0229,0x00 +0x022A,0x00 +0x022B,0x00 +0x022C,0x00 +0x022D,0x00 +0x022E,0x00 +0x022F,0x00 +0x0235,0x00 +0x0236,0x00 +0x0237,0x00 +0x0238,0x90 +0x0239,0x54 +0x023A,0x00 +0x023B,0x00 +0x023C,0x00 +0x023D,0x00 +0x023E,0x80 +0x024A,0x00 +0x024B,0x00 +0x024C,0x00 +0x024D,0x00 +0x024E,0x00 +0x024F,0x00 +0x0250,0x03 +0x0251,0x00 +0x0252,0x00 +0x0253,0x00 +0x0254,0x00 +0x0255,0x00 +0x0256,0x00 +0x0257,0x00 +0x0258,0x00 +0x0259,0x00 +0x025A,0x00 +0x025B,0x00 +0x025C,0x00 +0x025D,0x00 +0x025E,0x00 +0x025F,0x00 +0x0260,0x00 +0x0261,0x00 +0x0262,0x00 +0x0263,0x00 +0x0264,0x00 +0x0268,0x00 +0x0269,0x00 +0x026A,0x00 +0x026B,0x39 +0x026C,0x6B +0x026D,0x32 +0x026E,0x5F +0x026F,0x31 +0x0270,0x36 +0x0271,0x31 +0x0272,0x00 +0x0302,0x00 +0x0303,0x00 +0x0304,0x00 +0x0305,0x80 +0x0306,0x14 +0x0307,0x00 +0x0308,0x00 +0x0309,0x00 +0x030A,0x00 +0x030B,0x80 +0x030C,0x00 +0x030D,0x00 +0x030E,0x00 +0x030F,0x10 +0x0310,0x42 +0x0311,0x08 +0x0312,0x00 +0x0313,0x00 +0x0314,0x00 +0x0315,0x00 +0x0316,0x80 +0x0317,0x00 +0x0318,0x00 +0x0319,0x00 +0x031A,0x00 +0x031B,0x00 +0x031C,0x00 +0x031D,0x00 +0x031E,0x00 +0x031F,0x00 +0x0320,0x00 +0x0321,0x00 +0x0322,0x00 +0x0323,0x00 +0x0324,0x00 +0x0325,0x00 +0x0326,0x00 +0x0327,0x00 +0x0328,0x00 +0x0329,0x00 +0x032A,0x00 +0x032B,0x00 +0x032C,0x00 +0x032D,0x00 +0x032E,0x00 +0x032F,0x00 +0x0330,0x00 +0x0331,0x00 +0x0332,0x00 +0x0333,0x00 +0x0334,0x00 +0x0335,0x00 +0x0336,0x00 +0x0337,0x00 +0x0338,0x00 +0x0339,0x1F +0x033B,0x00 +0x033C,0x00 +0x033D,0x00 +0x033E,0x00 +0x033F,0x00 +0x0340,0x00 +0x0341,0x00 +0x0342,0x00 +0x0343,0x00 +0x0344,0x00 +0x0345,0x00 +0x0346,0x00 +0x0347,0x00 +0x0348,0x00 +0x0349,0x00 +0x034A,0x00 +0x034B,0x00 +0x034C,0x00 +0x034D,0x00 +0x034E,0x00 +0x034F,0x00 +0x0350,0x00 +0x0351,0x00 +0x0352,0x00 +0x0353,0x00 +0x0354,0x00 +0x0355,0x00 +0x0356,0x00 +0x0357,0x00 +0x0358,0x00 +0x0359,0x00 +0x035A,0x00 +0x035B,0x00 +0x035C,0x00 +0x035D,0x00 +0x035E,0x00 +0x035F,0x00 +0x0360,0x00 +0x0361,0x00 +0x0362,0x00 +0x0802,0x00 +0x0803,0x00 +0x0804,0x00 +0x0805,0x00 +0x0806,0x00 +0x0807,0x00 +0x0808,0x00 +0x0809,0x00 +0x080A,0x00 +0x080B,0x00 +0x080C,0x00 +0x080D,0x00 +0x080E,0x00 +0x080F,0x00 +0x0810,0x00 +0x0811,0x00 +0x0812,0x00 +0x0813,0x00 +0x0814,0x00 +0x0815,0x00 +0x0816,0x00 +0x0817,0x00 +0x0818,0x00 +0x0819,0x00 +0x081A,0x00 +0x081B,0x00 +0x081C,0x00 +0x081D,0x00 +0x081E,0x00 +0x081F,0x00 +0x0820,0x00 +0x0821,0x00 +0x0822,0x00 +0x0823,0x00 +0x0824,0x00 +0x0825,0x00 +0x0826,0x00 +0x0827,0x00 +0x0828,0x00 +0x0829,0x00 +0x082A,0x00 +0x082B,0x00 +0x082C,0x00 +0x082D,0x00 +0x082E,0x00 +0x082F,0x00 +0x0830,0x00 +0x0831,0x00 +0x0832,0x00 +0x0833,0x00 +0x0834,0x00 +0x0835,0x00 +0x0836,0x00 +0x0837,0x00 +0x0838,0x00 +0x0839,0x00 +0x083A,0x00 +0x083B,0x00 +0x083C,0x00 +0x083D,0x00 +0x083E,0x00 +0x083F,0x00 +0x0840,0x00 +0x0841,0x00 +0x0842,0x00 +0x0843,0x00 +0x0844,0x00 +0x0845,0x00 +0x0846,0x00 +0x0847,0x00 +0x0848,0x00 +0x0849,0x00 +0x084A,0x00 +0x084B,0x00 +0x084C,0x00 +0x084D,0x00 +0x084E,0x00 +0x084F,0x00 +0x0850,0x00 +0x0851,0x00 +0x0852,0x00 +0x0853,0x00 +0x0854,0x00 +0x0855,0x00 +0x0856,0x00 +0x0857,0x00 +0x0858,0x00 +0x0859,0x00 +0x085A,0x00 +0x085B,0x00 +0x085C,0x00 +0x085D,0x00 +0x085E,0x00 +0x085F,0x00 +0x0860,0x00 +0x0861,0x00 +0x090E,0x00 +0x091C,0x04 +0x0943,0x00 +0x0949,0x03 +0x094A,0x30 +0x094E,0x49 +0x094F,0x02 +0x095E,0x00 +0x0A02,0x00 +0x0A03,0x03 +0x0A04,0x01 +0x0A05,0x03 +0x0A14,0x00 +0x0A1A,0x00 +0x0A20,0x00 +0x0A26,0x00 +0x0A2C,0x00 +0x0B44,0x0F +0x0B4A,0x1C +0x0B57,0xA5 +0x0B58,0x00 +# End configuration registers +# +# Start configuration postamble +0x001C,0x01 +0x0B24,0xC3 +0x0B25,0x02 +# End configuration postamble diff --git a/src/eth/example/HTG9200/fpga/pll/HTG9200_161-9k2_161.slabtimeproj b/src/eth/example/HTG9200/fpga/pll/HTG9200_161-9k2_161.slabtimeproj new file mode 100644 index 0000000..dcb40c4 Binary files /dev/null and b/src/eth/example/HTG9200/fpga/pll/HTG9200_161-9k2_161.slabtimeproj differ diff --git a/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init.py b/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init.py new file mode 100755 index 0000000..2a1aa96 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init.py @@ -0,0 +1,644 @@ +#!/usr/bin/env python +""" +Generates an I2C init module for multiple chips +""" + +from jinja2 import Template + + +def si5341_cmds(regs, dev_addr=0x77): + cur_page = None + cur_addr = None + + cmds = [] + + print(f"Reading register list file '{regs}'...") + + with open(regs, "r") as f: + for line in f: + line = line.strip() + if not line or line == "Address,Data": + continue + if line[0] == '#': + cmds.append(f"// {line[1:].strip()}") + + if line.startswith("# Delay"): + cmds.append("cmd_delay(10); // delay 300 ms") + cur_addr = None + + continue + + d = line.split(",") + addr = int(d[0], 0) + page = (addr >> 8) & 0xff + data = int(d[1], 0) + + if page != cur_page: + cmds.append(f"cmd_start(7'h{dev_addr:02x});") + cmds.append("cmd_wr(8'h01);") + cmds.append(f"cmd_wr(8'h{page:02x}); // set page {page:#04x}") + cur_page = page + cur_addr = None + + if addr != cur_addr: + cmds.append(f"cmd_start(7'h{dev_addr:02x});") + cmds.append(f"cmd_wr(8'h{addr & 0xff:02x});") + cur_addr = addr + + cmds.append(f"cmd_wr(8'h{data:02x}); // write {data:#04x} to {addr:#06x}") + cur_addr += 1 + + return cmds + + +def mux_cmds(val, dev_addr): + cmds = [] + cmds.append(f"cmd_start(7'h{dev_addr:02x});") + cmds.append(f"cmd_wr(8'h{val:02x});") + cmds.append("cmd_stop(); // I2C stop") + return cmds + + +def main(): + cmds = [] + + cmds.append("// Initial delay") + cmds.append("cmd_delay(6); // delay 30 ms") + + # Si5341 on HTG 9200 + cmds.append("// Set muxes to select U48 Si5341 on HTG-9200") + cmds.extend(mux_cmds(0x00, 0x70)) + cmds.extend(mux_cmds(0x04, 0x71)) + + cmds.extend(si5341_cmds("HTG9200_161-9k2_161-Registers.txt", 0x77)) + generate(cmds) + + +def generate(cmds=None, name=None, output=None): + if cmds is None: + raise Exception("Command list is required") + + if name is None: + name = "si5341_i2c_init" + + if output is None: + output = name + ".sv" + + print(f"Generating Si5341 I2C init module {name}...") + + cmds.append("cmd_halt(); // end") + + cmd_str = "" + cmd_count = 0 + + for cmd in cmds: + if cmd.startswith('//'): + cmd_str += f" {cmd}\n" + else: + cmd_str += f" init_data[{cmd_count}] = {cmd}\n" + cmd_count += 1 + + t = Template(u"""// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2015-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * {{name}} + */ +module {{name}} # +( + parameter logic SIM_SPEEDUP = 1'b0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * I2C master interface + */ + taxi_axis_if.src m_axis_cmd, + taxi_axis_if.src m_axis_tx, + + /* + * Status + */ + output wire logic busy, + + /* + * Configuration + */ + input wire logic start +); + +/* + +Generic module for I2C bus initialization. Good for use when multiple devices +on an I2C bus must be initialized on system start without intervention of a +general-purpose processor. + +Copy this file and change init_data and INIT_DATA_LEN as needed. + +This module can be used in two modes: simple device initialization, or multiple +device initialization. In multiple device mode, the same initialization sequence +can be performed on multiple different device addresses. + +To use single device mode, only use the start write to address and write data commands. +The module will generate the I2C commands in sequential order. Terminate the list +with a 0 entry. + +To use the multiple device mode, use the start data and start address block commands +to set up lists of initialization data and device addresses. The module enters +multiple device mode upon seeing a start data block command. The module stores the +offset of the start of the data block and then skips ahead until it reaches a start +address block command. The module will store the offset to the address block and +read the first address in the block. Then it will jump back to the data block +and execute it, substituting the stored address for each current address write +command. Upon reaching the start address block command, the module will read out the +next address and start again at the top of the data block. If the module encounters +a start data block command while looking for an address, then it will store a new data +offset and then look for a start address block command. Terminate the list with a 0 +entry. Normal address commands will operate normally inside a data block. + +Commands: + +00 0000000 : stop +00 0000001 : exit multiple device mode +00 0000011 : start write to current address +00 0001000 : start address block +00 0001001 : start data block +00 001dddd : delay 2**(16+d) cycles +00 1000001 : send I2C stop +01 aaaaaaa : start write to address +1 dddddddd : write 8-bit data + +Examples + +write 0x11223344 to register 0x0004 on device at 0x50 + +01 1010000 start write to 0x50 +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +0 00000000 stop + +write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53 + +00 0001001 start data block +00 0000011 start write to current address +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +00 0001000 start address block +01 1010000 address 0x50 +01 1010001 address 0x51 +01 1010010 address 0x52 +01 1010011 address 0x53 +00 0000001 exit multi-dev mode +00 0000000 stop + +*/ + +// check configuration +if (m_axis_cmd.DATA_W < 12) + $fatal(0, "Command interface width must be at least 12 bits (instance %m)"); + +if (m_axis_tx.DATA_W != 8) + $fatal(0, "Data interface width must be 8 bits (instance %m)"); + +function [8:0] cmd_start(input [6:0] addr); + cmd_start = {2'b01, addr}; +endfunction + +function [8:0] cmd_wr(input [7:0] data); + cmd_wr = {1'b1, data}; +endfunction + +function [8:0] cmd_stop(); + cmd_stop = {2'b00, 7'b1000001}; +endfunction + +function [8:0] cmd_delay(input [3:0] d); + cmd_delay = {2'b00, 3'b001, d}; +endfunction + +function [8:0] cmd_halt(); + cmd_halt = 9'd0; +endfunction + +function [8:0] blk_start_data(); + blk_start_data = {2'b00, 7'b0001001}; +endfunction + +function [8:0] blk_start_addr(); + blk_start_addr = {2'b00, 7'b0001000}; +endfunction + +function [8:0] cmd_start_cur(); + cmd_start_cur = {2'b00, 7'b0000011}; +endfunction + +function [8:0] cmd_exit(); + cmd_exit = {2'b00, 7'b0000001}; +endfunction + +// init_data ROM +localparam INIT_DATA_LEN = {{cmd_count}}; + +reg [8:0] init_data [INIT_DATA_LEN-1:0]; + +initial begin +{{cmd_str-}} +end + +localparam [2:0] + STATE_IDLE = 3'd0, + STATE_RUN = 3'd1, + STATE_TABLE_1 = 3'd2, + STATE_TABLE_2 = 3'd3, + STATE_TABLE_3 = 3'd4; + +logic [2:0] state_reg = STATE_IDLE, state_next; + +localparam AW = $clog2(INIT_DATA_LEN); + +logic [8:0] init_data_reg = '0; + +logic [AW-1:0] address_reg = '0, address_next; +logic [AW-1:0] address_ptr_reg = '0, address_ptr_next; +logic [AW-1:0] data_ptr_reg = '0, data_ptr_next; + +logic [6:0] cur_address_reg = '0, cur_address_next; + +logic [31:0] delay_counter_reg = '0, delay_counter_next; + +logic [6:0] m_axis_cmd_address_reg = '0, m_axis_cmd_address_next; +logic m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next; +logic m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next; +logic m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next; +logic m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next; + +logic [7:0] m_axis_tx_tdata_reg = '0, m_axis_tx_tdata_next; +logic m_axis_tx_tvalid_reg = 1'b0, m_axis_tx_tvalid_next; + +logic start_flag_reg = 1'b0, start_flag_next; + +logic busy_reg = 1'b0; + +assign m_axis_cmd.tdata[6:0] = m_axis_cmd_address_reg; +assign m_axis_cmd.tdata[7] = m_axis_cmd_start_reg; +assign m_axis_cmd.tdata[8] = 1'b0; // read +assign m_axis_cmd.tdata[9] = m_axis_cmd_write_reg; +assign m_axis_cmd.tdata[10] = 1'b0; // write multi +assign m_axis_cmd.tdata[11] = m_axis_cmd_stop_reg; +assign m_axis_cmd.tvalid = m_axis_cmd_valid_reg; +assign m_axis_cmd.tlast = 1'b1; +assign m_axis_cmd.tid = '0; +assign m_axis_cmd.tdest = '0; +assign m_axis_cmd.tuser = '0; + +assign m_axis_tx.tdata = m_axis_tx_tdata_reg; +assign m_axis_tx.tvalid = m_axis_tx_tvalid_reg; +assign m_axis_tx.tlast = 1'b1; +assign m_axis_tx.tid = '0; +assign m_axis_tx.tdest = '0; +assign m_axis_tx.tuser = '0; + +assign busy = busy_reg; + +always_comb begin + state_next = STATE_IDLE; + + address_next = address_reg; + address_ptr_next = address_ptr_reg; + data_ptr_next = data_ptr_reg; + + cur_address_next = cur_address_reg; + + delay_counter_next = delay_counter_reg; + + m_axis_cmd_address_next = m_axis_cmd_address_reg; + m_axis_cmd_start_next = m_axis_cmd_start_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready); + m_axis_cmd_write_next = m_axis_cmd_write_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready); + m_axis_cmd_stop_next = m_axis_cmd_stop_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready); + m_axis_cmd_valid_next = m_axis_cmd_valid_reg && !m_axis_cmd.tready; + + m_axis_tx_tdata_next = m_axis_tx_tdata_reg; + m_axis_tx_tvalid_next = m_axis_tx_tvalid_reg && !m_axis_tx.tready; + + start_flag_next = start_flag_reg; + + if (m_axis_cmd.tvalid || m_axis_tx.tvalid) begin + // wait for output registers to clear + state_next = state_reg; + end else if (delay_counter_reg != 0) begin + // delay + delay_counter_next = delay_counter_reg - 1; + state_next = state_reg; + end else begin + case (state_reg) + STATE_IDLE: begin + // wait for start signal + if (!start_flag_reg && start) begin + address_next = '0; + start_flag_next = 1'b1; + state_next = STATE_RUN; + end else begin + state_next = STATE_IDLE; + end + end + STATE_RUN: begin + // process commands + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_tx_tdata_next = init_data_reg[7:0]; + m_axis_tx_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:4] == 5'b00001) begin + // delay + if (SIM_SPEEDUP) begin + delay_counter_next = 32'd1 << (init_data_reg[3:0]); + end else begin + delay_counter_next = 32'd1 << (init_data_reg[3:0]+16); + end + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_RUN; + end + end + STATE_TABLE_1: begin + // find address table start + if (init_data_reg == 9'b000001000) begin + // address table start + address_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end + end + STATE_TABLE_2: begin + // find next address + if (init_data_reg[8:7] == 2'b01) begin + // write address command + // store address and move to data table + cur_address_next = init_data_reg[6:0]; + address_ptr_next = address_reg + 1; + address_next = data_ptr_reg; + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end + end + STATE_TABLE_3: begin + // process data table with selected address + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_tx_tdata_next = init_data_reg[7:0]; + m_axis_tx_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000000011) begin + // write current address + m_axis_cmd_address_next = cur_address_reg; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg[8:4] == 5'b00001) begin + // delay + if (SIM_SPEEDUP) begin + delay_counter_next = 32'd1 << (init_data_reg[3:0]); + end else begin + delay_counter_next = 32'd1 << (init_data_reg[3:0]+16); + end + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'b000001000) begin + // address table start + address_next = address_ptr_reg; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_3; + end + end + default: begin + // invalid state + state_next = STATE_IDLE; + end + endcase + end +end + +always_ff @(posedge clk) begin + state_reg <= state_next; + + // read init_data ROM + init_data_reg <= init_data[address_next]; + + address_reg <= address_next; + address_ptr_reg <= address_ptr_next; + data_ptr_reg <= data_ptr_next; + + cur_address_reg <= cur_address_next; + + delay_counter_reg <= delay_counter_next; + + m_axis_cmd_address_reg <= m_axis_cmd_address_next; + m_axis_cmd_start_reg <= m_axis_cmd_start_next; + m_axis_cmd_write_reg <= m_axis_cmd_write_next; + m_axis_cmd_stop_reg <= m_axis_cmd_stop_next; + m_axis_cmd_valid_reg <= m_axis_cmd_valid_next; + + m_axis_tx_tdata_reg <= m_axis_tx_tdata_next; + m_axis_tx_tvalid_reg <= m_axis_tx_tvalid_next; + + start_flag_reg <= start && start_flag_next; + + busy_reg <= (state_reg != STATE_IDLE); + + if (rst) begin + state_reg <= STATE_IDLE; + + init_data_reg <= '0; + + address_reg <= '0; + address_ptr_reg <= '0; + data_ptr_reg <= '0; + + cur_address_reg <= '0; + + delay_counter_reg <= '0; + + m_axis_cmd_valid_reg <= 1'b0; + + m_axis_tx_tvalid_reg <= 1'b0; + + start_flag_reg <= 1'b0; + + busy_reg <= 1'b0; + end +end + +endmodule + +`resetall +""") + + print(f"Writing file '{output}'...") + + with open(output, 'w') as f: + f.write(t.render( + cmd_str=cmd_str, + cmd_count=cmd_count, + name=name + )) + f.flush() + + print("Done") + + +if __name__ == "__main__": + main() diff --git a/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init.sv b/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init.sv new file mode 100644 index 0000000..9f91946 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/pll/si5341_i2c_init.sv @@ -0,0 +1,1088 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2015-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * si5341_i2c_init + */ +module si5341_i2c_init # +( + parameter logic SIM_SPEEDUP = 1'b0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * I2C master interface + */ + taxi_axis_if.src m_axis_cmd, + taxi_axis_if.src m_axis_tx, + + /* + * Status + */ + output wire logic busy, + + /* + * Configuration + */ + input wire logic start +); + +/* + +Generic module for I2C bus initialization. Good for use when multiple devices +on an I2C bus must be initialized on system start without intervention of a +general-purpose processor. + +Copy this file and change init_data and INIT_DATA_LEN as needed. + +This module can be used in two modes: simple device initialization, or multiple +device initialization. In multiple device mode, the same initialization sequence +can be performed on multiple different device addresses. + +To use single device mode, only use the start write to address and write data commands. +The module will generate the I2C commands in sequential order. Terminate the list +with a 0 entry. + +To use the multiple device mode, use the start data and start address block commands +to set up lists of initialization data and device addresses. The module enters +multiple device mode upon seeing a start data block command. The module stores the +offset of the start of the data block and then skips ahead until it reaches a start +address block command. The module will store the offset to the address block and +read the first address in the block. Then it will jump back to the data block +and execute it, substituting the stored address for each current address write +command. Upon reaching the start address block command, the module will read out the +next address and start again at the top of the data block. If the module encounters +a start data block command while looking for an address, then it will store a new data +offset and then look for a start address block command. Terminate the list with a 0 +entry. Normal address commands will operate normally inside a data block. + +Commands: + +00 0000000 : stop +00 0000001 : exit multiple device mode +00 0000011 : start write to current address +00 0001000 : start address block +00 0001001 : start data block +00 001dddd : delay 2**(16+d) cycles +00 1000001 : send I2C stop +01 aaaaaaa : start write to address +1 dddddddd : write 8-bit data + +Examples + +write 0x11223344 to register 0x0004 on device at 0x50 + +01 1010000 start write to 0x50 +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +0 00000000 stop + +write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53 + +00 0001001 start data block +00 0000011 start write to current address +1 00000000 write address 0x0004 +1 00000100 +1 00010001 write data 0x11223344 +1 00100010 +1 00110011 +1 01000100 +00 0001000 start address block +01 1010000 address 0x50 +01 1010001 address 0x51 +01 1010010 address 0x52 +01 1010011 address 0x53 +00 0000001 exit multi-dev mode +00 0000000 stop + +*/ + +// check configuration +if (m_axis_cmd.DATA_W < 12) + $fatal(0, "Command interface width must be at least 12 bits (instance %m)"); + +if (m_axis_tx.DATA_W != 8) + $fatal(0, "Data interface width must be 8 bits (instance %m)"); + +function [8:0] cmd_start(input [6:0] addr); + cmd_start = {2'b01, addr}; +endfunction + +function [8:0] cmd_wr(input [7:0] data); + cmd_wr = {1'b1, data}; +endfunction + +function [8:0] cmd_stop(); + cmd_stop = {2'b00, 7'b1000001}; +endfunction + +function [8:0] cmd_delay(input [3:0] d); + cmd_delay = {2'b00, 3'b001, d}; +endfunction + +function [8:0] cmd_halt(); + cmd_halt = 9'd0; +endfunction + +function [8:0] blk_start_data(); + blk_start_data = {2'b00, 7'b0001001}; +endfunction + +function [8:0] blk_start_addr(); + blk_start_addr = {2'b00, 7'b0001000}; +endfunction + +function [8:0] cmd_start_cur(); + cmd_start_cur = {2'b00, 7'b0000011}; +endfunction + +function [8:0] cmd_exit(); + cmd_exit = {2'b00, 7'b0000001}; +endfunction + +// init_data ROM +localparam INIT_DATA_LEN = 536; + +reg [8:0] init_data [INIT_DATA_LEN-1:0]; + +initial begin + // Initial delay + init_data[0] = cmd_delay(6); // delay 30 ms + // Set muxes to select U48 Si5341 on HTG-9200 + init_data[1] = cmd_start(7'h70); + init_data[2] = cmd_wr(8'h00); + init_data[3] = cmd_stop(); // I2C stop + init_data[4] = cmd_start(7'h71); + init_data[5] = cmd_wr(8'h04); + init_data[6] = cmd_stop(); // I2C stop + // Si534x/7x/8x/9x Registers Script + // + // Part: Si5341 + // Project File: X:\Projects\verilog-ethernet\example\HTG9200\fpga_25g\pll\HTG9200_161-9k2_161.slabtimeproj + // Design ID: 9k2_161 + // Includes Pre/Post Download Control Register Writes: Yes + // Die Revision: B1 + // Creator: ClockBuilder Pro v4.1 [2021-09-22] + // Created On: 2023-07-19 01:51:06 GMT-07:00 + // + // Start configuration preamble + init_data[7] = cmd_start(7'h77); + init_data[8] = cmd_wr(8'h01); + init_data[9] = cmd_wr(8'h0b); // set page 0x0b + init_data[10] = cmd_start(7'h77); + init_data[11] = cmd_wr(8'h24); + init_data[12] = cmd_wr(8'hc0); // write 0xc0 to 0x0b24 + init_data[13] = cmd_wr(8'h00); // write 0x00 to 0x0b25 + // Rev D stuck divider fix + init_data[14] = cmd_start(7'h77); + init_data[15] = cmd_wr(8'h01); + init_data[16] = cmd_wr(8'h05); // set page 0x05 + init_data[17] = cmd_start(7'h77); + init_data[18] = cmd_wr(8'h02); + init_data[19] = cmd_wr(8'h01); // write 0x01 to 0x0502 + init_data[20] = cmd_start(7'h77); + init_data[21] = cmd_wr(8'h05); + init_data[22] = cmd_wr(8'h03); // write 0x03 to 0x0505 + init_data[23] = cmd_start(7'h77); + init_data[24] = cmd_wr(8'h01); + init_data[25] = cmd_wr(8'h09); // set page 0x09 + init_data[26] = cmd_start(7'h77); + init_data[27] = cmd_wr(8'h57); + init_data[28] = cmd_wr(8'h17); // write 0x17 to 0x0957 + init_data[29] = cmd_start(7'h77); + init_data[30] = cmd_wr(8'h01); + init_data[31] = cmd_wr(8'h0b); // set page 0x0b + init_data[32] = cmd_start(7'h77); + init_data[33] = cmd_wr(8'h4e); + init_data[34] = cmd_wr(8'h1a); // write 0x1a to 0x0b4e + // End configuration preamble + // + // Delay 300 msec + init_data[35] = cmd_delay(10); // delay 300 ms + // Delay is worst case time for device to complete any calibration + // that is running due to device state change previous to this script + // being processed. + // + // Start configuration registers + init_data[36] = cmd_start(7'h77); + init_data[37] = cmd_wr(8'h01); + init_data[38] = cmd_wr(8'h00); // set page 0x00 + init_data[39] = cmd_start(7'h77); + init_data[40] = cmd_wr(8'h06); + init_data[41] = cmd_wr(8'h00); // write 0x00 to 0x0006 + init_data[42] = cmd_wr(8'h00); // write 0x00 to 0x0007 + init_data[43] = cmd_wr(8'h00); // write 0x00 to 0x0008 + init_data[44] = cmd_start(7'h77); + init_data[45] = cmd_wr(8'h0b); + init_data[46] = cmd_wr(8'h74); // write 0x74 to 0x000b + init_data[47] = cmd_start(7'h77); + init_data[48] = cmd_wr(8'h17); + init_data[49] = cmd_wr(8'hd0); // write 0xd0 to 0x0017 + init_data[50] = cmd_wr(8'hff); // write 0xff to 0x0018 + init_data[51] = cmd_start(7'h77); + init_data[52] = cmd_wr(8'h21); + init_data[53] = cmd_wr(8'h0b); // write 0x0b to 0x0021 + init_data[54] = cmd_wr(8'h00); // write 0x00 to 0x0022 + init_data[55] = cmd_start(7'h77); + init_data[56] = cmd_wr(8'h2b); + init_data[57] = cmd_wr(8'h02); // write 0x02 to 0x002b + init_data[58] = cmd_wr(8'h33); // write 0x33 to 0x002c + init_data[59] = cmd_wr(8'h05); // write 0x05 to 0x002d + init_data[60] = cmd_wr(8'hae); // write 0xae to 0x002e + init_data[61] = cmd_wr(8'h00); // write 0x00 to 0x002f + init_data[62] = cmd_wr(8'hae); // write 0xae to 0x0030 + init_data[63] = cmd_wr(8'h00); // write 0x00 to 0x0031 + init_data[64] = cmd_wr(8'h00); // write 0x00 to 0x0032 + init_data[65] = cmd_wr(8'h00); // write 0x00 to 0x0033 + init_data[66] = cmd_wr(8'h00); // write 0x00 to 0x0034 + init_data[67] = cmd_wr(8'h00); // write 0x00 to 0x0035 + init_data[68] = cmd_wr(8'hae); // write 0xae to 0x0036 + init_data[69] = cmd_wr(8'h00); // write 0x00 to 0x0037 + init_data[70] = cmd_wr(8'hae); // write 0xae to 0x0038 + init_data[71] = cmd_wr(8'h00); // write 0x00 to 0x0039 + init_data[72] = cmd_wr(8'h00); // write 0x00 to 0x003a + init_data[73] = cmd_wr(8'h00); // write 0x00 to 0x003b + init_data[74] = cmd_wr(8'h00); // write 0x00 to 0x003c + init_data[75] = cmd_wr(8'h00); // write 0x00 to 0x003d + init_data[76] = cmd_start(7'h77); + init_data[77] = cmd_wr(8'h41); + init_data[78] = cmd_wr(8'h07); // write 0x07 to 0x0041 + init_data[79] = cmd_wr(8'h07); // write 0x07 to 0x0042 + init_data[80] = cmd_wr(8'h00); // write 0x00 to 0x0043 + init_data[81] = cmd_wr(8'h00); // write 0x00 to 0x0044 + init_data[82] = cmd_start(7'h77); + init_data[83] = cmd_wr(8'h9e); + init_data[84] = cmd_wr(8'h00); // write 0x00 to 0x009e + init_data[85] = cmd_start(7'h77); + init_data[86] = cmd_wr(8'h01); + init_data[87] = cmd_wr(8'h01); // set page 0x01 + init_data[88] = cmd_start(7'h77); + init_data[89] = cmd_wr(8'h02); + init_data[90] = cmd_wr(8'h01); // write 0x01 to 0x0102 + init_data[91] = cmd_start(7'h77); + init_data[92] = cmd_wr(8'h08); + init_data[93] = cmd_wr(8'h06); // write 0x06 to 0x0108 + init_data[94] = cmd_wr(8'h09); // write 0x09 to 0x0109 + init_data[95] = cmd_wr(8'h3b); // write 0x3b to 0x010a + init_data[96] = cmd_wr(8'h28); // write 0x28 to 0x010b + init_data[97] = cmd_start(7'h77); + init_data[98] = cmd_wr(8'h0d); + init_data[99] = cmd_wr(8'h06); // write 0x06 to 0x010d + init_data[100] = cmd_wr(8'h09); // write 0x09 to 0x010e + init_data[101] = cmd_wr(8'h3b); // write 0x3b to 0x010f + init_data[102] = cmd_wr(8'h28); // write 0x28 to 0x0110 + init_data[103] = cmd_start(7'h77); + init_data[104] = cmd_wr(8'h12); + init_data[105] = cmd_wr(8'h02); // write 0x02 to 0x0112 + init_data[106] = cmd_wr(8'h09); // write 0x09 to 0x0113 + init_data[107] = cmd_wr(8'h3b); // write 0x3b to 0x0114 + init_data[108] = cmd_wr(8'h29); // write 0x29 to 0x0115 + init_data[109] = cmd_start(7'h77); + init_data[110] = cmd_wr(8'h17); + init_data[111] = cmd_wr(8'h06); // write 0x06 to 0x0117 + init_data[112] = cmd_wr(8'h09); // write 0x09 to 0x0118 + init_data[113] = cmd_wr(8'h3b); // write 0x3b to 0x0119 + init_data[114] = cmd_wr(8'h28); // write 0x28 to 0x011a + init_data[115] = cmd_start(7'h77); + init_data[116] = cmd_wr(8'h1c); + init_data[117] = cmd_wr(8'h06); // write 0x06 to 0x011c + init_data[118] = cmd_wr(8'h09); // write 0x09 to 0x011d + init_data[119] = cmd_wr(8'h3b); // write 0x3b to 0x011e + init_data[120] = cmd_wr(8'h28); // write 0x28 to 0x011f + init_data[121] = cmd_start(7'h77); + init_data[122] = cmd_wr(8'h21); + init_data[123] = cmd_wr(8'h06); // write 0x06 to 0x0121 + init_data[124] = cmd_wr(8'h09); // write 0x09 to 0x0122 + init_data[125] = cmd_wr(8'h3b); // write 0x3b to 0x0123 + init_data[126] = cmd_wr(8'h28); // write 0x28 to 0x0124 + init_data[127] = cmd_start(7'h77); + init_data[128] = cmd_wr(8'h26); + init_data[129] = cmd_wr(8'h06); // write 0x06 to 0x0126 + init_data[130] = cmd_wr(8'h09); // write 0x09 to 0x0127 + init_data[131] = cmd_wr(8'h3b); // write 0x3b to 0x0128 + init_data[132] = cmd_wr(8'h28); // write 0x28 to 0x0129 + init_data[133] = cmd_start(7'h77); + init_data[134] = cmd_wr(8'h2b); + init_data[135] = cmd_wr(8'h06); // write 0x06 to 0x012b + init_data[136] = cmd_wr(8'h09); // write 0x09 to 0x012c + init_data[137] = cmd_wr(8'h3b); // write 0x3b to 0x012d + init_data[138] = cmd_wr(8'h28); // write 0x28 to 0x012e + init_data[139] = cmd_start(7'h77); + init_data[140] = cmd_wr(8'h30); + init_data[141] = cmd_wr(8'h06); // write 0x06 to 0x0130 + init_data[142] = cmd_wr(8'h09); // write 0x09 to 0x0131 + init_data[143] = cmd_wr(8'h3b); // write 0x3b to 0x0132 + init_data[144] = cmd_wr(8'h28); // write 0x28 to 0x0133 + init_data[145] = cmd_start(7'h77); + init_data[146] = cmd_wr(8'h3a); + init_data[147] = cmd_wr(8'h06); // write 0x06 to 0x013a + init_data[148] = cmd_wr(8'h09); // write 0x09 to 0x013b + init_data[149] = cmd_wr(8'h3b); // write 0x3b to 0x013c + init_data[150] = cmd_wr(8'h28); // write 0x28 to 0x013d + init_data[151] = cmd_start(7'h77); + init_data[152] = cmd_wr(8'h3f); + init_data[153] = cmd_wr(8'h00); // write 0x00 to 0x013f + init_data[154] = cmd_wr(8'h00); // write 0x00 to 0x0140 + init_data[155] = cmd_wr(8'h40); // write 0x40 to 0x0141 + init_data[156] = cmd_start(7'h77); + init_data[157] = cmd_wr(8'h01); + init_data[158] = cmd_wr(8'h02); // set page 0x02 + init_data[159] = cmd_start(7'h77); + init_data[160] = cmd_wr(8'h06); + init_data[161] = cmd_wr(8'h00); // write 0x00 to 0x0206 + init_data[162] = cmd_start(7'h77); + init_data[163] = cmd_wr(8'h08); + init_data[164] = cmd_wr(8'h02); // write 0x02 to 0x0208 + init_data[165] = cmd_wr(8'h00); // write 0x00 to 0x0209 + init_data[166] = cmd_wr(8'h00); // write 0x00 to 0x020a + init_data[167] = cmd_wr(8'h00); // write 0x00 to 0x020b + init_data[168] = cmd_wr(8'h00); // write 0x00 to 0x020c + init_data[169] = cmd_wr(8'h00); // write 0x00 to 0x020d + init_data[170] = cmd_wr(8'h01); // write 0x01 to 0x020e + init_data[171] = cmd_wr(8'h00); // write 0x00 to 0x020f + init_data[172] = cmd_wr(8'h00); // write 0x00 to 0x0210 + init_data[173] = cmd_wr(8'h00); // write 0x00 to 0x0211 + init_data[174] = cmd_wr(8'h02); // write 0x02 to 0x0212 + init_data[175] = cmd_wr(8'h00); // write 0x00 to 0x0213 + init_data[176] = cmd_wr(8'h00); // write 0x00 to 0x0214 + init_data[177] = cmd_wr(8'h00); // write 0x00 to 0x0215 + init_data[178] = cmd_wr(8'h00); // write 0x00 to 0x0216 + init_data[179] = cmd_wr(8'h00); // write 0x00 to 0x0217 + init_data[180] = cmd_wr(8'h01); // write 0x01 to 0x0218 + init_data[181] = cmd_wr(8'h00); // write 0x00 to 0x0219 + init_data[182] = cmd_wr(8'h00); // write 0x00 to 0x021a + init_data[183] = cmd_wr(8'h00); // write 0x00 to 0x021b + init_data[184] = cmd_wr(8'h00); // write 0x00 to 0x021c + init_data[185] = cmd_wr(8'h00); // write 0x00 to 0x021d + init_data[186] = cmd_wr(8'h00); // write 0x00 to 0x021e + init_data[187] = cmd_wr(8'h00); // write 0x00 to 0x021f + init_data[188] = cmd_wr(8'h00); // write 0x00 to 0x0220 + init_data[189] = cmd_wr(8'h00); // write 0x00 to 0x0221 + init_data[190] = cmd_wr(8'h00); // write 0x00 to 0x0222 + init_data[191] = cmd_wr(8'h00); // write 0x00 to 0x0223 + init_data[192] = cmd_wr(8'h00); // write 0x00 to 0x0224 + init_data[193] = cmd_wr(8'h00); // write 0x00 to 0x0225 + init_data[194] = cmd_wr(8'h00); // write 0x00 to 0x0226 + init_data[195] = cmd_wr(8'h00); // write 0x00 to 0x0227 + init_data[196] = cmd_wr(8'h00); // write 0x00 to 0x0228 + init_data[197] = cmd_wr(8'h00); // write 0x00 to 0x0229 + init_data[198] = cmd_wr(8'h00); // write 0x00 to 0x022a + init_data[199] = cmd_wr(8'h00); // write 0x00 to 0x022b + init_data[200] = cmd_wr(8'h00); // write 0x00 to 0x022c + init_data[201] = cmd_wr(8'h00); // write 0x00 to 0x022d + init_data[202] = cmd_wr(8'h00); // write 0x00 to 0x022e + init_data[203] = cmd_wr(8'h00); // write 0x00 to 0x022f + init_data[204] = cmd_start(7'h77); + init_data[205] = cmd_wr(8'h35); + init_data[206] = cmd_wr(8'h00); // write 0x00 to 0x0235 + init_data[207] = cmd_wr(8'h00); // write 0x00 to 0x0236 + init_data[208] = cmd_wr(8'h00); // write 0x00 to 0x0237 + init_data[209] = cmd_wr(8'h90); // write 0x90 to 0x0238 + init_data[210] = cmd_wr(8'h54); // write 0x54 to 0x0239 + init_data[211] = cmd_wr(8'h00); // write 0x00 to 0x023a + init_data[212] = cmd_wr(8'h00); // write 0x00 to 0x023b + init_data[213] = cmd_wr(8'h00); // write 0x00 to 0x023c + init_data[214] = cmd_wr(8'h00); // write 0x00 to 0x023d + init_data[215] = cmd_wr(8'h80); // write 0x80 to 0x023e + init_data[216] = cmd_start(7'h77); + init_data[217] = cmd_wr(8'h4a); + init_data[218] = cmd_wr(8'h00); // write 0x00 to 0x024a + init_data[219] = cmd_wr(8'h00); // write 0x00 to 0x024b + init_data[220] = cmd_wr(8'h00); // write 0x00 to 0x024c + init_data[221] = cmd_wr(8'h00); // write 0x00 to 0x024d + init_data[222] = cmd_wr(8'h00); // write 0x00 to 0x024e + init_data[223] = cmd_wr(8'h00); // write 0x00 to 0x024f + init_data[224] = cmd_wr(8'h03); // write 0x03 to 0x0250 + init_data[225] = cmd_wr(8'h00); // write 0x00 to 0x0251 + init_data[226] = cmd_wr(8'h00); // write 0x00 to 0x0252 + init_data[227] = cmd_wr(8'h00); // write 0x00 to 0x0253 + init_data[228] = cmd_wr(8'h00); // write 0x00 to 0x0254 + init_data[229] = cmd_wr(8'h00); // write 0x00 to 0x0255 + init_data[230] = cmd_wr(8'h00); // write 0x00 to 0x0256 + init_data[231] = cmd_wr(8'h00); // write 0x00 to 0x0257 + init_data[232] = cmd_wr(8'h00); // write 0x00 to 0x0258 + init_data[233] = cmd_wr(8'h00); // write 0x00 to 0x0259 + init_data[234] = cmd_wr(8'h00); // write 0x00 to 0x025a + init_data[235] = cmd_wr(8'h00); // write 0x00 to 0x025b + init_data[236] = cmd_wr(8'h00); // write 0x00 to 0x025c + init_data[237] = cmd_wr(8'h00); // write 0x00 to 0x025d + init_data[238] = cmd_wr(8'h00); // write 0x00 to 0x025e + init_data[239] = cmd_wr(8'h00); // write 0x00 to 0x025f + init_data[240] = cmd_wr(8'h00); // write 0x00 to 0x0260 + init_data[241] = cmd_wr(8'h00); // write 0x00 to 0x0261 + init_data[242] = cmd_wr(8'h00); // write 0x00 to 0x0262 + init_data[243] = cmd_wr(8'h00); // write 0x00 to 0x0263 + init_data[244] = cmd_wr(8'h00); // write 0x00 to 0x0264 + init_data[245] = cmd_start(7'h77); + init_data[246] = cmd_wr(8'h68); + init_data[247] = cmd_wr(8'h00); // write 0x00 to 0x0268 + init_data[248] = cmd_wr(8'h00); // write 0x00 to 0x0269 + init_data[249] = cmd_wr(8'h00); // write 0x00 to 0x026a + init_data[250] = cmd_wr(8'h39); // write 0x39 to 0x026b + init_data[251] = cmd_wr(8'h6b); // write 0x6b to 0x026c + init_data[252] = cmd_wr(8'h32); // write 0x32 to 0x026d + init_data[253] = cmd_wr(8'h5f); // write 0x5f to 0x026e + init_data[254] = cmd_wr(8'h31); // write 0x31 to 0x026f + init_data[255] = cmd_wr(8'h36); // write 0x36 to 0x0270 + init_data[256] = cmd_wr(8'h31); // write 0x31 to 0x0271 + init_data[257] = cmd_wr(8'h00); // write 0x00 to 0x0272 + init_data[258] = cmd_start(7'h77); + init_data[259] = cmd_wr(8'h01); + init_data[260] = cmd_wr(8'h03); // set page 0x03 + init_data[261] = cmd_start(7'h77); + init_data[262] = cmd_wr(8'h02); + init_data[263] = cmd_wr(8'h00); // write 0x00 to 0x0302 + init_data[264] = cmd_wr(8'h00); // write 0x00 to 0x0303 + init_data[265] = cmd_wr(8'h00); // write 0x00 to 0x0304 + init_data[266] = cmd_wr(8'h80); // write 0x80 to 0x0305 + init_data[267] = cmd_wr(8'h14); // write 0x14 to 0x0306 + init_data[268] = cmd_wr(8'h00); // write 0x00 to 0x0307 + init_data[269] = cmd_wr(8'h00); // write 0x00 to 0x0308 + init_data[270] = cmd_wr(8'h00); // write 0x00 to 0x0309 + init_data[271] = cmd_wr(8'h00); // write 0x00 to 0x030a + init_data[272] = cmd_wr(8'h80); // write 0x80 to 0x030b + init_data[273] = cmd_wr(8'h00); // write 0x00 to 0x030c + init_data[274] = cmd_wr(8'h00); // write 0x00 to 0x030d + init_data[275] = cmd_wr(8'h00); // write 0x00 to 0x030e + init_data[276] = cmd_wr(8'h10); // write 0x10 to 0x030f + init_data[277] = cmd_wr(8'h42); // write 0x42 to 0x0310 + init_data[278] = cmd_wr(8'h08); // write 0x08 to 0x0311 + init_data[279] = cmd_wr(8'h00); // write 0x00 to 0x0312 + init_data[280] = cmd_wr(8'h00); // write 0x00 to 0x0313 + init_data[281] = cmd_wr(8'h00); // write 0x00 to 0x0314 + init_data[282] = cmd_wr(8'h00); // write 0x00 to 0x0315 + init_data[283] = cmd_wr(8'h80); // write 0x80 to 0x0316 + init_data[284] = cmd_wr(8'h00); // write 0x00 to 0x0317 + init_data[285] = cmd_wr(8'h00); // write 0x00 to 0x0318 + init_data[286] = cmd_wr(8'h00); // write 0x00 to 0x0319 + init_data[287] = cmd_wr(8'h00); // write 0x00 to 0x031a + init_data[288] = cmd_wr(8'h00); // write 0x00 to 0x031b + init_data[289] = cmd_wr(8'h00); // write 0x00 to 0x031c + init_data[290] = cmd_wr(8'h00); // write 0x00 to 0x031d + init_data[291] = cmd_wr(8'h00); // write 0x00 to 0x031e + init_data[292] = cmd_wr(8'h00); // write 0x00 to 0x031f + init_data[293] = cmd_wr(8'h00); // write 0x00 to 0x0320 + init_data[294] = cmd_wr(8'h00); // write 0x00 to 0x0321 + init_data[295] = cmd_wr(8'h00); // write 0x00 to 0x0322 + init_data[296] = cmd_wr(8'h00); // write 0x00 to 0x0323 + init_data[297] = cmd_wr(8'h00); // write 0x00 to 0x0324 + init_data[298] = cmd_wr(8'h00); // write 0x00 to 0x0325 + init_data[299] = cmd_wr(8'h00); // write 0x00 to 0x0326 + init_data[300] = cmd_wr(8'h00); // write 0x00 to 0x0327 + init_data[301] = cmd_wr(8'h00); // write 0x00 to 0x0328 + init_data[302] = cmd_wr(8'h00); // write 0x00 to 0x0329 + init_data[303] = cmd_wr(8'h00); // write 0x00 to 0x032a + init_data[304] = cmd_wr(8'h00); // write 0x00 to 0x032b + init_data[305] = cmd_wr(8'h00); // write 0x00 to 0x032c + init_data[306] = cmd_wr(8'h00); // write 0x00 to 0x032d + init_data[307] = cmd_wr(8'h00); // write 0x00 to 0x032e + init_data[308] = cmd_wr(8'h00); // write 0x00 to 0x032f + init_data[309] = cmd_wr(8'h00); // write 0x00 to 0x0330 + init_data[310] = cmd_wr(8'h00); // write 0x00 to 0x0331 + init_data[311] = cmd_wr(8'h00); // write 0x00 to 0x0332 + init_data[312] = cmd_wr(8'h00); // write 0x00 to 0x0333 + init_data[313] = cmd_wr(8'h00); // write 0x00 to 0x0334 + init_data[314] = cmd_wr(8'h00); // write 0x00 to 0x0335 + init_data[315] = cmd_wr(8'h00); // write 0x00 to 0x0336 + init_data[316] = cmd_wr(8'h00); // write 0x00 to 0x0337 + init_data[317] = cmd_wr(8'h00); // write 0x00 to 0x0338 + init_data[318] = cmd_wr(8'h1f); // write 0x1f to 0x0339 + init_data[319] = cmd_start(7'h77); + init_data[320] = cmd_wr(8'h3b); + init_data[321] = cmd_wr(8'h00); // write 0x00 to 0x033b + init_data[322] = cmd_wr(8'h00); // write 0x00 to 0x033c + init_data[323] = cmd_wr(8'h00); // write 0x00 to 0x033d + init_data[324] = cmd_wr(8'h00); // write 0x00 to 0x033e + init_data[325] = cmd_wr(8'h00); // write 0x00 to 0x033f + init_data[326] = cmd_wr(8'h00); // write 0x00 to 0x0340 + init_data[327] = cmd_wr(8'h00); // write 0x00 to 0x0341 + init_data[328] = cmd_wr(8'h00); // write 0x00 to 0x0342 + init_data[329] = cmd_wr(8'h00); // write 0x00 to 0x0343 + init_data[330] = cmd_wr(8'h00); // write 0x00 to 0x0344 + init_data[331] = cmd_wr(8'h00); // write 0x00 to 0x0345 + init_data[332] = cmd_wr(8'h00); // write 0x00 to 0x0346 + init_data[333] = cmd_wr(8'h00); // write 0x00 to 0x0347 + init_data[334] = cmd_wr(8'h00); // write 0x00 to 0x0348 + init_data[335] = cmd_wr(8'h00); // write 0x00 to 0x0349 + init_data[336] = cmd_wr(8'h00); // write 0x00 to 0x034a + init_data[337] = cmd_wr(8'h00); // write 0x00 to 0x034b + init_data[338] = cmd_wr(8'h00); // write 0x00 to 0x034c + init_data[339] = cmd_wr(8'h00); // write 0x00 to 0x034d + init_data[340] = cmd_wr(8'h00); // write 0x00 to 0x034e + init_data[341] = cmd_wr(8'h00); // write 0x00 to 0x034f + init_data[342] = cmd_wr(8'h00); // write 0x00 to 0x0350 + init_data[343] = cmd_wr(8'h00); // write 0x00 to 0x0351 + init_data[344] = cmd_wr(8'h00); // write 0x00 to 0x0352 + init_data[345] = cmd_wr(8'h00); // write 0x00 to 0x0353 + init_data[346] = cmd_wr(8'h00); // write 0x00 to 0x0354 + init_data[347] = cmd_wr(8'h00); // write 0x00 to 0x0355 + init_data[348] = cmd_wr(8'h00); // write 0x00 to 0x0356 + init_data[349] = cmd_wr(8'h00); // write 0x00 to 0x0357 + init_data[350] = cmd_wr(8'h00); // write 0x00 to 0x0358 + init_data[351] = cmd_wr(8'h00); // write 0x00 to 0x0359 + init_data[352] = cmd_wr(8'h00); // write 0x00 to 0x035a + init_data[353] = cmd_wr(8'h00); // write 0x00 to 0x035b + init_data[354] = cmd_wr(8'h00); // write 0x00 to 0x035c + init_data[355] = cmd_wr(8'h00); // write 0x00 to 0x035d + init_data[356] = cmd_wr(8'h00); // write 0x00 to 0x035e + init_data[357] = cmd_wr(8'h00); // write 0x00 to 0x035f + init_data[358] = cmd_wr(8'h00); // write 0x00 to 0x0360 + init_data[359] = cmd_wr(8'h00); // write 0x00 to 0x0361 + init_data[360] = cmd_wr(8'h00); // write 0x00 to 0x0362 + init_data[361] = cmd_start(7'h77); + init_data[362] = cmd_wr(8'h01); + init_data[363] = cmd_wr(8'h08); // set page 0x08 + init_data[364] = cmd_start(7'h77); + init_data[365] = cmd_wr(8'h02); + init_data[366] = cmd_wr(8'h00); // write 0x00 to 0x0802 + init_data[367] = cmd_wr(8'h00); // write 0x00 to 0x0803 + init_data[368] = cmd_wr(8'h00); // write 0x00 to 0x0804 + init_data[369] = cmd_wr(8'h00); // write 0x00 to 0x0805 + init_data[370] = cmd_wr(8'h00); // write 0x00 to 0x0806 + init_data[371] = cmd_wr(8'h00); // write 0x00 to 0x0807 + init_data[372] = cmd_wr(8'h00); // write 0x00 to 0x0808 + init_data[373] = cmd_wr(8'h00); // write 0x00 to 0x0809 + init_data[374] = cmd_wr(8'h00); // write 0x00 to 0x080a + init_data[375] = cmd_wr(8'h00); // write 0x00 to 0x080b + init_data[376] = cmd_wr(8'h00); // write 0x00 to 0x080c + init_data[377] = cmd_wr(8'h00); // write 0x00 to 0x080d + init_data[378] = cmd_wr(8'h00); // write 0x00 to 0x080e + init_data[379] = cmd_wr(8'h00); // write 0x00 to 0x080f + init_data[380] = cmd_wr(8'h00); // write 0x00 to 0x0810 + init_data[381] = cmd_wr(8'h00); // write 0x00 to 0x0811 + init_data[382] = cmd_wr(8'h00); // write 0x00 to 0x0812 + init_data[383] = cmd_wr(8'h00); // write 0x00 to 0x0813 + init_data[384] = cmd_wr(8'h00); // write 0x00 to 0x0814 + init_data[385] = cmd_wr(8'h00); // write 0x00 to 0x0815 + init_data[386] = cmd_wr(8'h00); // write 0x00 to 0x0816 + init_data[387] = cmd_wr(8'h00); // write 0x00 to 0x0817 + init_data[388] = cmd_wr(8'h00); // write 0x00 to 0x0818 + init_data[389] = cmd_wr(8'h00); // write 0x00 to 0x0819 + init_data[390] = cmd_wr(8'h00); // write 0x00 to 0x081a + init_data[391] = cmd_wr(8'h00); // write 0x00 to 0x081b + init_data[392] = cmd_wr(8'h00); // write 0x00 to 0x081c + init_data[393] = cmd_wr(8'h00); // write 0x00 to 0x081d + init_data[394] = cmd_wr(8'h00); // write 0x00 to 0x081e + init_data[395] = cmd_wr(8'h00); // write 0x00 to 0x081f + init_data[396] = cmd_wr(8'h00); // write 0x00 to 0x0820 + init_data[397] = cmd_wr(8'h00); // write 0x00 to 0x0821 + init_data[398] = cmd_wr(8'h00); // write 0x00 to 0x0822 + init_data[399] = cmd_wr(8'h00); // write 0x00 to 0x0823 + init_data[400] = cmd_wr(8'h00); // write 0x00 to 0x0824 + init_data[401] = cmd_wr(8'h00); // write 0x00 to 0x0825 + init_data[402] = cmd_wr(8'h00); // write 0x00 to 0x0826 + init_data[403] = cmd_wr(8'h00); // write 0x00 to 0x0827 + init_data[404] = cmd_wr(8'h00); // write 0x00 to 0x0828 + init_data[405] = cmd_wr(8'h00); // write 0x00 to 0x0829 + init_data[406] = cmd_wr(8'h00); // write 0x00 to 0x082a + init_data[407] = cmd_wr(8'h00); // write 0x00 to 0x082b + init_data[408] = cmd_wr(8'h00); // write 0x00 to 0x082c + init_data[409] = cmd_wr(8'h00); // write 0x00 to 0x082d + init_data[410] = cmd_wr(8'h00); // write 0x00 to 0x082e + init_data[411] = cmd_wr(8'h00); // write 0x00 to 0x082f + init_data[412] = cmd_wr(8'h00); // write 0x00 to 0x0830 + init_data[413] = cmd_wr(8'h00); // write 0x00 to 0x0831 + init_data[414] = cmd_wr(8'h00); // write 0x00 to 0x0832 + init_data[415] = cmd_wr(8'h00); // write 0x00 to 0x0833 + init_data[416] = cmd_wr(8'h00); // write 0x00 to 0x0834 + init_data[417] = cmd_wr(8'h00); // write 0x00 to 0x0835 + init_data[418] = cmd_wr(8'h00); // write 0x00 to 0x0836 + init_data[419] = cmd_wr(8'h00); // write 0x00 to 0x0837 + init_data[420] = cmd_wr(8'h00); // write 0x00 to 0x0838 + init_data[421] = cmd_wr(8'h00); // write 0x00 to 0x0839 + init_data[422] = cmd_wr(8'h00); // write 0x00 to 0x083a + init_data[423] = cmd_wr(8'h00); // write 0x00 to 0x083b + init_data[424] = cmd_wr(8'h00); // write 0x00 to 0x083c + init_data[425] = cmd_wr(8'h00); // write 0x00 to 0x083d + init_data[426] = cmd_wr(8'h00); // write 0x00 to 0x083e + init_data[427] = cmd_wr(8'h00); // write 0x00 to 0x083f + init_data[428] = cmd_wr(8'h00); // write 0x00 to 0x0840 + init_data[429] = cmd_wr(8'h00); // write 0x00 to 0x0841 + init_data[430] = cmd_wr(8'h00); // write 0x00 to 0x0842 + init_data[431] = cmd_wr(8'h00); // write 0x00 to 0x0843 + init_data[432] = cmd_wr(8'h00); // write 0x00 to 0x0844 + init_data[433] = cmd_wr(8'h00); // write 0x00 to 0x0845 + init_data[434] = cmd_wr(8'h00); // write 0x00 to 0x0846 + init_data[435] = cmd_wr(8'h00); // write 0x00 to 0x0847 + init_data[436] = cmd_wr(8'h00); // write 0x00 to 0x0848 + init_data[437] = cmd_wr(8'h00); // write 0x00 to 0x0849 + init_data[438] = cmd_wr(8'h00); // write 0x00 to 0x084a + init_data[439] = cmd_wr(8'h00); // write 0x00 to 0x084b + init_data[440] = cmd_wr(8'h00); // write 0x00 to 0x084c + init_data[441] = cmd_wr(8'h00); // write 0x00 to 0x084d + init_data[442] = cmd_wr(8'h00); // write 0x00 to 0x084e + init_data[443] = cmd_wr(8'h00); // write 0x00 to 0x084f + init_data[444] = cmd_wr(8'h00); // write 0x00 to 0x0850 + init_data[445] = cmd_wr(8'h00); // write 0x00 to 0x0851 + init_data[446] = cmd_wr(8'h00); // write 0x00 to 0x0852 + init_data[447] = cmd_wr(8'h00); // write 0x00 to 0x0853 + init_data[448] = cmd_wr(8'h00); // write 0x00 to 0x0854 + init_data[449] = cmd_wr(8'h00); // write 0x00 to 0x0855 + init_data[450] = cmd_wr(8'h00); // write 0x00 to 0x0856 + init_data[451] = cmd_wr(8'h00); // write 0x00 to 0x0857 + init_data[452] = cmd_wr(8'h00); // write 0x00 to 0x0858 + init_data[453] = cmd_wr(8'h00); // write 0x00 to 0x0859 + init_data[454] = cmd_wr(8'h00); // write 0x00 to 0x085a + init_data[455] = cmd_wr(8'h00); // write 0x00 to 0x085b + init_data[456] = cmd_wr(8'h00); // write 0x00 to 0x085c + init_data[457] = cmd_wr(8'h00); // write 0x00 to 0x085d + init_data[458] = cmd_wr(8'h00); // write 0x00 to 0x085e + init_data[459] = cmd_wr(8'h00); // write 0x00 to 0x085f + init_data[460] = cmd_wr(8'h00); // write 0x00 to 0x0860 + init_data[461] = cmd_wr(8'h00); // write 0x00 to 0x0861 + init_data[462] = cmd_start(7'h77); + init_data[463] = cmd_wr(8'h01); + init_data[464] = cmd_wr(8'h09); // set page 0x09 + init_data[465] = cmd_start(7'h77); + init_data[466] = cmd_wr(8'h0e); + init_data[467] = cmd_wr(8'h00); // write 0x00 to 0x090e + init_data[468] = cmd_start(7'h77); + init_data[469] = cmd_wr(8'h1c); + init_data[470] = cmd_wr(8'h04); // write 0x04 to 0x091c + init_data[471] = cmd_start(7'h77); + init_data[472] = cmd_wr(8'h43); + init_data[473] = cmd_wr(8'h00); // write 0x00 to 0x0943 + init_data[474] = cmd_start(7'h77); + init_data[475] = cmd_wr(8'h49); + init_data[476] = cmd_wr(8'h03); // write 0x03 to 0x0949 + init_data[477] = cmd_wr(8'h30); // write 0x30 to 0x094a + init_data[478] = cmd_start(7'h77); + init_data[479] = cmd_wr(8'h4e); + init_data[480] = cmd_wr(8'h49); // write 0x49 to 0x094e + init_data[481] = cmd_wr(8'h02); // write 0x02 to 0x094f + init_data[482] = cmd_start(7'h77); + init_data[483] = cmd_wr(8'h5e); + init_data[484] = cmd_wr(8'h00); // write 0x00 to 0x095e + init_data[485] = cmd_start(7'h77); + init_data[486] = cmd_wr(8'h01); + init_data[487] = cmd_wr(8'h0a); // set page 0x0a + init_data[488] = cmd_start(7'h77); + init_data[489] = cmd_wr(8'h02); + init_data[490] = cmd_wr(8'h00); // write 0x00 to 0x0a02 + init_data[491] = cmd_wr(8'h03); // write 0x03 to 0x0a03 + init_data[492] = cmd_wr(8'h01); // write 0x01 to 0x0a04 + init_data[493] = cmd_wr(8'h03); // write 0x03 to 0x0a05 + init_data[494] = cmd_start(7'h77); + init_data[495] = cmd_wr(8'h14); + init_data[496] = cmd_wr(8'h00); // write 0x00 to 0x0a14 + init_data[497] = cmd_start(7'h77); + init_data[498] = cmd_wr(8'h1a); + init_data[499] = cmd_wr(8'h00); // write 0x00 to 0x0a1a + init_data[500] = cmd_start(7'h77); + init_data[501] = cmd_wr(8'h20); + init_data[502] = cmd_wr(8'h00); // write 0x00 to 0x0a20 + init_data[503] = cmd_start(7'h77); + init_data[504] = cmd_wr(8'h26); + init_data[505] = cmd_wr(8'h00); // write 0x00 to 0x0a26 + init_data[506] = cmd_start(7'h77); + init_data[507] = cmd_wr(8'h2c); + init_data[508] = cmd_wr(8'h00); // write 0x00 to 0x0a2c + init_data[509] = cmd_start(7'h77); + init_data[510] = cmd_wr(8'h01); + init_data[511] = cmd_wr(8'h0b); // set page 0x0b + init_data[512] = cmd_start(7'h77); + init_data[513] = cmd_wr(8'h44); + init_data[514] = cmd_wr(8'h0f); // write 0x0f to 0x0b44 + init_data[515] = cmd_start(7'h77); + init_data[516] = cmd_wr(8'h4a); + init_data[517] = cmd_wr(8'h1c); // write 0x1c to 0x0b4a + init_data[518] = cmd_start(7'h77); + init_data[519] = cmd_wr(8'h57); + init_data[520] = cmd_wr(8'ha5); // write 0xa5 to 0x0b57 + init_data[521] = cmd_wr(8'h00); // write 0x00 to 0x0b58 + // End configuration registers + // + // Start configuration postamble + init_data[522] = cmd_start(7'h77); + init_data[523] = cmd_wr(8'h01); + init_data[524] = cmd_wr(8'h00); // set page 0x00 + init_data[525] = cmd_start(7'h77); + init_data[526] = cmd_wr(8'h1c); + init_data[527] = cmd_wr(8'h01); // write 0x01 to 0x001c + init_data[528] = cmd_start(7'h77); + init_data[529] = cmd_wr(8'h01); + init_data[530] = cmd_wr(8'h0b); // set page 0x0b + init_data[531] = cmd_start(7'h77); + init_data[532] = cmd_wr(8'h24); + init_data[533] = cmd_wr(8'hc3); // write 0xc3 to 0x0b24 + init_data[534] = cmd_wr(8'h02); // write 0x02 to 0x0b25 + // End configuration postamble + init_data[535] = cmd_halt(); // end +end + +localparam [2:0] + STATE_IDLE = 3'd0, + STATE_RUN = 3'd1, + STATE_TABLE_1 = 3'd2, + STATE_TABLE_2 = 3'd3, + STATE_TABLE_3 = 3'd4; + +logic [2:0] state_reg = STATE_IDLE, state_next; + +localparam AW = $clog2(INIT_DATA_LEN); + +logic [8:0] init_data_reg = '0; + +logic [AW-1:0] address_reg = '0, address_next; +logic [AW-1:0] address_ptr_reg = '0, address_ptr_next; +logic [AW-1:0] data_ptr_reg = '0, data_ptr_next; + +logic [6:0] cur_address_reg = '0, cur_address_next; + +logic [31:0] delay_counter_reg = '0, delay_counter_next; + +logic [6:0] m_axis_cmd_address_reg = '0, m_axis_cmd_address_next; +logic m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next; +logic m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next; +logic m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next; +logic m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next; + +logic [7:0] m_axis_tx_tdata_reg = '0, m_axis_tx_tdata_next; +logic m_axis_tx_tvalid_reg = 1'b0, m_axis_tx_tvalid_next; + +logic start_flag_reg = 1'b0, start_flag_next; + +logic busy_reg = 1'b0; + +assign m_axis_cmd.tdata[6:0] = m_axis_cmd_address_reg; +assign m_axis_cmd.tdata[7] = m_axis_cmd_start_reg; +assign m_axis_cmd.tdata[8] = 1'b0; // read +assign m_axis_cmd.tdata[9] = m_axis_cmd_write_reg; +assign m_axis_cmd.tdata[10] = 1'b0; // write multi +assign m_axis_cmd.tdata[11] = m_axis_cmd_stop_reg; +assign m_axis_cmd.tvalid = m_axis_cmd_valid_reg; +assign m_axis_cmd.tlast = 1'b1; +assign m_axis_cmd.tid = '0; +assign m_axis_cmd.tdest = '0; +assign m_axis_cmd.tuser = '0; + +assign m_axis_tx.tdata = m_axis_tx_tdata_reg; +assign m_axis_tx.tvalid = m_axis_tx_tvalid_reg; +assign m_axis_tx.tlast = 1'b1; +assign m_axis_tx.tid = '0; +assign m_axis_tx.tdest = '0; +assign m_axis_tx.tuser = '0; + +assign busy = busy_reg; + +always_comb begin + state_next = STATE_IDLE; + + address_next = address_reg; + address_ptr_next = address_ptr_reg; + data_ptr_next = data_ptr_reg; + + cur_address_next = cur_address_reg; + + delay_counter_next = delay_counter_reg; + + m_axis_cmd_address_next = m_axis_cmd_address_reg; + m_axis_cmd_start_next = m_axis_cmd_start_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready); + m_axis_cmd_write_next = m_axis_cmd_write_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready); + m_axis_cmd_stop_next = m_axis_cmd_stop_reg && !(m_axis_cmd.tvalid && m_axis_cmd.tready); + m_axis_cmd_valid_next = m_axis_cmd_valid_reg && !m_axis_cmd.tready; + + m_axis_tx_tdata_next = m_axis_tx_tdata_reg; + m_axis_tx_tvalid_next = m_axis_tx_tvalid_reg && !m_axis_tx.tready; + + start_flag_next = start_flag_reg; + + if (m_axis_cmd.tvalid || m_axis_tx.tvalid) begin + // wait for output registers to clear + state_next = state_reg; + end else if (delay_counter_reg != 0) begin + // delay + delay_counter_next = delay_counter_reg - 1; + state_next = state_reg; + end else begin + case (state_reg) + STATE_IDLE: begin + // wait for start signal + if (!start_flag_reg && start) begin + address_next = '0; + start_flag_next = 1'b1; + state_next = STATE_RUN; + end else begin + state_next = STATE_IDLE; + end + end + STATE_RUN: begin + // process commands + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_tx_tdata_next = init_data_reg[7:0]; + m_axis_tx_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg[8:4] == 5'b00001) begin + // delay + if (SIM_SPEEDUP) begin + delay_counter_next = 32'd1 << (init_data_reg[3:0]); + end else begin + delay_counter_next = 32'd1 << (init_data_reg[3:0]+16); + end + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_RUN; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_RUN; + end + end + STATE_TABLE_1: begin + // find address table start + if (init_data_reg == 9'b000001000) begin + // address table start + address_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end + end + STATE_TABLE_2: begin + // find next address + if (init_data_reg[8:7] == 2'b01) begin + // write address command + // store address and move to data table + cur_address_next = init_data_reg[6:0]; + address_ptr_next = address_reg + 1; + address_next = data_ptr_reg; + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_2; + end + end + STATE_TABLE_3: begin + // process data table with selected address + if (init_data_reg[8] == 1'b1) begin + // write data + m_axis_cmd_write_next = 1'b1; + m_axis_cmd_stop_next = 1'b0; + m_axis_cmd_valid_next = 1'b1; + + m_axis_tx_tdata_next = init_data_reg[7:0]; + m_axis_tx_tvalid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg[8:7] == 2'b01) begin + // write address + m_axis_cmd_address_next = init_data_reg[6:0]; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000000011) begin + // write current address + m_axis_cmd_address_next = cur_address_reg; + m_axis_cmd_start_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg[8:4] == 5'b00001) begin + // delay + if (SIM_SPEEDUP) begin + delay_counter_next = 32'd1 << (init_data_reg[3:0]); + end else begin + delay_counter_next = 32'd1 << (init_data_reg[3:0]+16); + end + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b001000001) begin + // send stop + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + address_next = address_reg + 1; + + state_next = STATE_TABLE_3; + end else if (init_data_reg == 9'b000001001) begin + // data table start + data_ptr_next = address_reg + 1; + address_next = address_reg + 1; + state_next = STATE_TABLE_1; + end else if (init_data_reg == 9'b000001000) begin + // address table start + address_next = address_ptr_reg; + state_next = STATE_TABLE_2; + end else if (init_data_reg == 9'd1) begin + // exit mode + address_next = address_reg + 1; + state_next = STATE_RUN; + end else if (init_data_reg == 9'd0) begin + // stop + m_axis_cmd_start_next = 1'b0; + m_axis_cmd_write_next = 1'b0; + m_axis_cmd_stop_next = 1'b1; + m_axis_cmd_valid_next = 1'b1; + + state_next = STATE_IDLE; + end else begin + // invalid command, skip + address_next = address_reg + 1; + state_next = STATE_TABLE_3; + end + end + default: begin + // invalid state + state_next = STATE_IDLE; + end + endcase + end +end + +always_ff @(posedge clk) begin + state_reg <= state_next; + + // read init_data ROM + init_data_reg <= init_data[address_next]; + + address_reg <= address_next; + address_ptr_reg <= address_ptr_next; + data_ptr_reg <= data_ptr_next; + + cur_address_reg <= cur_address_next; + + delay_counter_reg <= delay_counter_next; + + m_axis_cmd_address_reg <= m_axis_cmd_address_next; + m_axis_cmd_start_reg <= m_axis_cmd_start_next; + m_axis_cmd_write_reg <= m_axis_cmd_write_next; + m_axis_cmd_stop_reg <= m_axis_cmd_stop_next; + m_axis_cmd_valid_reg <= m_axis_cmd_valid_next; + + m_axis_tx_tdata_reg <= m_axis_tx_tdata_next; + m_axis_tx_tvalid_reg <= m_axis_tx_tvalid_next; + + start_flag_reg <= start && start_flag_next; + + busy_reg <= (state_reg != STATE_IDLE); + + if (rst) begin + state_reg <= STATE_IDLE; + + init_data_reg <= '0; + + address_reg <= '0; + address_ptr_reg <= '0; + data_ptr_reg <= '0; + + cur_address_reg <= '0; + + delay_counter_reg <= '0; + + m_axis_cmd_valid_reg <= 1'b0; + + m_axis_tx_tvalid_reg <= 1'b0; + + start_flag_reg <= 1'b0; + + busy_reg <= 1'b0; + end +end + +endmodule + +`resetall \ No newline at end of file diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga.sv b/src/eth/example/HTG9200/fpga/rtl/fpga.sv new file mode 100644 index 0000000..b36744a --- /dev/null +++ b/src/eth/example/HTG9200/fpga/rtl/fpga.sv @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + parameter logic SIM = 1'b0, + parameter string VENDOR = "XILINX", + parameter string FAMILY = "virtexuplus" +) +( + /* + * Clock: 200 MHz LVDS + */ + input wire logic ref_clk_p, + input wire logic ref_clk_n, + + /* + * GPIO + */ + input wire logic [1:0] btn, + input wire logic [7:0] sw, + output wire logic [7:0] led, + + /* + * I2C for board management + */ + inout wire logic i2c_main_scl, + inout wire logic i2c_main_sda, + output wire logic i2c_main_rst_n, + + /* + * PLL + */ + output wire logic clk_gty2_fdec, + output wire logic clk_gty2_finc, + input wire logic clk_gty2_intr_n, + input wire logic clk_gty2_lol_n, + output wire logic clk_gty2_oe_n, + output wire logic clk_gty2_sync_n, + output wire logic clk_gty2_rst_n, + + /* + * UART: 921600 bps, 8N1 + */ + output wire logic uart_rxd, + input wire logic uart_txd, + input wire logic uart_rts, + output wire logic uart_cts, + output wire logic uart_rst_n, + output wire logic uart_suspend_n, + + /* + * Ethernet: QSFP28 + */ + output wire logic [3:0] qsfp_1_tx_p, + output wire logic [3:0] qsfp_1_tx_n, + input wire logic [3:0] qsfp_1_rx_p, + input wire logic [3:0] qsfp_1_rx_n, + input wire logic qsfp_1_mgt_refclk_p, + input wire logic qsfp_1_mgt_refclk_n, + output wire logic qsfp_1_resetl, + input wire logic qsfp_1_modprsl, + input wire logic qsfp_1_intl, + + output wire logic [3:0] qsfp_2_tx_p, + output wire logic [3:0] qsfp_2_tx_n, + input wire logic [3:0] qsfp_2_rx_p, + input wire logic [3:0] qsfp_2_rx_n, + input wire logic qsfp_2_mgt_refclk_p, + input wire logic qsfp_2_mgt_refclk_n, + output wire logic qsfp_2_resetl, + input wire logic qsfp_2_modprsl, + input wire logic qsfp_2_intl, + + output wire logic [3:0] qsfp_3_tx_p, + output wire logic [3:0] qsfp_3_tx_n, + input wire logic [3:0] qsfp_3_rx_p, + input wire logic [3:0] qsfp_3_rx_n, + input wire logic qsfp_3_mgt_refclk_p, + input wire logic qsfp_3_mgt_refclk_n, + output wire logic qsfp_3_resetl, + input wire logic qsfp_3_modprsl, + input wire logic qsfp_3_intl, + + output wire logic [3:0] qsfp_4_tx_p, + output wire logic [3:0] qsfp_4_tx_n, + input wire logic [3:0] qsfp_4_rx_p, + input wire logic [3:0] qsfp_4_rx_n, + input wire logic qsfp_4_mgt_refclk_p, + input wire logic qsfp_4_mgt_refclk_n, + output wire logic qsfp_4_resetl, + input wire logic qsfp_4_modprsl, + input wire logic qsfp_4_intl, + + output wire logic [3:0] qsfp_5_tx_p, + output wire logic [3:0] qsfp_5_tx_n, + input wire logic [3:0] qsfp_5_rx_p, + input wire logic [3:0] qsfp_5_rx_n, + input wire logic qsfp_5_mgt_refclk_p, + input wire logic qsfp_5_mgt_refclk_n, + output wire logic qsfp_5_resetl, + input wire logic qsfp_5_modprsl, + input wire logic qsfp_5_intl, + + output wire logic [3:0] qsfp_6_tx_p, + output wire logic [3:0] qsfp_6_tx_n, + input wire logic [3:0] qsfp_6_rx_p, + input wire logic [3:0] qsfp_6_rx_n, + input wire logic qsfp_6_mgt_refclk_p, + input wire logic qsfp_6_mgt_refclk_n, + output wire logic qsfp_6_resetl, + input wire logic qsfp_6_modprsl, + input wire logic qsfp_6_intl, + + output wire logic [3:0] qsfp_7_tx_p, + output wire logic [3:0] qsfp_7_tx_n, + input wire logic [3:0] qsfp_7_rx_p, + input wire logic [3:0] qsfp_7_rx_n, + input wire logic qsfp_7_mgt_refclk_p, + input wire logic qsfp_7_mgt_refclk_n, + output wire logic qsfp_7_resetl, + input wire logic qsfp_7_modprsl, + input wire logic qsfp_7_intl, + + output wire logic [3:0] qsfp_8_tx_p, + output wire logic [3:0] qsfp_8_tx_n, + input wire logic [3:0] qsfp_8_rx_p, + input wire logic [3:0] qsfp_8_rx_n, + input wire logic qsfp_8_mgt_refclk_p, + input wire logic qsfp_8_mgt_refclk_n, + output wire logic qsfp_8_resetl, + input wire logic qsfp_8_modprsl, + input wire logic qsfp_8_intl, + + output wire logic [3:0] qsfp_9_tx_p, + output wire logic [3:0] qsfp_9_tx_n, + input wire logic [3:0] qsfp_9_rx_p, + input wire logic [3:0] qsfp_9_rx_n, + input wire logic qsfp_9_mgt_refclk_p, + input wire logic qsfp_9_mgt_refclk_n, + output wire logic qsfp_9_resetl, + input wire logic qsfp_9_modprsl, + input wire logic qsfp_9_intl +); + +// Clock and reset + +wire ref_clk_ibufg; + +// Internal 125 MHz clock +wire clk_125mhz_mmcm_out; +wire clk_125mhz_int; +wire rst_125mhz_int; + +wire mmcm_rst = ~btn[0]; +wire mmcm_locked; +wire mmcm_clkfb; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +ref_clk_ibufg_inst ( + .O (ref_clk_ibufg), + .I (ref_clk_p), + .IB (ref_clk_n) +); + +// MMCM instance +MMCME4_BASE #( + // 200 MHz input + .CLKIN1_PERIOD(5.0), + .REF_JITTER1(0.010), + // 200 MHz input / 1 = 200 MHz PFD (range 10 MHz to 500 MHz) + .DIVCLK_DIVIDE(1), + // 200 MHz PFD * 5 = 1000 MHz VCO (range 800 MHz to 1600 MHz) + .CLKFBOUT_MULT_F(5), + .CLKFBOUT_PHASE(0), + // 1000 MHz / 8 = 125 MHz, 0 degrees + .CLKOUT0_DIVIDE_F(8), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + // Not used + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + // Not used + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + // Not used + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + // Not used + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT4_CASCADE("FALSE"), + // Not used + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + // Not used + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + + // optimized bandwidth + .BANDWIDTH("OPTIMIZED"), + // don't wait for lock during startup + .STARTUP_WAIT("FALSE") +) +clk_mmcm_inst ( + // 200 MHz input + .CLKIN1(ref_clk_ibufg), + // direct clkfb feeback + .CLKFBIN(mmcm_clkfb), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + // 125 MHz, 0 degrees + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + // Not used + .CLKOUT1(), + .CLKOUT1B(), + // Not used + .CLKOUT2(), + .CLKOUT2B(), + // Not used + .CLKOUT3(), + .CLKOUT3B(), + // Not used + .CLKOUT4(), + // Not used + .CLKOUT5(), + // Not used + .CLKOUT6(), + // reset input + .RST(mmcm_rst), + // don't power down + .PWRDWN(1'b0), + // locked output + .LOCKED(mmcm_locked) +); + +BUFG +clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int) +); + +taxi_sync_reset #( + .N(4) +) +sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int) +); + +// GPIO +wire btn_int; +wire [7:0] sw_int; + +taxi_debounce_switch #( + .WIDTH(9), + .N(4), + .RATE(125000) +) +debounce_switch_inst ( + .clk(clk_125mhz_int), + .rst(rst_125mhz_int), + .in({btn[1], + sw}), + .out({btn_int, + sw_int}) +); + +wire uart_txd_int; +wire uart_rts_int; + +taxi_sync_signal #( + .WIDTH(2), + .N(2) +) +sync_signal_inst ( + .clk(clk_125mhz_int), + .in({uart_txd, uart_rts}), + .out({uart_txd_int, uart_rts_int}) +); + +wire i2c_scl_i; +wire i2c_scl_o; +wire i2c_sda_i; +wire i2c_sda_o; + +assign i2c_scl_i = i2c_main_scl; +assign i2c_main_scl = i2c_scl_o ? 1'bz : 1'b0; +assign i2c_sda_i = i2c_main_sda; +assign i2c_main_sda = i2c_sda_o ? 1'bz : 1'b0; +assign i2c_main_rst_n = 1'b1; + +fpga_core +core_inst ( + /* + * Clock: 125MHz + * Synchronous reset + */ + .clk_125mhz(clk_125mhz_int), + .rst_125mhz(rst_125mhz_int), + + /* + * GPIO + */ + .btn(btn_int), + .sw(sw_int), + .led(led), + + /* + * I2C for board management + */ + .i2c_scl_i(i2c_scl_i), + .i2c_scl_o(i2c_scl_o), + .i2c_sda_i(i2c_sda_i), + .i2c_sda_o(i2c_sda_o), + + /* + * PLL + */ + .clk_gty2_fdec(clk_gty2_fdec), + .clk_gty2_finc(clk_gty2_finc), + .clk_gty2_intr_n(clk_gty2_intr_n), + .clk_gty2_lol_n(clk_gty2_lol_n), + .clk_gty2_oe_n(clk_gty2_oe_n), + .clk_gty2_sync_n(clk_gty2_sync_n), + .clk_gty2_rst_n(clk_gty2_rst_n), + + /* + * UART: 921600 bps, 8N1 + */ + .uart_rxd(uart_rxd), + .uart_txd(uart_txd_int), + .uart_rts(uart_rts_int), + .uart_cts(uart_cts), + .uart_rst_n(uart_rst_n), + .uart_suspend_n(uart_suspend_n), + + /* + * Ethernet: QSFP28 + */ + .eth_gty_tx_p({qsfp_9_tx_p, qsfp_8_tx_p, qsfp_7_tx_p, qsfp_6_tx_p, qsfp_5_tx_p, qsfp_4_tx_p, qsfp_3_tx_p, qsfp_2_tx_p, qsfp_1_tx_p}), + .eth_gty_tx_n({qsfp_9_tx_n, qsfp_8_tx_n, qsfp_7_tx_n, qsfp_6_tx_n, qsfp_5_tx_n, qsfp_4_tx_n, qsfp_3_tx_n, qsfp_2_tx_n, qsfp_1_tx_n}), + .eth_gty_rx_p({qsfp_9_rx_p, qsfp_8_rx_p, qsfp_7_rx_p, qsfp_6_rx_p, qsfp_5_rx_p, qsfp_4_rx_p, qsfp_3_rx_p, qsfp_2_rx_p, qsfp_1_rx_p}), + .eth_gty_rx_n({qsfp_9_rx_n, qsfp_8_rx_n, qsfp_7_rx_n, qsfp_6_rx_n, qsfp_5_rx_n, qsfp_4_rx_n, qsfp_3_rx_n, qsfp_2_rx_n, qsfp_1_rx_n}), + .eth_gty_mgt_refclk_p({qsfp_9_mgt_refclk_p, qsfp_8_mgt_refclk_p, qsfp_7_mgt_refclk_p, qsfp_6_mgt_refclk_p, qsfp_5_mgt_refclk_p, qsfp_4_mgt_refclk_p, qsfp_3_mgt_refclk_p, qsfp_2_mgt_refclk_p, qsfp_1_mgt_refclk_p}), + .eth_gty_mgt_refclk_n({qsfp_9_mgt_refclk_n, qsfp_8_mgt_refclk_n, qsfp_7_mgt_refclk_n, qsfp_6_mgt_refclk_n, qsfp_5_mgt_refclk_n, qsfp_4_mgt_refclk_n, qsfp_3_mgt_refclk_n, qsfp_2_mgt_refclk_n, qsfp_1_mgt_refclk_n}), + .eth_gty_mgt_refclk_out(), + + .eth_port_resetl({qsfp_9_resetl, qsfp_8_resetl, qsfp_7_resetl, qsfp_6_resetl, qsfp_5_resetl, qsfp_4_resetl, qsfp_3_resetl, qsfp_2_resetl, qsfp_1_resetl}), + .eth_port_modprsl({qsfp_9_modprsl, qsfp_8_modprsl, qsfp_7_modprsl, qsfp_6_modprsl, qsfp_5_modprsl, qsfp_4_modprsl, qsfp_3_modprsl, qsfp_2_modprsl, qsfp_1_modprsl}), + .eth_port_intl({qsfp_9_intl, qsfp_8_intl, qsfp_7_intl, qsfp_6_intl, qsfp_5_intl, qsfp_4_intl, qsfp_3_intl, qsfp_2_intl, qsfp_1_intl}) +); + +endmodule + +`resetall diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv new file mode 100644 index 0000000..6bc9212 --- /dev/null +++ b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv @@ -0,0 +1,674 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core # +( + parameter logic SIM = 1'b0, + parameter string VENDOR = "XILINX", + parameter string FAMILY = "virtexuplus", + parameter PORT_CNT = 9, + parameter GTY_QUAD_CNT = PORT_CNT, + parameter GTY_CNT = GTY_QUAD_CNT*4, + parameter GTY_CLK_CNT = GTY_QUAD_CNT +) +( + /* + * Clock: 125MHz + * Synchronous reset + */ + input wire logic clk_125mhz, + input wire logic rst_125mhz, + + /* + * GPIO + */ + input wire logic btn, + input wire logic [7:0] sw, + output wire logic [7:0] led, + + /* + * I2C for board management + */ + input wire logic i2c_scl_i, + output wire logic i2c_scl_o, + input wire logic i2c_sda_i, + output wire logic i2c_sda_o, + + /* + * PLL + */ + output wire logic clk_gty2_fdec, + output wire logic clk_gty2_finc, + input wire logic clk_gty2_intr_n, + input wire logic clk_gty2_lol_n, + output wire logic clk_gty2_oe_n, + output wire logic clk_gty2_sync_n, + output wire logic clk_gty2_rst_n, + + /* + * UART: 921600 bps, 8N1 + */ + output wire logic uart_rxd, + input wire logic uart_txd, + input wire logic uart_rts, + output wire logic uart_cts, + output wire logic uart_rst_n, + output wire logic uart_suspend_n, + + /* + * Ethernet: QSFP28 + */ + output wire logic [GTY_CNT-1:0] eth_gty_tx_p, + output wire logic [GTY_CNT-1:0] eth_gty_tx_n, + input wire logic [GTY_CNT-1:0] eth_gty_rx_p, + input wire logic [GTY_CNT-1:0] eth_gty_rx_n, + input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p, + input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n, + output wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_out, + + output wire logic [PORT_CNT-1:0] eth_port_resetl, + input wire logic [PORT_CNT-1:0] eth_port_modprsl, + input wire logic [PORT_CNT-1:0] eth_port_intl +); + +wire i2c_init_scl_i = i2c_scl_i; +wire i2c_init_scl_o; +wire i2c_init_sda_i = i2c_sda_i; +wire i2c_init_sda_o; + +wire i2c_xfcp_scl_i = i2c_scl_i; +wire i2c_xfcp_scl_o; +wire i2c_xfcp_sda_i = i2c_sda_i; +wire i2c_xfcp_sda_o; + +assign i2c_scl_o = i2c_init_scl_o & i2c_xfcp_scl_o; +assign i2c_sda_o = i2c_init_sda_o & i2c_xfcp_sda_o; + +// Si5341 init +taxi_axis_if #(.DATA_W(12)) si5341_i2c_cmd(); +taxi_axis_if #(.DATA_W(8)) si5341_i2c_tx(); +taxi_axis_if #(.DATA_W(8)) si5341_i2c_rx(); + +assign si5341_i2c_rx.tready = 1'b1; + +wire si5341_i2c_busy; + +taxi_i2c_master +si5341_i2c_master_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * Host interface + */ + .s_axis_cmd(si5341_i2c_cmd), + .s_axis_tx(si5341_i2c_tx), + .m_axis_rx(si5341_i2c_rx), + + /* + * I2C interface + */ + .scl_i(i2c_init_scl_i), + .scl_o(i2c_init_scl_o), + .sda_i(i2c_init_sda_i), + .sda_o(i2c_init_sda_o), + + /* + * Status + */ + .busy(), + .bus_control(), + .bus_active(), + .missed_ack(), + + /* + * Configuration + */ + .prescale(SIM ? 32 : 312), + .stop_on_idle(1) +); + +si5341_i2c_init #( + .SIM_SPEEDUP(SIM) +) +si5341_i2c_init_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * I2C master interface + */ + .m_axis_cmd(si5341_i2c_cmd), + .m_axis_tx(si5341_i2c_tx), + + /* + * Status + */ + .busy(si5341_i2c_busy), + + /* + * Configuration + */ + .start(1'b1) +); + +assign clk_gty2_fdec = 1'b0; +assign clk_gty2_finc = 1'b0; +assign clk_gty2_oe_n = 1'b0; +assign clk_gty2_sync_n = 1'b1; +assign clk_gty2_rst_n = !rst_125mhz; + +// XFCP +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us(); + +assign uart_cts = 1'b1; +assign uart_rst_n = 1'b1; +assign uart_suspend_n = 1'b1; + +taxi_xfcp_if_uart #( + .TX_FIFO_DEPTH(512), + .RX_FIFO_DEPTH(512) +) +xfcp_if_uart_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * UART interface + */ + .uart_rxd(uart_txd), + .uart_txd(uart_rxd), + + /* + * XFCP downstream interface + */ + .xfcp_dsp_ds(xfcp_ds), + .xfcp_dsp_us(xfcp_us), + + /* + * Configuration + */ + .prescale(16'(125000000/921600)) +); + +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[2](), xfcp_sw_us[2](); + +taxi_xfcp_switch #( + .XFCP_ID_STR("HTG-9200"), + .XFCP_EXT_ID(0), + .XFCP_EXT_ID_STR("Taxi example"), + .PORTS($size(xfcp_sw_us)) +) +xfcp_sw_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_ds), + .xfcp_usp_us(xfcp_us), + + /* + * XFCP downstream ports + */ + .xfcp_dsp_ds(xfcp_sw_ds), + .xfcp_dsp_us(xfcp_sw_us) +); + +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(11)) axis_stat(); + +taxi_xfcp_mod_stats #( + .XFCP_ID_STR("Statistics"), + .XFCP_EXT_ID(0), + .XFCP_EXT_ID_STR(""), + .STAT_COUNT_W(64), + .STAT_PIPELINE(2) +) +xfcp_stats_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_sw_ds[0]), + .xfcp_usp_us(xfcp_sw_us[0]), + + /* + * Statistics increment input + */ + .s_axis_stat(axis_stat) +); + +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(axis_stat.ID_W)) axis_eth_stat[GTY_QUAD_CNT](); + +taxi_axis_arb_mux #( + .S_COUNT($size(axis_eth_stat)), + .UPDATE_TID(1'b0), + .ARB_ROUND_ROBIN(1'b1), + .ARB_LSB_HIGH_PRIO(1'b0) +) +stat_mux_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * AXI4-Stream inputs (sink) + */ + .s_axis(axis_eth_stat), + + /* + * AXI4-Stream output (source) + */ + .m_axis(axis_stat) +); + +taxi_xfcp_mod_i2c_master #( + .DEFAULT_PRESCALE(16'(125000000/400000/4)) +) +xfcp_mod_i2c_inst ( + .clk(clk_125mhz), + .rst(rst_125mhz), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_sw_ds[1]), + .xfcp_usp_us(xfcp_sw_us[1]), + + /* + * I2C interface + */ + .i2c_scl_i(i2c_xfcp_scl_i), + .i2c_scl_o(i2c_xfcp_scl_o), + .i2c_sda_i(i2c_xfcp_sda_i), + .i2c_sda_o(i2c_xfcp_sda_o) +); + +// Ethernet +wire eth_reset = SIM ? 1'b0 : (si5341_i2c_busy || !clk_gty2_lol_n); +assign eth_port_resetl = {PORT_CNT{~eth_reset}}; + +wire [GTY_CNT-1:0] eth_gty_tx_clk; +wire [GTY_CNT-1:0] eth_gty_tx_rst; +taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT](); +taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT](); + +wire [GTY_CNT-1:0] eth_gty_rx_clk; +wire [GTY_CNT-1:0] eth_gty_rx_rst; +taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT](); + +wire [GTY_CNT-1:0] eth_gty_rx_status; + +wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood; + +wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk; +wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg; + +wire [GTY_CLK_CNT-1:0] eth_gty_rst; + +for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk + + wire eth_gty_mgt_refclk_int; + + if (SIM) begin + + assign eth_gty_mgt_refclk[n] = eth_gty_mgt_refclk_p[n]; + assign eth_gty_mgt_refclk_int = eth_gty_mgt_refclk_p[n]; + assign eth_gty_mgt_refclk_bufg[n] = eth_gty_mgt_refclk_int; + + end else begin + + IBUFDS_GTE4 ibufds_gte4_eth_gty_mgt_refclk_inst ( + .I (eth_gty_mgt_refclk_p[n]), + .IB (eth_gty_mgt_refclk_n[n]), + .CEB (1'b0), + .O (eth_gty_mgt_refclk[n]), + .ODIV2 (eth_gty_mgt_refclk_int) + ); + + BUFG_GT bufg_gt_eth_gty_mgt_refclk_inst ( + .CE (ð_gty_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (eth_gty_mgt_refclk_int), + .O (eth_gty_mgt_refclk_bufg[n]) + ); + + end + + assign eth_gty_mgt_refclk_out[n] = eth_gty_mgt_refclk_bufg[n]; + + taxi_sync_reset #( + .N(4) + ) + qsfp_sync_reset_inst ( + .clk(eth_gty_mgt_refclk_bufg[n]), + .rst(rst_125mhz || eth_reset), + .out(eth_gty_rst[n]) + ); + +end + +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP3[4] = '{"QSFP3.1", "QSFP3.2", "QSFP3.3", "QSFP3.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP4[4] = '{"QSFP4.1", "QSFP4.2", "QSFP4.3", "QSFP4.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP5[4] = '{"QSFP5.1", "QSFP5.2", "QSFP5.3", "QSFP5.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP6[4] = '{"QSFP6.1", "QSFP6.2", "QSFP6.3", "QSFP6.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP7[4] = '{"QSFP7.1", "QSFP7.2", "QSFP7.3", "QSFP7.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP8[4] = '{"QSFP8.1", "QSFP8.2", "QSFP8.3", "QSFP8.4"}; +localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP9[4] = '{"QSFP9.1", "QSFP9.2", "QSFP9.3", "QSFP9.4"}; + +for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad + + localparam CLK = n; + localparam CNT = 4; + + taxi_eth_mac_25g_us #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + + .CNT(CNT), + + // GT config + .CFG_LOW_LATENCY(1), + + // GT type + .GT_TYPE("GTY"), + + // PHY parameters + .PADDING_EN(1'b1), + .DIC_EN(1'b1), + .MIN_FRAME_LEN(64), + .PTP_TS_EN(1'b0), + .PTP_TS_FMT_TOD(1'b1), + .PTP_TS_W(96), + .PRBS31_EN(1'b0), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/6.4), + .STAT_EN(1), + .STAT_TX_LEVEL(1), + .STAT_RX_LEVEL(1), + .STAT_ID_BASE(n*CNT*(16+16)), + .STAT_UPDATE_PERIOD(1024), + .STAT_STR_EN(1), + .STAT_PREFIX_STR( + n == 0 ? STAT_PREFIX_STR_QSFP1 : + n == 1 ? STAT_PREFIX_STR_QSFP2 : + n == 2 ? STAT_PREFIX_STR_QSFP3 : + n == 3 ? STAT_PREFIX_STR_QSFP4 : + n == 4 ? STAT_PREFIX_STR_QSFP5 : + n == 5 ? STAT_PREFIX_STR_QSFP6 : + n == 6 ? STAT_PREFIX_STR_QSFP7 : + n == 7 ? STAT_PREFIX_STR_QSFP8 : + STAT_PREFIX_STR_QSFP9 + ) + ) + mac_inst ( + .xcvr_ctrl_clk(clk_125mhz), + .xcvr_ctrl_rst(eth_gty_rst[CLK]), + + /* + * Common + */ + .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]), + .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]), + .xcvr_qpll0pd_in(1'b0), + .xcvr_qpll0reset_in(1'b0), + .xcvr_qpll0pcierate_in(3'd0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[CLK]), + .xcvr_qpll1pd_in(1'b0), + .xcvr_qpll1reset_in(1'b0), + .xcvr_qpll1pcierate_in(3'd0), + .xcvr_qpll1lock_out(), + .xcvr_qpll1clk_out(), + .xcvr_qpll1refclk_out(), + + /* + * Serial data + */ + .xcvr_txp(eth_gty_tx_p[n*CNT +: CNT]), + .xcvr_txn(eth_gty_tx_n[n*CNT +: CNT]), + .xcvr_rxp(eth_gty_rx_p[n*CNT +: CNT]), + .xcvr_rxn(eth_gty_rx_n[n*CNT +: CNT]), + + /* + * MAC clocks + */ + .rx_clk(eth_gty_rx_clk[n*CNT +: CNT]), + .rx_rst_in('0), + .rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]), + .tx_clk(eth_gty_tx_clk[n*CNT +: CNT]), + .tx_rst_in('0), + .tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]), + .ptp_sample_clk('0), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(eth_gty_axis_tx[n*CNT +: CNT]), + .m_axis_tx_cpl(eth_gty_axis_tx_cpl[n*CNT +: CNT]), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(eth_gty_axis_rx[n*CNT +: CNT]), + + /* + * PTP clock + */ + .tx_ptp_ts('{CNT{'0}}), + .tx_ptp_ts_step('0), + .rx_ptp_ts('{CNT{'0}}), + .rx_ptp_ts_step('0), + + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + .tx_lfc_req('0), + .tx_lfc_resend('0), + .rx_lfc_en('0), + .rx_lfc_req(), + .rx_lfc_ack('0), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + .tx_pfc_req('{CNT{'0}}), + .tx_pfc_resend('0), + .rx_pfc_en('{CNT{'0}}), + .rx_pfc_req(), + .rx_pfc_ack('{CNT{'0}}), + + /* + * Pause interface + */ + .tx_lfc_pause_en('0), + .tx_pause_req('0), + .tx_pause_ack(), + + /* + * Statistics + */ + .stat_clk(clk_125mhz), + .stat_rst(rst_125mhz), + .m_axis_stat(axis_eth_stat[n]), + + /* + * Status + */ + .tx_start_packet(), + .stat_tx_byte(), + .stat_tx_pkt_len(), + .stat_tx_pkt_ucast(), + .stat_tx_pkt_mcast(), + .stat_tx_pkt_bcast(), + .stat_tx_pkt_vlan(), + .stat_tx_pkt_good(), + .stat_tx_pkt_bad(), + .stat_tx_err_oversize(), + .stat_tx_err_user(), + .stat_tx_err_underflow(), + .rx_start_packet(), + .rx_error_count(), + .rx_block_lock(), + .rx_high_ber(), + .rx_status(eth_gty_rx_status[n*CNT +: CNT]), + .stat_rx_byte(), + .stat_rx_pkt_len(), + .stat_rx_pkt_fragment(), + .stat_rx_pkt_jabber(), + .stat_rx_pkt_ucast(), + .stat_rx_pkt_mcast(), + .stat_rx_pkt_bcast(), + .stat_rx_pkt_vlan(), + .stat_rx_pkt_good(), + .stat_rx_pkt_bad(), + .stat_rx_err_oversize(), + .stat_rx_err_bad_fcs(), + .stat_rx_err_bad_block(), + .stat_rx_err_framing(), + .stat_rx_err_preamble(), + .stat_rx_fifo_drop('0), + .stat_tx_mcf(), + .stat_rx_mcf(), + .stat_tx_lfc_pkt(), + .stat_tx_lfc_xon(), + .stat_tx_lfc_xoff(), + .stat_tx_lfc_paused(), + .stat_tx_pfc_pkt(), + .stat_tx_pfc_xon(), + .stat_tx_pfc_xoff(), + .stat_tx_pfc_paused(), + .stat_rx_lfc_pkt(), + .stat_rx_lfc_xon(), + .stat_rx_lfc_xoff(), + .stat_rx_lfc_paused(), + .stat_rx_pfc_pkt(), + .stat_rx_pfc_xon(), + .stat_rx_pfc_xoff(), + .stat_rx_pfc_paused(), + + /* + * Configuration + */ + .cfg_tx_max_pkt_len('{CNT{16'd9218}}), + .cfg_tx_ifg('{CNT{8'd12}}), + .cfg_tx_enable('1), + .cfg_rx_max_pkt_len('{CNT{16'd9218}}), + .cfg_rx_enable('1), + .cfg_tx_prbs31_enable('0), + .cfg_rx_prbs31_enable('0), + .cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}), + .cfg_mcf_rx_check_eth_dst_mcast('1), + .cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}), + .cfg_mcf_rx_check_eth_dst_ucast('0), + .cfg_mcf_rx_eth_src('{CNT{48'd0}}), + .cfg_mcf_rx_check_eth_src('0), + .cfg_mcf_rx_eth_type('{CNT{16'h8808}}), + .cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}), + .cfg_mcf_rx_check_opcode_lfc('1), + .cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}), + .cfg_mcf_rx_check_opcode_pfc('1), + .cfg_mcf_rx_forward('0), + .cfg_mcf_rx_enable('0), + .cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}), + .cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}), + .cfg_tx_lfc_eth_type('{CNT{16'h8808}}), + .cfg_tx_lfc_opcode('{CNT{16'h0001}}), + .cfg_tx_lfc_en('0), + .cfg_tx_lfc_quanta('{CNT{16'hffff}}), + .cfg_tx_lfc_refresh('{CNT{16'h7fff}}), + .cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}), + .cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}), + .cfg_tx_pfc_eth_type('{CNT{16'h8808}}), + .cfg_tx_pfc_opcode('{CNT{16'h0101}}), + .cfg_tx_pfc_en('0), + .cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}), + .cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}), + .cfg_rx_lfc_opcode('{CNT{16'h0001}}), + .cfg_rx_lfc_en('0), + .cfg_rx_pfc_opcode('{CNT{16'h0101}}), + .cfg_rx_pfc_en('0) + ); + +end + +for (genvar n = 0; n < GTY_CNT; n = n + 1) begin : gty_ch + + taxi_axis_async_fifo #( + .DEPTH(16384), + .RAM_PIPELINE(2), + .FRAME_FIFO(1), + .USER_BAD_FRAME_VALUE(1'b1), + .USER_BAD_FRAME_MASK(1'b1), + .DROP_OVERSIZE_FRAME(1), + .DROP_BAD_FRAME(1), + .DROP_WHEN_FULL(1) + ) + ch_fifo ( + /* + * AXI4-Stream input (sink) + */ + .s_clk(eth_gty_rx_clk[n]), + .s_rst(eth_gty_rx_rst[n]), + .s_axis(eth_gty_axis_rx[n]), + + /* + * AXI4-Stream output (source) + */ + .m_clk(eth_gty_tx_clk[n]), + .m_rst(eth_gty_tx_rst[n]), + .m_axis(eth_gty_axis_tx[n]), + + /* + * Pause + */ + .s_pause_req(1'b0), + .s_pause_ack(), + .m_pause_req(1'b0), + .m_pause_ack(), + + /* + * Status + */ + .s_status_depth(), + .s_status_depth_commit(), + .s_status_overflow(), + .s_status_bad_frame(), + .s_status_good_frame(), + .m_status_depth(), + .m_status_depth_commit(), + .m_status_overflow(), + .m_status_bad_frame(), + .m_status_good_frame() + ); + +end + +endmodule + +`resetall diff --git a/src/eth/example/HTG9200/fpga/tb/fpga_core/Makefile b/src/eth/example/HTG9200/fpga/tb/fpga_core/Makefile new file mode 100644 index 0000000..eac873b --- /dev/null +++ b/src/eth/example/HTG9200/fpga/tb/fpga_core/Makefile @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = fpga_core +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/../pll/si5341_i2c_init.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_i2c_master.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv +VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_SIM := "1'b1" +export PARAM_VENDOR := "\"XILINX\"" +export PARAM_FAMILY := "\"virtexuplus\"" +export PARAM_PORT_CNT := 9 +export PARAM_GTY_QUAD_CNT := $(PARAM_PORT_CNT) +export PARAM_GTY_CNT := $(shell echo $$(( 4 * $(PARAM_GTY_QUAD_CNT) ))) +export PARAM_GTY_CLK_CNT := $(PARAM_GTY_QUAD_CNT) + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/eth/example/HTG9200/fpga/tb/fpga_core/baser.py b/src/eth/example/HTG9200/fpga/tb/fpga_core/baser.py new file mode 120000 index 0000000..946b03b --- /dev/null +++ b/src/eth/example/HTG9200/fpga/tb/fpga_core/baser.py @@ -0,0 +1 @@ +../../lib/taxi/src/eth/tb/baser.py \ No newline at end of file diff --git a/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py new file mode 100644 index 0000000..3a1c49c --- /dev/null +++ b/src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,254 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: MIT +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import logging +import os +import sys + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer, Combine + +from cocotbext.eth import XgmiiFrame +from cocotbext.uart import UartSource, UartSink + +try: + from baser import BaseRSerdesSource, BaseRSerdesSink +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + from baser import BaseRSerdesSource, BaseRSerdesSink + finally: + del sys.path[0] + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start()) + + self.uart_source = UartSource(dut.uart_rxd, baud=921600, bits=8, stop_bits=1) + self.uart_sink = UartSink(dut.uart_txd, baud=921600, bits=8, stop_bits=1) + + self.qsfp_sources = [] + self.qsfp_sinks = [] + + for inst in dut.gty_quad: + for ch in inst.mac_inst.ch: + gt_inst = ch.ch_inst.gt.gt_inst + + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) + else: + clk = 2.56 + gbx_cfg = None + + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) + + dut.i2c_scl_i.setimmediatevalue(1) + dut.i2c_sda_i.setimmediatevalue(1) + dut.clk_gty2_intr_n.setimmediatevalue(1) + dut.clk_gty2_lol_n.setimmediatevalue(1) + dut.sw.setimmediatevalue(0) + dut.eth_port_modprsl.setimmediatevalue(0) + dut.eth_port_intl.setimmediatevalue(0) + + cocotb.start_soon(self._run_refclk()) + + async def init(self): + + self.dut.rst_125mhz.setimmediatevalue(0) + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + self.dut.rst_125mhz.value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + self.dut.rst_125mhz.value = 0 + + for k in range(10): + await RisingEdge(self.dut.clk_125mhz) + + async def _run_refclk(self): + t = Timer(3.2, 'ns') + val = 2**len(self.dut.eth_gty_mgt_refclk_p)-1 + while True: + self.dut.eth_gty_mgt_refclk_p.value = val + await t + self.dut.eth_gty_mgt_refclk_p.value = 0 + await t + + +async def mac_test(tb, source, sink): + tb.log.info("Test MAC") + + tb.log.info("Wait for block lock") + for k in range(1200): + await RisingEdge(tb.dut.clk_125mhz) + + tb.log.info("Multiple small packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] + + for p in pkts: + await source.send(XgmiiFrame.from_payload(p)) + + for k in range(count): + rx_frame = await sink.recv() + + tb.log.info("RX frame: %s", rx_frame) + + assert rx_frame.get_payload() == pkts[k] + assert rx_frame.check_fcs() + + tb.log.info("Multiple large packets") + + count = 32 + + pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] + + for p in pkts: + await source.send(XgmiiFrame.from_payload(p)) + + for k in range(count): + rx_frame = await sink.recv() + + tb.log.info("RX frame: %s", rx_frame) + + assert rx_frame.get_payload() == pkts[k] + assert rx_frame.check_fcs() + + tb.log.info("MAC test done") + + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tests = [] + + for k in range(len(tb.qsfp_sources)): + tb.log.info("Start QSFP %d MAC loopback test", k) + + tests.append(cocotb.start_soon(mac_test(tb, tb.qsfp_sources[k], tb.qsfp_sinks[k]))) + + await Combine(*tests) + + await RisingEdge(dut.clk_125mhz) + await RisingEdge(dut.clk_125mhz) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "..", "pll", "si5341_i2c_init.sv"), + os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"), + os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_i2c_master.f"), + os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_async_fifo.f"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"), + os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"), + os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['SIM'] = "1'b1" + parameters['VENDOR'] = "\"XILINX\"" + parameters['FAMILY'] = "\"virtexuplus\"" + parameters['PORT_CNT'] = 9 + parameters['GTY_QUAD_CNT'] = parameters['PORT_CNT'] + parameters['GTY_CNT'] = parameters['GTY_QUAD_CNT']*4 + parameters['GTY_CLK_CNT'] = parameters['GTY_QUAD_CNT'] + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + )