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axis: Add AXI stream combination async FIFO/adapter module and testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-02-06 00:52:04 -08:00
parent b1dcd8c6a2
commit d52aa2f97e
5 changed files with 1201 additions and 0 deletions
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rtl/axis/taxi_axis_async_fifo_adapter.f Normal file
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taxi_axis_async_fifo_adapter.sv
taxi_axis_async_fifo.sv
taxi_axis_adapter.sv
taxi_axis_if.sv

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rtl/axis/taxi_axis_async_fifo_adapter.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2019-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream asynchronous FIFO with width converter
*/
module taxi_axis_async_fifo_adapter #
(
// FIFO depth in words
// KEEP_W words per cycle if KEEP_EN set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// number of RAM pipeline registers in FIFO
parameter RAM_PIPELINE = 1,
// use output FIFO
// When set, the RAM read enable and pipeline clock enables are removed
parameter logic OUTPUT_FIFO_EN = 1'b0,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_EN set
parameter logic FRAME_FIFO = 1'b0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames larger than FIFO
// Requires FRAME_FIFO set
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
// Drop frames marked bad
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter logic DROP_BAD_FRAME = 1'b0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO and DROP_OVERSIZE_FRAME set
parameter logic DROP_WHEN_FULL = 1'b0,
// Mark incoming frames as bad frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO to be clear
parameter logic MARK_WHEN_FULL = 1'b0,
// Enable pause request input
parameter logic PAUSE_EN = 1'b0,
// Pause between frames
parameter logic FRAME_PAUSE = FRAME_FIFO
)
(
/*
* AXI4-Stream input (sink)
*/
input wire logic s_clk,
input wire logic s_rst,
taxi_axis_if.snk s_axis,
/*
* AXI4-Stream output (source)
*/
input wire logic m_clk,
input wire logic m_rst,
taxi_axis_if.src m_axis,
/*
* Pause
*/
input wire logic s_pause_req = 1'b0,
output wire logic s_pause_ack,
input wire logic m_pause_req = 1'b0,
output wire logic m_pause_ack,
/*
* Status
*/
output wire logic [$clog2(DEPTH):0] s_status_depth,
output wire logic [$clog2(DEPTH):0] s_status_depth_commit,
output wire logic s_status_overflow,
output wire logic s_status_bad_frame,
output wire logic s_status_good_frame,
output wire logic [$clog2(DEPTH):0] m_status_depth,
output wire logic [$clog2(DEPTH):0] m_status_depth_commit,
output wire logic m_status_overflow,
output wire logic m_status_bad_frame,
output wire logic m_status_good_frame
);
// extract parameters
localparam S_DATA_W = s_axis.DATA_W;
localparam logic S_KEEP_EN = s_axis.KEEP_EN;
localparam S_KEEP_W = s_axis.KEEP_W;
localparam logic S_STRB_EN = s_axis.STRB_EN;
localparam M_DATA_W = m_axis.DATA_W;
localparam logic M_KEEP_EN = m_axis.KEEP_EN;
localparam M_KEEP_W = m_axis.KEEP_W;
localparam logic M_STRB_EN = m_axis.STRB_EN;
// force keep width to 1 when disabled
localparam S_BYTE_LANES = S_KEEP_EN ? S_KEEP_W : 1;
localparam M_BYTE_LANES = M_KEEP_EN ? M_KEEP_W : 1;
// bus byte sizes (must be identical)
localparam S_BYTE_SIZE = S_DATA_W / S_BYTE_LANES;
localparam M_BYTE_SIZE = M_DATA_W / M_BYTE_LANES;
// output bus is wider
localparam EXPAND_BUS = M_BYTE_LANES > S_BYTE_LANES;
// total data and keep widths
localparam DATA_W = EXPAND_BUS ? M_DATA_W : S_DATA_W;
localparam KEEP_W = EXPAND_BUS ? M_BYTE_LANES : S_BYTE_LANES;
localparam KEEP_EN = EXPAND_BUS ? M_KEEP_EN : S_KEEP_EN;
localparam STRB_EN = M_STRB_EN && S_STRB_EN;
// check configuration
if (S_BYTE_SIZE * S_BYTE_LANES != S_DATA_W)
$fatal(0, "Error: input data width not evenly divisible (instance %m)");
if (M_BYTE_SIZE * M_BYTE_LANES != M_DATA_W)
$fatal(0, "Error: output data width not evenly divisible (instance %m)");
if (S_BYTE_SIZE != M_BYTE_SIZE)
$fatal(0, "Error: byte size mismatch (instance %m)");
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(s_axis.STRB_EN),
.LAST_EN(s_axis.LAST_EN),
.ID_EN(s_axis.ID_EN),
.ID_W(s_axis.ID_W),
.DEST_EN(s_axis.DEST_EN),
.DEST_W(s_axis.DEST_W),
.USER_EN(s_axis.USER_EN),
.USER_W(s_axis.USER_W)
) axis_pre_fifo();
taxi_axis_if #(
.DATA_W(DATA_W),
.KEEP_EN(KEEP_EN),
.KEEP_W(KEEP_W),
.STRB_EN(m_axis.STRB_EN),
.LAST_EN(m_axis.LAST_EN),
.ID_EN(m_axis.ID_EN),
.ID_W(m_axis.ID_W),
.DEST_EN(m_axis.DEST_EN),
.DEST_W(m_axis.DEST_W),
.USER_EN(m_axis.USER_EN),
.USER_W(m_axis.USER_W)
) axis_post_fifo();
taxi_axis_adapter
pre_fifo_adapter_inst (
.clk(s_clk),
.rst(s_rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_axis(axis_pre_fifo)
);
taxi_axis_async_fifo #(
.DEPTH(DEPTH),
.RAM_PIPELINE(RAM_PIPELINE),
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.MARK_WHEN_FULL(MARK_WHEN_FULL),
.PAUSE_EN(PAUSE_EN),
.FRAME_PAUSE(FRAME_PAUSE)
)
fifo_inst (
/*
* AXI4-Stream input (sink)
*/
.s_clk(s_clk),
.s_rst(s_rst),
.s_axis(axis_pre_fifo),
/*
* AXI4-Stream output (source)
*/
.m_clk(m_clk),
.m_rst(m_rst),
.m_axis(axis_post_fifo),
/*
* Pause
*/
.s_pause_req(s_pause_req),
.s_pause_ack(s_pause_ack),
.m_pause_req(m_pause_req),
.m_pause_ack(m_pause_ack),
/*
* Status
*/
.s_status_depth(s_status_depth),
.s_status_depth_commit(s_status_depth_commit),
.s_status_overflow(s_status_overflow),
.s_status_bad_frame(s_status_bad_frame),
.s_status_good_frame(s_status_good_frame),
.m_status_depth(m_status_depth),
.m_status_depth_commit(m_status_depth_commit),
.m_status_overflow(m_status_overflow),
.m_status_bad_frame(m_status_bad_frame),
.m_status_good_frame(m_status_good_frame)
);
taxi_axis_adapter
post_fifo_adapter_inst (
.clk(m_clk),
.rst(m_rst),
/*
* AXI4-Stream input (sink)
*/
.s_axis(axis_post_fifo),
/*
* AXI4-Stream output (source)
*/
.m_axis(m_axis)
);
endmodule
`resetall

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tb/axis/taxi_axis_async_fifo_adapter/Makefile Normal file
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# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2021-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
DUT = taxi_axis_async_fifo_adapter
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += ../../../rtl/axis/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_S_DATA_W := 8
export PARAM_S_KEEP_EN := $(shell echo $$(( $(PARAM_S_DATA_W) > 8 )))
export PARAM_S_KEEP_W := $(shell echo $$(( ( $(PARAM_S_DATA_W) + 7 ) / 8 )))
export PARAM_S_STRB_EN := 0
export PARAM_M_DATA_W := 8
export PARAM_M_KEEP_EN := $(shell echo $$(( $(PARAM_M_DATA_W) > 8 )))
export PARAM_M_KEEP_W := $(shell echo $$(( ( $(PARAM_M_DATA_W) + 7 ) / 8 )))
export PARAM_M_STRB_EN := $(PARAM_S_STRB_EN)
export PARAM_DEPTH := $(shell echo $$(( 1024 * ($(PARAM_S_KEEP_W) > $(PARAM_M_KEEP_W) ? $(PARAM_S_KEEP_W) : $(PARAM_M_KEEP_W)) )))
export PARAM_ID_EN := 1
export PARAM_ID_W := 8
export PARAM_DEST_EN := 1
export PARAM_DEST_W := 8
export PARAM_USER_EN := 1
export PARAM_USER_W := 1
export PARAM_RAM_PIPELINE := 1
export PARAM_OUTPUT_FIFO_EN := 0
export PARAM_FRAME_FIFO := 1
export PARAM_USER_BAD_FRAME_VALUE := 1
export PARAM_USER_BAD_FRAME_MASK := 1
export PARAM_DROP_OVERSIZE_FRAME := $(PARAM_FRAME_FIFO)
export PARAM_DROP_BAD_FRAME := $(PARAM_DROP_OVERSIZE_FRAME)
export PARAM_DROP_WHEN_FULL := 0
export PARAM_MARK_WHEN_FULL := 0
export PARAM_PAUSE_EN := 1
export PARAM_FRAME_PAUSE := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

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tb/axis/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.py Normal file
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#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2021-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.regression import TestFactory
from cocotbext.axi import AxiStreamBus, AxiStreamFrame, AxiStreamSource, AxiStreamSink
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
s_clk = int(os.getenv("S_CLK_PERIOD", "10"))
m_clk = int(os.getenv("M_CLK_PERIOD", "11"))
cocotb.start_soon(Clock(dut.s_clk, s_clk, units="ns").start())
cocotb.start_soon(Clock(dut.m_clk, m_clk, units="ns").start())
self.source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis), dut.s_clk, dut.s_rst)
self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis), dut.m_clk, dut.m_rst)
dut.s_pause_req.setimmediatevalue(0)
dut.m_pause_req.setimmediatevalue(0)
def set_idle_generator(self, generator=None):
if generator:
self.source.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.sink.set_pause_generator(generator())
async def reset(self):
self.dut.m_rst.setimmediatevalue(0)
self.dut.s_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.s_clk)
self.dut.m_rst.value = 1
self.dut.s_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.s_clk)
self.dut.m_rst.value = 0
self.dut.s_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.s_clk)
async def reset_source(self):
self.dut.s_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.s_clk)
self.dut.s_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.s_clk)
self.dut.s_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.s_clk)
async def reset_sink(self):
self.dut.m_rst.setimmediatevalue(0)
for k in range(10):
await RisingEdge(self.dut.m_clk)
self.dut.m_rst.value = 1
for k in range(10):
await RisingEdge(self.dut.m_clk)
self.dut.m_rst.value = 0
for k in range(10):
await RisingEdge(self.dut.m_clk)
async def run_test(dut, payload_lengths=None, payload_data=None, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for test_data in [payload_data(x) for x in payload_lengths()]:
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_tuser_assert(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data, tuser=1)
await tb.source.send(test_frame)
if int(dut.DROP_BAD_FRAME.value):
for k in range(64):
await RisingEdge(dut.s_clk)
else:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_init_sink_pause(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.s_clk)
tb.sink.pause = False
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_init_sink_pause_reset(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.s_clk)
await tb.reset()
tb.sink.pause = False
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_init_sink_pause_source_reset(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.s_clk)
await tb.reset_source()
tb.sink.pause = False
for k in range(64):
await RisingEdge(dut.s_clk)
rx_frame = await tb.sink.recv()
assert rx_frame.tuser
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_init_sink_pause_sink_reset(dut):
tb = TB(dut)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 32))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(64):
await RisingEdge(dut.s_clk)
await tb.reset_sink()
tb.sink.pause = False
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_shift_in_source_reset(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(8):
await RisingEdge(dut.s_clk)
await tb.reset_source()
for k in range(64):
await RisingEdge(dut.s_clk)
if int(dut.FRAME_FIFO.value):
assert tb.sink.empty()
else:
rx_frame = await tb.sink.recv()
assert rx_frame.tuser
assert tb.sink.empty()
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_shift_in_sink_reset(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range(8):
await RisingEdge(dut.s_clk)
await tb.reset_sink()
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_shift_out_source_reset(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
await RisingEdge(dut.m_axis.tvalid)
for k in range(8):
await RisingEdge(dut.s_clk)
await tb.reset_source()
for k in range(64):
await RisingEdge(dut.s_clk)
rx_frame = await tb.sink.recv()
assert rx_frame.tuser
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_shift_out_sink_reset(dut):
tb = TB(dut)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 256))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
await RisingEdge(dut.m_axis.tvalid)
for k in range(8):
await RisingEdge(dut.s_clk)
await tb.reset_sink()
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_pause(dut):
tb = TB(dut)
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
await tb.reset()
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), 16*byte_lanes))
test_frame = AxiStreamFrame(test_data)
for k in range(16):
await tb.source.send(test_frame)
for k in range(60):
await RisingEdge(dut.s_clk)
dut.m_pause_req.value = 1
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
dut.m_pause_req.value = 0
for k in range(60):
await RisingEdge(dut.s_clk)
dut.s_pause_req.value = 1
for k in range(64):
await RisingEdge(dut.s_clk)
assert tb.sink.idle()
dut.s_pause_req.value = 0
for k in range(16):
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_overflow(dut):
tb = TB(dut)
depth = int(dut.DEPTH.value)
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
await tb.reset()
tb.sink.pause = True
size = (16*byte_lanes)
count = depth*2 // size
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), size))
test_frame = AxiStreamFrame(test_data)
for k in range(count):
await tb.source.send(test_frame)
for k in range((depth//byte_lanes)*3):
await RisingEdge(dut.s_clk)
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
assert tb.source.idle()
else:
assert not tb.source.idle()
tb.sink.pause = False
if int(dut.DROP_WHEN_FULL.value) or int(dut.MARK_WHEN_FULL.value):
for k in range((depth//byte_lanes)*3):
await RisingEdge(dut.s_clk)
rx_count = 0
while not tb.sink.empty():
rx_frame = await tb.sink.recv()
if int(dut.MARK_WHEN_FULL.value) and rx_frame.tuser:
continue
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
rx_count += 1
assert rx_count < count
else:
for k in range(count):
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_test_oversize(dut):
tb = TB(dut)
depth = int(dut.DEPTH.value)
byte_lanes = min(tb.source.byte_lanes, tb.sink.byte_lanes)
await tb.reset()
tb.sink.pause = True
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), depth*2))
test_frame = AxiStreamFrame(test_data)
await tb.source.send(test_frame)
for k in range((depth//byte_lanes)*2):
await RisingEdge(dut.s_clk)
tb.sink.pause = False
if int(dut.DROP_OVERSIZE_FRAME.value):
for k in range((depth//byte_lanes)*2):
await RisingEdge(dut.s_clk)
else:
rx_frame = await tb.sink.recv()
if int(dut.MARK_WHEN_FULL.value):
assert rx_frame.tuser
else:
assert rx_frame.tdata == test_data
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
byte_lanes = max(tb.source.byte_lanes, tb.sink.byte_lanes)
id_count = 2**len(tb.source.bus.tid)
cur_id = 1
await tb.reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
test_frames = []
for k in range(512):
length = random.randint(1, byte_lanes*16)
test_data = bytearray(itertools.islice(itertools.cycle(range(256)), length))
test_frame = AxiStreamFrame(test_data)
test_frame.tid = cur_id
test_frame.tdest = cur_id
test_frames.append(test_frame)
await tb.source.send(test_frame)
cur_id = (cur_id + 1) % id_count
if dut.DROP_WHEN_FULL.value or dut.MARK_WHEN_FULL.value:
cycles = 0
while cycles < 100:
cycles += 1
if not tb.source.idle() or dut.s_axis.tvalid.value.integer or dut.m_axis.tvalid.value.integer or dut.m_status_depth.value.integer:
cycles = 0
await RisingEdge(dut.m_clk)
while not tb.sink.empty():
rx_frame = await tb.sink.recv()
if dut.MARK_WHEN_FULL.value and rx_frame.tuser:
continue
assert not rx_frame.tuser
while True:
test_frame = test_frames.pop(0)
if rx_frame.tid == test_frame.tid and rx_frame.tdest == test_frame.tdest and rx_frame.tdata == test_frame.tdata:
break
assert len(test_frames) < 512
else:
for test_frame in test_frames:
rx_frame = await tb.sink.recv()
assert rx_frame.tdata == test_frame.tdata
assert rx_frame.tid == test_frame.tid
assert rx_frame.tdest == test_frame.tdest
assert not rx_frame.tuser
assert tb.sink.empty()
await RisingEdge(dut.s_clk)
await RisingEdge(dut.s_clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
def size_list():
data_width = max(len(cocotb.top.m_axis.tdata), len(cocotb.top.s_axis.tdata))
byte_width = data_width // 8
return list(range(1, byte_width*4+1))+[512]+[1]*64
def incrementing_payload(length):
return bytearray(itertools.islice(itertools.cycle(range(256)), length))
if cocotb.SIM_NAME:
factory = TestFactory(run_test)
factory.add_option("payload_lengths", [size_list])
factory.add_option("payload_data", [incrementing_payload])
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
for test in [
run_test_tuser_assert,
run_test_init_sink_pause,
run_test_init_sink_pause_reset,
run_test_init_sink_pause_source_reset,
run_test_init_sink_pause_sink_reset,
run_test_shift_in_source_reset,
run_test_shift_in_sink_reset,
run_test_shift_out_source_reset,
run_test_shift_out_sink_reset,
run_test_pause,
run_test_overflow,
run_test_oversize
]:
factory = TestFactory(test)
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize(("frame_fifo", "drop_oversize_frame", "drop_bad_frame",
"drop_when_full", "mark_when_full"),
[(0, 0, 0, 0, 0), (1, 0, 0, 0, 0), (1, 1, 0, 0, 0), (1, 1, 1, 0, 0),
(1, 1, 1, 1, 0), (0, 0, 0, 0, 1)])
@pytest.mark.parametrize("m_data_w", [8, 16, 32])
@pytest.mark.parametrize("s_data_w", [8, 16, 32])
def test_taxi_axis_async_fifo_adapter(request, s_data_w, m_data_w,
frame_fifo, drop_oversize_frame, drop_bad_frame,
drop_when_full, mark_when_full):
dut = "taxi_axis_async_fifo_adapter"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, "axis", f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['S_DATA_W'] = s_data_w
parameters['S_KEEP_EN'] = int(parameters['S_DATA_W'] > 8)
parameters['S_KEEP_W'] = (parameters['S_DATA_W'] + 7) // 8
parameters['M_DATA_W'] = m_data_w
parameters['M_KEEP_EN'] = int(parameters['M_DATA_W'] > 8)
parameters['M_KEEP_W'] = (parameters['M_DATA_W'] + 7) // 8
parameters['DEPTH'] = 1024 * max(parameters['S_KEEP_W'], parameters['M_KEEP_W'])
parameters['ID_EN'] = 1
parameters['ID_W'] = 8
parameters['DEST_EN'] = 1
parameters['DEST_W'] = 8
parameters['USER_EN'] = 1
parameters['USER_W'] = 1
parameters['RAM_PIPELINE'] = 1
parameters['OUTPUT_FIFO_EN'] = 0
parameters['FRAME_FIFO'] = frame_fifo
parameters['USER_BAD_FRAME_VALUE'] = 1
parameters['USER_BAD_FRAME_MASK'] = 1
parameters['DROP_OVERSIZE_FRAME'] = drop_oversize_frame
parameters['DROP_BAD_FRAME'] = drop_bad_frame
parameters['DROP_WHEN_FULL'] = drop_when_full
parameters['MARK_WHEN_FULL'] = mark_when_full
parameters['PAUSE_EN'] = 1
parameters['FRAME_PAUSE'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

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@@ -0,0 +1,153 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream asynchronous FIFO with width converter testbench
*/
module test_taxi_axis_async_fifo_adapter #
(
/* verilator lint_off WIDTHTRUNC */
parameter DEPTH = 4096,
parameter S_DATA_W = 8,
parameter logic S_KEEP_EN = (S_DATA_W>8),
parameter S_KEEP_W = ((S_DATA_W+7)/8),
parameter logic S_STRB_EN = 0,
parameter M_DATA_W = 8,
parameter logic M_KEEP_EN = (M_DATA_W>8),
parameter M_KEEP_W = ((M_DATA_W+7)/8),
parameter logic M_STRB_EN = 0,
parameter logic ID_EN = 1'b0,
parameter ID_W = 8,
parameter logic DEST_EN = 1'b0,
parameter DEST_W = 8,
parameter logic USER_EN = 1'b1,
parameter USER_W = 1,
parameter RAM_PIPELINE = 1,
parameter logic OUTPUT_FIFO_EN = 1'b0,
parameter logic FRAME_FIFO = 1'b0,
parameter logic [USER_W-1:0] USER_BAD_FRAME_VALUE = 1'b1,
parameter logic [USER_W-1:0] USER_BAD_FRAME_MASK = 1'b1,
parameter logic DROP_OVERSIZE_FRAME = FRAME_FIFO,
parameter logic DROP_BAD_FRAME = 1'b0,
parameter logic DROP_WHEN_FULL = 1'b0,
parameter logic MARK_WHEN_FULL = 1'b0,
parameter logic PAUSE_EN = 1'b0,
parameter logic FRAME_PAUSE = FRAME_FIFO
/* verilator lint_on WIDTHTRUNC */
)
();
logic s_clk;
logic s_rst;
taxi_axis_if #(
.DATA_W(S_DATA_W),
.KEEP_EN(S_KEEP_EN),
.KEEP_W(S_KEEP_W),
.STRB_EN(S_STRB_EN),
.LAST_EN(1'b1),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) s_axis();
logic m_clk;
logic m_rst;
taxi_axis_if #(
.DATA_W(M_DATA_W),
.KEEP_EN(M_KEEP_EN),
.KEEP_W(M_KEEP_W),
.STRB_EN(M_STRB_EN),
.LAST_EN(1'b1),
.ID_EN(ID_EN),
.ID_W(ID_W),
.DEST_EN(DEST_EN),
.DEST_W(DEST_W),
.USER_EN(USER_EN),
.USER_W(USER_W)
) m_axis();
logic s_pause_req;
logic s_pause_ack;
logic m_pause_req;
logic m_pause_ack;
logic [$clog2(DEPTH):0] s_status_depth;
logic [$clog2(DEPTH):0] s_status_depth_commit;
logic s_status_overflow;
logic s_status_bad_frame;
logic s_status_good_frame;
logic [$clog2(DEPTH):0] m_status_depth;
logic [$clog2(DEPTH):0] m_status_depth_commit;
logic m_status_overflow;
logic m_status_bad_frame;
logic m_status_good_frame;
taxi_axis_async_fifo_adapter #(
.DEPTH(DEPTH),
.RAM_PIPELINE(RAM_PIPELINE),
.OUTPUT_FIFO_EN(OUTPUT_FIFO_EN),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_OVERSIZE_FRAME(DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.MARK_WHEN_FULL(MARK_WHEN_FULL),
.PAUSE_EN(PAUSE_EN),
.FRAME_PAUSE(FRAME_PAUSE)
)
uut (
/*
* AXI4-Stream input (sink)
*/
.s_clk(s_clk),
.s_rst(s_rst),
.s_axis(s_axis),
/*
* AXI4-Stream output (source)
*/
.m_clk(m_clk),
.m_rst(m_rst),
.m_axis(m_axis),
/*
* Pause
*/
.s_pause_req(s_pause_req),
.s_pause_ack(s_pause_ack),
.m_pause_req(m_pause_req),
.m_pause_ack(m_pause_ack),
/*
* Status
*/
.s_status_depth(s_status_depth),
.s_status_depth_commit(s_status_depth_commit),
.s_status_overflow(s_status_overflow),
.s_status_bad_frame(s_status_bad_frame),
.s_status_good_frame(s_status_good_frame),
.m_status_depth(m_status_depth),
.m_status_depth_commit(m_status_depth_commit),
.m_status_overflow(m_status_overflow),
.m_status_bad_frame(m_status_bad_frame),
.m_status_good_frame(m_status_good_frame)
);
endmodule
`resetall