diff --git a/README.md b/README.md
index df9c79a..643d70c 100644
--- a/README.md
+++ b/README.md
@@ -94,6 +94,7 @@ Example designs are provided for several different FPGA boards, showcasing many
 *  Digilent Arty A7 (Xilinx Artix 7 XC7A35T)
 *  Xilinx KC705 (Xilinx Kintex 7 XC7K325T)
 *  Xilinx KCU105 (Xilinx Kintex UltraScale XCKU040)
+*  Xilinx KR260 (Xilinx Kria K26 SoM / Zynq UltraScale+ XCK26)
 *  Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)
 
 ## Testing
diff --git a/example/KR260/fpga/README.md b/example/KR260/fpga/README.md
new file mode 100644
index 0000000..dd18826
--- /dev/null
+++ b/example/KR260/fpga/README.md
@@ -0,0 +1,31 @@
+# Taxi Example Design for KR260
+
+## Introduction
+
+This example design targets the Xilinx KR260 FPGA board.
+
+The design places looped-back MACs on the BASE-T ports and SFP+ cage, as well as a looped-back UART on on the USB UART connection.
+
+*  USB UART
+    *  Looped-back UART
+*  RJ-45 Ethernet ports with TI DP83867CSRGZ PHY
+    *  Looped-back MAC via RGMII
+*  SFP+ cage
+    *  Looped-back 1000BASE-X via Xilinx PCS/PMA core and GTH transceiver
+
+## Board details
+
+*  FPGA: xck26-sfvc784-2LV-c
+*  1000BASE-T PHY: Marvell 88E1111 via SGMII
+
+## How to build
+
+Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.
+
+## How to test
+
+Run `make program` to program the board with Vivado.
+
+To test the looped-back UART, use any serial terminal software like minicom, screen, etc.  The looped-back UART will echo typed text back without modification.
+
+To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback.  Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
diff --git a/example/KR260/fpga/common/vivado.mk b/example/KR260/fpga/common/vivado.mk
new file mode 100644
index 0000000..07c56e2
--- /dev/null
+++ b/example/KR260/fpga/common/vivado.mk
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: MIT
+###################################################################
+#
+# Xilinx Vivado FPGA Makefile
+#
+# Copyright (c) 2016-2025 Alex Forencich
+#
+###################################################################
+#
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - list of source files
+# INC_FILES - list of include files
+# XDC_FILES - list of timing constraint files
+# XCI_FILES - list of IP XCI files
+# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
+# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
+#
+# Note: both SYN_FILES and INC_FILES support file list files.  File list
+# files are files with a .f extension that contain a list of additional
+# files to include, one path relative to the .f file location per line.
+# The .f files are processed recursively, and then the complete file list
+# is de-duplicated, with later files in the list taking precedence.
+#
+# Example:
+#
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+#
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include $(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+XDC_FILES ?= $(PROJECT).xdc
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
+INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
+
+###################################################################
+# Main Targets
+#
+# all: build everything (fpga)
+# fpga: build FPGA config
+# vivado: open project in Vivado
+# tmpclean: remove intermediate files
+# clean: remove output files and project files
+# distclean: remove archived output files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+
+# create fresh project if Makefile or IP files have changed
+create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
+	for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+# source config TCL scripts if any source file has changed
+update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# output files (including potentially bit, bin, ltx, and xsa)
+$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
+	if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
diff --git a/example/KR260/fpga/eth_rgmii.xdc b/example/KR260/fpga/eth_rgmii.xdc
new file mode 100644
index 0000000..770f92b
--- /dev/null
+++ b/example/KR260/fpga/eth_rgmii.xdc
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# Ethernet constraints
+
+# IDELAY from PHY chip (RGMII)
+set_property DELAY_VALUE 0 [get_cells {phy2_rx_ctl_idelay phy2_rxd_idelay_bit[*].idelay_inst}]
+set_property DELAY_VALUE 0 [get_cells {phy3_rx_ctl_idelay phy3_rxd_idelay_bit[*].idelay_inst}]
+
+# MMCM phase (RGMII)
+set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
diff --git a/example/KR260/fpga/fpga.xdc b/example/KR260/fpga/fpga.xdc
new file mode 100644
index 0000000..2d9cf54
--- /dev/null
+++ b/example/KR260/fpga/fpga.xdc
@@ -0,0 +1,174 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# XDC constraints for the Xilinx KR260 board
+# part: xck26-sfvc784-2LV-c
+
+# General configuration
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+
+# System clocks
+# 25 MHz system clock
+set_property -dict {LOC C3   IOSTANDARD LVCMOS18} [get_ports clk_25mhz] ;# HPA_CLK0_P som240_1_a6
+create_clock -period 40.000 -name clk_25mhz [get_ports clk_25mhz]
+
+# 25 MHz system clock
+#set_property -dict {LOC L3 IOSTANDARD LVCMOS18} [get_ports clk_25mhz] ;# HPB_CLK0_P som240_2_d18
+#create_clock -period 40.000 -name clk_25mhz [get_ports clk_25mhz]
+
+# LEDs
+set_property -dict {LOC F8   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] ;# HPA14P som240_1_d13
+set_property -dict {LOC E8   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] ;# HPA14N som240_1_d14
+
+set_property -dict {LOC G8   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp_led[0]}] ;# HPA13P som240_1_a12
+set_property -dict {LOC F7   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp_led[1]}] ;# HPA13N som240_1_a13
+
+set_false_path -to [get_ports {led[*] sfp_led[*]}]
+set_output_delay 0 [get_ports {led[*] sfp_led[*]}]
+
+# PMOD1
+#set_property -dict {LOC H12  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] ;# J2.1 / HDA11 som240_1_a17
+#set_property -dict {LOC E10  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] ;# J2.3 / HDA12 som240_1_d20
+#set_property -dict {LOC D10  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] ;# J2.5 / HDA13 som240_1_d21
+#set_property -dict {LOC C11  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] ;# J2.7 / HDA14 som240_1_d22
+#set_property -dict {LOC B10  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] ;# J2.2 / HDA15 som240_1_b20
+#set_property -dict {LOC E12  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] ;# J2.4 / HDA16_CC som240_1_b21
+#set_property -dict {LOC D11  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] ;# J2.6 / HDA17 som240_1_b22
+#set_property -dict {LOC B11  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] ;# J2.8 / HDA18 som240_1_c22
+
+#set_false_path -to [get_ports {pmod1[*]}]
+#set_output_delay 0 [get_ports {pmod1[*]}]
+
+# PMOD2
+#set_property -dict {LOC J11  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[0]}] ;# J18.1 / HDA02 som240_1_d18
+#set_property -dict {LOC J10  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[1]}] ;# J18.3 / HDA03 som240_1_b16
+#set_property -dict {LOC K13  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[2]}] ;# J18.5 / HDA04 som240_1_b17
+#set_property -dict {LOC K12  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[3]}] ;# J18.7 / HDA05 som240_1_b18
+#set_property -dict {LOC H11  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[4]}] ;# J18.2 / HDA06 som240_1_c18
+#set_property -dict {LOC G10  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[5]}] ;# J18.4 / HDA07 som240_1_c19
+#set_property -dict {LOC F12  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[6]}] ;# J18.6 / HDA08_CC som240_1_c20
+#set_property -dict {LOC F11  IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod2[7]}] ;# J18.8 / HDA09 som240_1_a15
+
+#set_false_path -to [get_ports {pmod2[*]}]
+#set_output_delay 0 [get_ports {pmod2[*]}]
+
+# PMOD3
+#set_property -dict {LOC AE12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[0]}] ;# J19.1 / HDB00_CC som240_2_d44
+#set_property -dict {LOC AF12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[1]}] ;# J19.3 / HDB01 som240_2_d45
+#set_property -dict {LOC AG10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[2]}] ;# J19.5 / HDB02 som240_2_d46
+#set_property -dict {LOC AH10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[3]}] ;# J19.7 / HDB03 som240_2_d48
+#set_property -dict {LOC AF11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[4]}] ;# J19.2 / HDB04 som240_2_d49
+#set_property -dict {LOC AG11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[5]}] ;# J19.4 / HDB05 som240_2_d50
+#set_property -dict {LOC AH12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[6]}] ;# J19.6 / HDB06 som240_2_c46
+#set_property -dict {LOC AH11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod3[7]}] ;# J19.8 / HDB07 som240_2_c47
+
+#set_false_path -to [get_ports {pmod3[*]}]
+#set_output_delay 0 [get_ports {pmod3[*]}]
+
+# PMOD4
+#set_property -dict {LOC AC12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[0]}] ;# J20.1 / HDB08_CC som240_2_c48
+#set_property -dict {LOC AD12 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[1]}] ;# J20.3 / HDB09 som240_2_c50
+#set_property -dict {LOC AE10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[2]}] ;# J20.5 / HDB10 som240_2_c51
+#set_property -dict {LOC AF10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[3]}] ;# J20.7 / HDB11 som240_2_c52
+#set_property -dict {LOC AD11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[4]}] ;# J20.2 / HDB12 som240_2_b44
+#set_property -dict {LOC AD10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[5]}] ;# J20.4 / HDB13 som240_2_b45
+#set_property -dict {LOC AA11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[6]}] ;# J20.6 / HDB14 som240_2_b46
+#set_property -dict {LOC AA10 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod4[7]}] ;# J20.8 / HDB15 som240_2_b48
+
+#set_false_path -to [get_ports {pmod4[*]}]
+#set_output_delay 0 [get_ports {pmod4[*]}]
+
+# Gigabit Ethernet RGMII PHY
+set_property -dict {LOC D4   IOSTANDARD LVCMOS18} [get_ports {phy2_rx_clk}] ;# from U79.32 RX_CLK / HPA09P_CLK som240_1_d10
+set_property -dict {LOC A1   IOSTANDARD LVCMOS18} [get_ports {phy2_rxd[0]}] ;# from U79.33 RX_D0_SGMII_COP / HPA06N som240_1_a4
+set_property -dict {LOC B3   IOSTANDARD LVCMOS18} [get_ports {phy2_rxd[1]}] ;# from U79.34 RX_D1_SGMII_CON / HPA07P som240_1_b7
+set_property -dict {LOC A3   IOSTANDARD LVCMOS18} [get_ports {phy2_rxd[2]}] ;# from U79.35 RX_D2_SGMII_SOP / HPA07N som240_1_b8
+set_property -dict {LOC B4   IOSTANDARD LVCMOS18} [get_ports {phy2_rxd[3]}] ;# from U79.36 RX_D3_SGMII_SON / HPA08P som240_1_c9
+set_property -dict {LOC A4   IOSTANDARD LVCMOS18} [get_ports {phy2_rx_ctl}] ;# from U79.38 RX_CTRL / HPA08N som240_1_c10
+set_property -dict {LOC A2   IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy2_tx_clk}] ;# from U79.29 GTX_CLK / HPA06P_CLK som240_1_a3
+set_property -dict {LOC E1   IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy2_txd[0]}] ;# from U79.28 TX_D0_SGMII_SIN / HPA01P som240_1_d7
+set_property -dict {LOC D1   IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy2_txd[1]}] ;# from U79.27 TX_D1_SGMII_SIP / HPA01N som240_1_d8
+set_property -dict {LOC F2   IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy2_txd[2]}] ;# from U79.26 TX_D2 / HPA02P som240_1_d4
+set_property -dict {LOC E2   IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy2_txd[3]}] ;# from U79.25 TX_D3 / HPA02N som240_1_d5
+set_property -dict {LOC F1   IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy2_tx_ctl}] ;# from U79.37 TX_CTRL / HPA00_CCN som240_1_c4
+set_property -dict {LOC B1   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy2_reset_n}] ;# from U79.43 RESET_B / HPA05_CCN som240_1_b2
+#set_property -dict {LOC F3   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy2_mdio}] ;# from U79.17 MDIO / HPA03N som240_1_c7
+#set_property -dict {LOC G3   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy2_mdc}] ;# from U79.16 MDC / HPA03P som240_1_c6
+#set_property -dict {LOC E4   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy2_led[0]}] ;# from U79.47 LED_0 / HPA04P som240_1_b4
+#set_property -dict {LOC E3   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy2_led[1]}] ;# from U79.46 LED_1 / HPA04N som240_1_b5
+#set_property -dict {LOC C1   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy2_led[2]}] ;# from U79.45 LED_2 / HPA05_CCP som240_1_b1
+
+create_clock -period 8.000 -name {phy2_rx_clk} [get_ports {phy2_rx_clk}]
+
+set_false_path -to [get_ports {phy2_reset_n}]
+set_output_delay 0 [get_ports {phy2_reset_n}]
+# set_false_path -from [get_ports {phy2_led[*]}]
+# set_input_delay 0 [get_ports {phy2_led[*]}]
+
+#set_false_path -to [get_ports {phy2_mdio phy2_mdc}]
+#set_output_delay 0 [get_ports {phy2_mdio phy2_mdc}]
+#set_false_path -from [get_ports {phy2_mdio}]
+#set_input_delay 0 [get_ports {phy2_mdio}]
+
+set_property -dict {LOC K4   IOSTANDARD LVCMOS18} [get_ports {phy3_rx_clk}] ;# from U80.32 RX_CLK / HPB09P_CLK som240_2_c11
+set_property -dict {LOC H1   IOSTANDARD LVCMOS18} [get_ports {phy3_rxd[0]}] ;# from U80.33 RX_D0_SGMII_COP / HPB06N som240_2_a21
+set_property -dict {LOC K2   IOSTANDARD LVCMOS18} [get_ports {phy3_rxd[1]}] ;# from U80.34 RX_D1_SGMII_CON / HPB07P som240_2_b15
+set_property -dict {LOC J2   IOSTANDARD LVCMOS18} [get_ports {phy3_rxd[2]}] ;# from U80.35 RX_D2_SGMII_SOP / HPB07N som240_2_b16
+set_property -dict {LOC H4   IOSTANDARD LVCMOS18} [get_ports {phy3_rxd[3]}] ;# from U80.36 RX_D3_SGMII_SON / HPB08P som240_2_a14
+set_property -dict {LOC H3   IOSTANDARD LVCMOS18} [get_ports {phy3_rx_ctl}] ;# from U80.38 RX_CTRL HBP08N som240_2_a15
+set_property -dict {LOC J1   IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy3_tx_clk}] ;# from U80.29 GTX_CLK / HPB06P_CLK som240_2_a20
+set_property -dict {LOC U9   IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy3_txd[0]}] ;# from U80.28 TX_D0_SGMII_SIN / HPB01P som240_2_d12
+set_property -dict {LOC V9   IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy3_txd[1]}] ;# from U80.27 TX_D1_SGMII_SIP / HPB01N som240_2_d13
+set_property -dict {LOC U8   IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy3_txd[2]}] ;# from U80.26 TX_D2 / HPB02P som240_2_c17
+set_property -dict {LOC V8   IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy3_txd[3]}] ;# from U80.25 TX_D3 / HPB02N som240_2_c18
+set_property -dict {LOC Y8   IOSTANDARD LVCMOS18 SLEW FAST DRIVE 12} [get_ports {phy3_tx_ctl}] ;# from U80.37 TX_CTRL / HPB00_CCN som240_2_d16
+set_property -dict {LOC K1   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy3_reset_n}] ;# from U80.43 RESET_B / HPB05_CCN som240_2_b19
+#set_property -dict {LOC T8   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy3_mdio}] ;# from U80.17 MDIO / HPB03N som240_2_b25
+#set_property -dict {LOC R8   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy3_mdc}] ;# from U80.16 MDC / HPB03P som240_2_b24
+#set_property -dict {LOC R7   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy3_led[0]}] ;# from U80.47 LED_0 / HPB04P som240_2_d21
+#set_property -dict {LOC T7   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy3_led[1]}] ;# from U80.46 LED_1 / HPB04N som240_2_d22
+#set_property -dict {LOC L1   IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {phy3_led[2]}] ;# from U80.45 LED_2 / HPB05_CCP som240_2_b18
+
+create_clock -period 8.000 -name {phy3_rx_clk} [get_ports {phy3_rx_clk}]
+
+set_false_path -to [get_ports {phy3_reset_n}]
+set_output_delay 0 [get_ports {phy3_reset_n}]
+# set_false_path -from [get_ports {phy3_led[*]}]
+# set_input_delay 0 [get_ports {phy3_led[*]}]
+
+#set_false_path -to [get_ports {phy3_mdio phy3_mdc}]
+#set_output_delay 0 [get_ports {phy3_mdio phy3_mdc}]
+#set_false_path -from [get_ports {phy3_mdio}]
+#set_input_delay 0 [get_ports {phy3_mdio}]
+
+# SFP+ Interface
+set_property -dict {LOC T2  } [get_ports sfp_rx_p] ;# MGTHRXP2_224 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3 / GTH_DP2_C2M_P som240_2_b1
+set_property -dict {LOC T1  } [get_ports sfp_rx_n] ;# MGTHRXN2_224 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3 / GTH_DP2_C2M_N som240_2_b2
+set_property -dict {LOC R4  } [get_ports sfp_tx_p] ;# MGTHTXP2_224 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3 / GTH_DP2_M2C_P som240_2_b5
+set_property -dict {LOC R3  } [get_ports sfp_tx_n] ;# MGTHTXN2_224 GTHE4_CHANNEL_X1Y12 / GTHE4_COMMON_X1Y3 / GTH_DP2_M2C_N som240_2_b6
+set_property -dict {LOC Y6  } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_224 from U90 / GTH_REFCLK0_C2M_P som240_2_c3
+set_property -dict {LOC Y5  } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_224 from U90 / GTH_REFCLK0_C2M_N som240_2_c4
+set_property -dict {LOC Y10  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp_tx_disable] ;# HDB19 som240_2_a47
+set_property -dict {LOC A10  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp_tx_fault]   ;# HDA19 som240_1_c23
+set_property -dict {LOC J12  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp_rx_los]     ;# HDA10 som240_1_a16
+set_property -dict {LOC W10  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp_mod_abs]    ;# HDB18 som240_2_a46
+set_property -dict {LOC AB11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp_i2c_scl]    ;# HDB16 som240_2_b49
+set_property -dict {LOC AC11 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp_i2c_sda]    ;# HDB17 som240_2_b50
+
+# 156.25 MHz MGT reference clock
+create_clock -period 6.400 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]
+
+set_false_path -to [get_ports {sfp_tx_disable}]
+set_output_delay 0 [get_ports {sfp_tx_disable}]
+set_false_path -from [get_ports {sfp_tx_fault sfp_rx_los sfp_mod_abs}]
+set_input_delay 0 [get_ports {sfp_tx_fault sfp_rx_los sfp_mod_abs}]
+
+set_false_path -to [get_ports {sfp_i2c_sda sfp_i2c_scl}]
+set_output_delay 0 [get_ports {sfp_i2c_sda sfp_i2c_scl}]
+set_false_path -from [get_ports {sfp_i2c_sda sfp_i2c_scl}]
+set_input_delay 0 [get_ports {sfp_i2c_sda sfp_i2c_scl}]
diff --git a/example/KR260/fpga/fpga_1g/Makefile b/example/KR260/fpga/fpga_1g/Makefile
new file mode 100644
index 0000000..fd05f1a
--- /dev/null
+++ b/example/KR260/fpga/fpga_1g/Makefile
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xck26-sfvc784-2LV-c
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplus
+
+# Files for synthesis
+SYN_FILES = ../rtl/fpga.sv
+SYN_FILES += ../rtl/fpga_core.sv
+SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f
+SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f
+SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv
+SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += ../eth_rgmii.xdc
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_rgmii_phy_if.tcl
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_1g_rgmii.tcl
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl
+
+# IP
+IP_TCL_FILES = ../ip/basex_pcs_pma_0.tcl
+
+# Configuration
+# CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(PROJECT).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
diff --git a/example/KR260/fpga/fpga_1g/generate_bit_iodelay.tcl b/example/KR260/fpga/fpga_1g/generate_bit_iodelay.tcl
new file mode 100644
index 0000000..e758d6a
--- /dev/null
+++ b/example/KR260/fpga/fpga_1g/generate_bit_iodelay.tcl
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# Generate bit file with different IODELAY settings without rebuilding the full project
+
+open_project fpga.xpr
+open_run impl_1
+
+# IDELAY from PHY chip (RGMII)
+set_property DELAY_VALUE 0 [get_cells {phy2_rx_ctl_idelay phy2_rxd_idelay_bit[*].idelay_inst}]
+set_property DELAY_VALUE 0 [get_cells {phy3_rx_ctl_idelay phy3_rxd_idelay_bit[*].idelay_inst}]
+
+# MMCM phase (RGMII)
+set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
+
+write_bitstream -force fpga.bit
+exit
diff --git a/example/KR260/fpga/ip/basex_pcs_pma_0.tcl b/example/KR260/fpga/ip/basex_pcs_pma_0.tcl
new file mode 100644
index 0000000..a4c6f27
--- /dev/null
+++ b/example/KR260/fpga/ip/basex_pcs_pma_0.tcl
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name basex_pcs_pma_0
+
+set_property -dict [list \
+    CONFIG.Standard {1000BASEX} \
+    CONFIG.Physical_Interface {Transceiver} \
+    CONFIG.Management_Interface {false} \
+    CONFIG.Auto_Negotiation {false} \
+    CONFIG.TransceiverControl {false} \
+    CONFIG.RefClkRate {156.25} \
+    CONFIG.DrpClkRate {62.5} \
+    CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \
+    CONFIG.GT_Location {X0Y6} \
+] [get_ips basex_pcs_pma_0]
diff --git a/example/KR260/fpga/lib/taxi b/example/KR260/fpga/lib/taxi
new file mode 120000
index 0000000..11a54ed
--- /dev/null
+++ b/example/KR260/fpga/lib/taxi
@@ -0,0 +1 @@
+../../../../
\ No newline at end of file
diff --git a/example/KR260/fpga/rtl/fpga.sv b/example/KR260/fpga/rtl/fpga.sv
new file mode 100644
index 0000000..d7ed8a9
--- /dev/null
+++ b/example/KR260/fpga/rtl/fpga.sv
@@ -0,0 +1,537 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter VENDOR = "XILINX",
+    // device family
+    parameter FAMILY = "zynquplus",
+    // Use 90 degree clock for RGMII transmit
+    parameter logic USE_CLK90 = 1'b1
+)
+(
+    /*
+     * Clock: 25MHz
+     */
+    input  wire logic        clk_25mhz,
+
+    /*
+     * GPIO
+     */
+    output wire logic [1:0]  led,
+    output wire logic [1:0]  sfp_led,
+
+    /*
+     * Ethernet: 1000BASE-T RGMII
+     */
+    input  wire logic        phy2_rx_clk,
+    input  wire logic [3:0]  phy2_rxd,
+    input  wire logic        phy2_rx_ctl,
+    output wire logic        phy2_tx_clk,
+    output wire logic [3:0]  phy2_txd,
+    output wire logic        phy2_tx_ctl,
+    output wire logic        phy2_reset_n,
+
+    input  wire logic        phy3_rx_clk,
+    input  wire logic [3:0]  phy3_rxd,
+    input  wire logic        phy3_rx_ctl,
+    output wire logic        phy3_tx_clk,
+    output wire logic [3:0]  phy3_txd,
+    output wire logic        phy3_tx_ctl,
+    output wire logic        phy3_reset_n,
+
+    /*
+     * Ethernet: SFP+
+     */
+    input  wire logic        sfp_rx_p,
+    input  wire logic        sfp_rx_n,
+    output wire logic        sfp_tx_p,
+    output wire logic        sfp_tx_n,
+    input  wire logic        sfp_mgt_refclk_p,
+    input  wire logic        sfp_mgt_refclk_n,
+
+    output wire logic        sfp_tx_disable,
+    input  wire logic        sfp_tx_fault,
+    input  wire logic        sfp_rx_los,
+    input  wire logic        sfp_mod_abs,
+    inout  wire logic        sfp_i2c_scl,
+    inout  wire logic        sfp_i2c_sda
+);
+
+// Clock and reset
+
+// Internal 125 MHz clock
+wire clk_125mhz_mmcm_out;
+wire clk90_125mhz_mmcm_out;
+wire clk_125mhz_int;
+wire clk90_125mhz_int;
+wire rst_125mhz_int;
+
+// Internal 62.5 MHz clock
+wire clk_62mhz_mmcm_out;
+wire clk_62mhz_int;
+
+// Internal 312.5 MHz clock
+wire clk_312mhz_mmcm_out;
+wire clk_312mhz_int;
+wire rst_312mhz_int;
+
+wire mmcm_rst = 1'b0;
+wire mmcm_locked;
+wire mmcm_clkfb;
+
+// MMCM instance
+MMCME3_BASE #(
+    // 25 MHz input
+    .CLKIN1_PERIOD(40),
+    .REF_JITTER1(0.010),
+    // 25 MHz input / 1 = 25 MHz PFD (range 10 MHz to 500 MHz)
+    .DIVCLK_DIVIDE(1),
+    // 25 MHz PFD * 50 = 1250 MHz VCO (range 600 MHz to 1440 MHz)
+    .CLKFBOUT_MULT_F(50),
+    .CLKFBOUT_PHASE(0),
+    // 1250 MHz / 10 = 125 MHz, 0 degrees
+    .CLKOUT0_DIVIDE_F(10),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    // 1250 MHz / 10 = 125 MHz, 90 degrees
+    .CLKOUT1_DIVIDE(10),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(90),
+    // 1250 MHz / 20 = 62.5 MHz, 0 degrees
+    .CLKOUT2_DIVIDE(20),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    // 1250 MHz / 4 = 312.5 MHz, 0 degrees
+    .CLKOUT3_DIVIDE(4),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    // Not used
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT4_CASCADE("FALSE"),
+    // Not used
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    // Not used
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+
+    // optimized bandwidth
+    .BANDWIDTH("OPTIMIZED"),
+    // don't wait for lock during startup
+    .STARTUP_WAIT("FALSE")
+)
+clk_mmcm_inst (
+    // 25 MHz input
+    .CLKIN1(clk_25mhz),
+    // direct clkfb feeback
+    .CLKFBIN(mmcm_clkfb),
+    .CLKFBOUT(mmcm_clkfb),
+    .CLKFBOUTB(),
+    // 125 MHz, 0 degrees
+    .CLKOUT0(clk_125mhz_mmcm_out),
+    .CLKOUT0B(),
+    // 125 MHz, 90 degrees
+    .CLKOUT1(clk90_125mhz_mmcm_out),
+    .CLKOUT1B(),
+    // 62.5 MHz, 0 degrees
+    .CLKOUT2(clk_62mhz_mmcm_out),
+    .CLKOUT2B(),
+    // 312.5 MHz, 0 degrees
+    .CLKOUT3(clk_312mhz_mmcm_out),
+    .CLKOUT3B(),
+    // Not used
+    .CLKOUT4(),
+    // Not used
+    .CLKOUT5(),
+    // Not used
+    .CLKOUT6(),
+    // reset input
+    .RST(mmcm_rst),
+    // don't power down
+    .PWRDWN(1'b0),
+    // locked output
+    .LOCKED(mmcm_locked)
+);
+
+BUFG
+clk_125mhz_bufg_inst (
+    .I(clk_125mhz_mmcm_out),
+    .O(clk_125mhz_int)
+);
+
+BUFG
+clk90_125mhz_bufg_inst (
+    .I(clk90_125mhz_mmcm_out),
+    .O(clk90_125mhz_int)
+);
+
+BUFG
+clk_62mhz_bufg_inst (
+    .I(clk_62mhz_mmcm_out),
+    .O(clk_62mhz_int)
+);
+
+BUFG
+clk_312mhz_bufg_inst (
+    .I(clk_312mhz_mmcm_out),
+    .O(clk_312mhz_int)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_125mhz_inst (
+    .clk(clk_125mhz_int),
+    .rst(~mmcm_locked),
+    .out(rst_125mhz_int)
+);
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_312mhz_inst (
+    .clk(clk_312mhz_int),
+    .rst(~mmcm_locked),
+    .out(rst_312mhz_int)
+);
+
+// GPIO
+wire sfp_tx_fault_int;
+wire sfp_rx_los_int;
+wire sfp_mod_abs_int;
+
+wire sfp_i2c_scl_i;
+wire sfp_i2c_scl_o;
+wire sfp_i2c_scl_t;
+wire sfp_i2c_sda_i;
+wire sfp_i2c_sda_o;
+wire sfp_i2c_sda_t;
+
+reg sfp_i2c_scl_o_reg;
+reg sfp_i2c_scl_t_reg;
+reg sfp_i2c_sda_o_reg;
+reg sfp_i2c_sda_t_reg;
+
+always @(posedge clk_125mhz_int) begin
+    sfp_i2c_scl_o_reg <= sfp_i2c_scl_o;
+    sfp_i2c_scl_t_reg <= sfp_i2c_scl_t;
+    sfp_i2c_sda_o_reg <= sfp_i2c_sda_o;
+    sfp_i2c_sda_t_reg <= sfp_i2c_sda_t;
+end
+
+taxi_sync_signal #(
+    .WIDTH(5),
+    .N(2)
+)
+sync_signal_inst (
+    .clk(clk_125mhz_int),
+    .in({sfp_tx_fault, sfp_rx_los, sfp_mod_abs, sfp_i2c_scl, sfp_i2c_sda}),
+    .out({sfp_tx_fault_int, sfp_rx_los_int, sfp_mod_abs_int, sfp_i2c_scl_i, sfp_i2c_sda_i})
+);
+
+assign sfp_i2c_scl = sfp_i2c_scl_t_reg ? 1'bz : sfp_i2c_scl_o_reg;
+assign sfp_i2c_sda = sfp_i2c_sda_t_reg ? 1'bz : sfp_i2c_sda_o_reg;
+
+// IODELAY elements for RGMII interface to PHY
+wire [3:0] phy2_rxd_int;
+wire phy2_rx_ctl_int;
+
+wire [3:0] phy3_rxd_int;
+wire phy3_rx_ctl_int;
+
+IDELAYCTRL #(
+    .SIM_DEVICE("ULTRASCALE")
+)
+idelayctrl_inst (
+    .REFCLK(clk_312mhz_int),
+    .RST(rst_312mhz_int),
+    .RDY()
+);
+
+for (genvar n = 0; n < 4; n = n + 1) begin : phy2_rxd_idelay_bit
+    
+    IDELAYE3 #(
+        .DELAY_SRC("IDATAIN"),
+        .CASCADE("NONE"),
+        .DELAY_TYPE("FIXED"),
+        .DELAY_VALUE(0),
+        .REFCLK_FREQUENCY(312.5),
+        .DELAY_FORMAT("TIME"),
+        .UPDATE_MODE("SYNC"),
+        .SIM_DEVICE("ULTRASCALE_PLUS")
+    )
+    idelay_inst (
+        .CASC_IN(1'b0),
+        .CASC_RETURN(1'b0),
+        .CASC_OUT(),
+        .IDATAIN(phy2_rxd[n]),
+        .DATAIN(1'b0),
+        .DATAOUT(phy2_rxd_int[n]),
+        .CLK(1'b0),
+        .EN_VTC(1'b1),
+        .CE(1'b0),
+        .INC(1'b0),
+        .LOAD(1'b0),
+        .RST(1'b0),
+        .CNTVALUEIN(9'd0),
+        .CNTVALUEOUT()
+    );
+
+end
+
+IDELAYE3 #(
+    .DELAY_SRC("IDATAIN"),
+    .CASCADE("NONE"),
+    .DELAY_TYPE("FIXED"),
+    .DELAY_VALUE(0),
+    .REFCLK_FREQUENCY(312.5),
+    .DELAY_FORMAT("TIME"),
+    .UPDATE_MODE("SYNC"),
+    .SIM_DEVICE("ULTRASCALE_PLUS")
+)
+phy2_rx_ctl_idelay (
+    .CASC_IN(1'b0),
+    .CASC_RETURN(1'b0),
+    .CASC_OUT(),
+    .IDATAIN(phy2_rx_ctl),
+    .DATAIN(1'b0),
+    .DATAOUT(phy2_rx_ctl_int),
+    .CLK(1'b0),
+    .EN_VTC(1'b1),
+    .CE(1'b0),
+    .INC(1'b0),
+    .LOAD(1'b0),
+    .RST(1'b0),
+    .CNTVALUEIN(9'd0),
+    .CNTVALUEOUT()
+);
+
+for (genvar n = 0; n < 4; n = n + 1) begin : phy3_rxd_idelay_bit
+    
+    IDELAYE3 #(
+        .DELAY_SRC("IDATAIN"),
+        .CASCADE("NONE"),
+        .DELAY_TYPE("FIXED"),
+        .DELAY_VALUE(0),
+        .REFCLK_FREQUENCY(312.5),
+        .DELAY_FORMAT("TIME"),
+        .UPDATE_MODE("SYNC"),
+        .SIM_DEVICE("ULTRASCALE_PLUS")
+    )
+    idelay_inst (
+        .CASC_IN(1'b0),
+        .CASC_RETURN(1'b0),
+        .CASC_OUT(),
+        .IDATAIN(phy3_rxd[n]),
+        .DATAIN(1'b0),
+        .DATAOUT(phy3_rxd_int[n]),
+        .CLK(1'b0),
+        .EN_VTC(1'b1),
+        .CE(1'b0),
+        .INC(1'b0),
+        .LOAD(1'b0),
+        .RST(1'b0),
+        .CNTVALUEIN(9'd0),
+        .CNTVALUEOUT()
+    );
+
+end
+
+IDELAYE3 #(
+    .DELAY_SRC("IDATAIN"),
+    .CASCADE("NONE"),
+    .DELAY_TYPE("FIXED"),
+    .DELAY_VALUE(0),
+    .REFCLK_FREQUENCY(312.5),
+    .DELAY_FORMAT("TIME"),
+    .UPDATE_MODE("SYNC"),
+    .SIM_DEVICE("ULTRASCALE_PLUS")
+)
+phy3_rx_ctl_idelay (
+    .CASC_IN(1'b0),
+    .CASC_RETURN(1'b0),
+    .CASC_OUT(),
+    .IDATAIN(phy3_rx_ctl),
+    .DATAIN(1'b0),
+    .DATAOUT(phy3_rx_ctl_int),
+    .CLK(1'b0),
+    .EN_VTC(1'b1),
+    .CE(1'b0),
+    .INC(1'b0),
+    .LOAD(1'b0),
+    .RST(1'b0),
+    .CNTVALUEIN(9'd0),
+    .CNTVALUEOUT()
+);
+
+// 1000BASE-X SFP
+wire sfp_gmii_clk_int;
+wire sfp_gmii_rst_int;
+wire sfp_gmii_clk_en_int;
+wire [7:0] sfp_gmii_txd_int;
+wire sfp_gmii_tx_en_int;
+wire sfp_gmii_tx_er_int;
+wire [7:0] sfp_gmii_rxd_int;
+wire sfp_gmii_rx_dv_int;
+wire sfp_gmii_rx_er_int;
+
+wire sfp_gmii_txuserclk2;
+wire sfp_gmii_resetdone;
+
+assign sfp_gmii_clk_int = sfp_gmii_txuserclk2;
+
+taxi_sync_reset #(
+    .N(4)
+)
+sync_reset_sfp_inst (
+    .clk(sfp_gmii_clk_int),
+    .rst(rst_125mhz_int || !sfp_gmii_resetdone),
+    .out(sfp_gmii_rst_int)
+);
+
+wire [15:0] sfp_status_vect;
+
+wire sfp_status_link_status              = sfp_status_vect[0];
+wire sfp_status_link_synchronization     = sfp_status_vect[1];
+wire sfp_status_rudi_c                   = sfp_status_vect[2];
+wire sfp_status_rudi_i                   = sfp_status_vect[3];
+wire sfp_status_rudi_invalid             = sfp_status_vect[4];
+wire sfp_status_rxdisperr                = sfp_status_vect[5];
+wire sfp_status_rxnotintable             = sfp_status_vect[6];
+wire sfp_status_phy_link_status          = sfp_status_vect[7];
+wire [1:0] sfp_status_remote_fault_encdg = sfp_status_vect[9:8];
+wire [1:0] sfp_status_speed              = sfp_status_vect[11:10];
+wire sfp_status_duplex                   = sfp_status_vect[12];
+wire sfp_status_remote_fault             = sfp_status_vect[13];
+wire [1:0] sfp_status_pause              = sfp_status_vect[15:14];
+
+wire [4:0] sfp_config_vect;
+
+assign sfp_config_vect[4] = 1'b0; // autonegotiation enable
+assign sfp_config_vect[3] = 1'b0; // isolate
+assign sfp_config_vect[2] = 1'b0; // power down
+assign sfp_config_vect[1] = 1'b0; // loopback enable
+assign sfp_config_vect[0] = 1'b0; // unidirectional enable
+
+basex_pcs_pma_0
+sfp_pcspma (
+    .gtrefclk_p(sfp_mgt_refclk_p),
+    .gtrefclk_n(sfp_mgt_refclk_n),
+    .gtrefclk_out(),
+    .txn(sfp_tx_n),
+    .txp(sfp_tx_p),
+    .rxn(sfp_rx_n),
+    .rxp(sfp_rx_p),
+    .independent_clock_bufg(clk_62mhz_int),
+    .userclk_out(),
+    .userclk2_out(sfp_gmii_txuserclk2),
+    .rxuserclk_out(),
+    .rxuserclk2_out(),
+    .gtpowergood(),
+    .resetdone(sfp_gmii_resetdone),
+    .pma_reset_out(),
+    .mmcm_locked_out(),
+    .gmii_txd(sfp_gmii_txd_int),
+    .gmii_tx_en(sfp_gmii_tx_en_int),
+    .gmii_tx_er(sfp_gmii_tx_er_int),
+    .gmii_rxd(sfp_gmii_rxd_int),
+    .gmii_rx_dv(sfp_gmii_rx_dv_int),
+    .gmii_rx_er(sfp_gmii_rx_er_int),
+    .gmii_isolate(),
+    .configuration_vector(sfp_config_vect),
+    .status_vector(sfp_status_vect),
+    .reset(rst_125mhz_int),
+    .signal_detect(1'b1)
+);
+
+assign sfp_gmii_clk_en_int = 1'b1;
+
+fpga_core #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .USE_CLK90(USE_CLK90)
+)
+core_inst (
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    .clk(clk_125mhz_int),
+    .clk90(clk90_125mhz_int),
+    .rst(rst_125mhz_int),
+
+    /*
+     * GPIO
+     */
+    .led(led),
+    .sfp_led(sfp_led),
+
+    /*
+     * Ethernet: 1000BASE-T RGMII
+     */
+    .phy2_rgmii_rx_clk(phy2_rx_clk),
+    .phy2_rgmii_rxd(phy2_rxd_int),
+    .phy2_rgmii_rx_ctl(phy2_rx_ctl_int),
+    .phy2_rgmii_tx_clk(phy2_tx_clk),
+    .phy2_rgmii_txd(phy2_txd),
+    .phy2_rgmii_tx_ctl(phy2_tx_ctl),
+    .phy2_reset_n(phy2_reset_n),
+
+    .phy3_rgmii_rx_clk(phy3_rx_clk),
+    .phy3_rgmii_rxd(phy3_rxd_int),
+    .phy3_rgmii_rx_ctl(phy3_rx_ctl_int),
+    .phy3_rgmii_tx_clk(phy3_tx_clk),
+    .phy3_rgmii_txd(phy3_txd),
+    .phy3_rgmii_tx_ctl(phy3_tx_ctl),
+    .phy3_reset_n(phy3_reset_n),
+
+    /*
+     * Ethernet: 1000BASE-X SFP
+     */
+    .sfp_gmii_clk(sfp_gmii_clk_int),
+    .sfp_gmii_rst(sfp_gmii_rst_int),
+    .sfp_gmii_clk_en(sfp_gmii_clk_en_int),
+    .sfp_gmii_rxd(sfp_gmii_rxd_int),
+    .sfp_gmii_rx_dv(sfp_gmii_rx_dv_int),
+    .sfp_gmii_rx_er(sfp_gmii_rx_er_int),
+    .sfp_gmii_txd(sfp_gmii_txd_int),
+    .sfp_gmii_tx_en(sfp_gmii_tx_en_int),
+    .sfp_gmii_tx_er(sfp_gmii_tx_er_int),
+    .sfp_tx_disable(sfp_tx_disable),
+    .sfp_tx_fault(sfp_tx_fault_int),
+    .sfp_rx_los(sfp_rx_los_int),
+    .sfp_mod_abs(sfp_mod_abs_int),
+    .sfp_i2c_scl_i(sfp_i2c_scl_i),
+    .sfp_i2c_scl_o(sfp_i2c_scl_o),
+    .sfp_i2c_scl_t(sfp_i2c_scl_t),
+    .sfp_i2c_sda_i(sfp_i2c_sda_i),
+    .sfp_i2c_sda_o(sfp_i2c_sda_o),
+    .sfp_i2c_sda_t(sfp_i2c_sda_t)
+);
+
+endmodule
+
+`resetall
diff --git a/example/KR260/fpga/rtl/fpga_core.sv b/example/KR260/fpga/rtl/fpga_core.sv
new file mode 100644
index 0000000..6b87e6f
--- /dev/null
+++ b/example/KR260/fpga/rtl/fpga_core.sv
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: MIT
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    // simulation (set to avoid vendor primitives)
+    parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
+    parameter VENDOR = "XILINX",
+    // device family
+    parameter FAMILY = "zynquplus",
+    // Use 90 degree clock for RGMII transmit
+    parameter logic USE_CLK90 = 1'b1
+)
+(
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    input  wire logic        clk,
+    input  wire logic        clk90,
+    input  wire logic        rst,
+
+    /*
+     * GPIO
+     */
+    output wire logic [1:0]  led,
+    output wire logic [1:0]  sfp_led,
+
+    /*
+     * Ethernet: 1000BASE-T
+     */
+    input  wire logic        phy2_rgmii_rx_clk,
+    input  wire logic [3:0]  phy2_rgmii_rxd,
+    input  wire logic        phy2_rgmii_rx_ctl,
+    output wire logic        phy2_rgmii_tx_clk,
+    output wire logic [3:0]  phy2_rgmii_txd,
+    output wire logic        phy2_rgmii_tx_ctl,
+    output wire logic        phy2_reset_n,
+
+    input  wire logic        phy3_rgmii_rx_clk,
+    input  wire logic [3:0]  phy3_rgmii_rxd,
+    input  wire logic        phy3_rgmii_rx_ctl,
+    output wire logic        phy3_rgmii_tx_clk,
+    output wire logic [3:0]  phy3_rgmii_txd,
+    output wire logic        phy3_rgmii_tx_ctl,
+    output wire logic        phy3_reset_n,
+
+    /*
+     * Ethernet: 1000BASE-X SFP
+     */
+    input  wire logic        sfp_gmii_clk,
+    input  wire logic        sfp_gmii_rst,
+    input  wire logic        sfp_gmii_clk_en,
+    input  wire logic [7:0]  sfp_gmii_rxd,
+    input  wire logic        sfp_gmii_rx_dv,
+    input  wire logic        sfp_gmii_rx_er,
+    output wire logic [7:0]  sfp_gmii_txd,
+    output wire logic        sfp_gmii_tx_en,
+    output wire logic        sfp_gmii_tx_er,
+
+    output wire logic        sfp_tx_disable,
+    input  wire logic        sfp_tx_fault,
+    input  wire logic        sfp_rx_los,
+    input  wire logic        sfp_mod_abs,
+    input  wire logic        sfp_i2c_scl_i,
+    output wire logic        sfp_i2c_scl_o,
+    output wire logic        sfp_i2c_scl_t,
+    input  wire logic        sfp_i2c_sda_i,
+    output wire logic        sfp_i2c_sda_o,
+    output wire logic        sfp_i2c_sda_t
+);
+
+// BASE-T PHY
+assign phy2_reset_n = !rst;
+assign phy3_reset_n = !rst;
+
+taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_phy2_eth();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_phy2_tx_cpl();
+
+taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_phy3_eth();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_phy3_tx_cpl();
+
+taxi_eth_mac_1g_rgmii_fifo #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .USE_CLK90(USE_CLK90),
+    .PADDING_EN(1),
+    .MIN_FRAME_LEN(64),
+    .TX_FIFO_DEPTH(16384),
+    .TX_FRAME_FIFO(1),
+    .RX_FIFO_DEPTH(16384),
+    .RX_FRAME_FIFO(1)
+)
+phy2_eth_mac_inst (
+    .gtx_clk(clk),
+    .gtx_clk90(clk90),
+    .gtx_rst(rst),
+    .logic_clk(clk),
+    .logic_rst(rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(axis_phy2_eth),
+    .m_axis_tx_cpl(axis_phy2_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(axis_phy2_eth),
+
+    /*
+     * RGMII interface
+     */
+    .rgmii_rx_clk(phy2_rgmii_rx_clk),
+    .rgmii_rxd(phy2_rgmii_rxd),
+    .rgmii_rx_ctl(phy2_rgmii_rx_ctl),
+    .rgmii_tx_clk(phy2_rgmii_tx_clk),
+    .rgmii_txd(phy2_rgmii_txd),
+    .rgmii_tx_ctl(phy2_rgmii_tx_ctl),
+
+    /*
+     * Status
+     */
+    .tx_error_underflow(),
+    .tx_fifo_overflow(),
+    .tx_fifo_bad_frame(),
+    .tx_fifo_good_frame(),
+    .rx_error_bad_frame(),
+    .rx_error_bad_fcs(),
+    .rx_fifo_overflow(),
+    .rx_fifo_bad_frame(),
+    .rx_fifo_good_frame(),
+    .link_speed(),
+
+    /*
+     * Configuration
+     */
+    .cfg_ifg(8'd12),
+    .cfg_tx_enable(1'b1),
+    .cfg_rx_enable(1'b1)
+);
+
+taxi_eth_mac_1g_rgmii_fifo #(
+    .SIM(SIM),
+    .VENDOR(VENDOR),
+    .FAMILY(FAMILY),
+    .USE_CLK90(USE_CLK90),
+    .PADDING_EN(1),
+    .MIN_FRAME_LEN(64),
+    .TX_FIFO_DEPTH(16384),
+    .TX_FRAME_FIFO(1),
+    .RX_FIFO_DEPTH(16384),
+    .RX_FRAME_FIFO(1)
+)
+phy3_eth_mac_inst (
+    .gtx_clk(clk),
+    .gtx_clk90(clk90),
+    .gtx_rst(rst),
+    .logic_clk(clk),
+    .logic_rst(rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(axis_phy3_eth),
+    .m_axis_tx_cpl(axis_phy3_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(axis_phy3_eth),
+
+    /*
+     * RGMII interface
+     */
+    .rgmii_rx_clk(phy3_rgmii_rx_clk),
+    .rgmii_rxd(phy3_rgmii_rxd),
+    .rgmii_rx_ctl(phy3_rgmii_rx_ctl),
+    .rgmii_tx_clk(phy3_rgmii_tx_clk),
+    .rgmii_txd(phy3_rgmii_txd),
+    .rgmii_tx_ctl(phy3_rgmii_tx_ctl),
+
+    /*
+     * Status
+     */
+    .tx_error_underflow(),
+    .tx_fifo_overflow(),
+    .tx_fifo_bad_frame(),
+    .tx_fifo_good_frame(),
+    .rx_error_bad_frame(),
+    .rx_error_bad_fcs(),
+    .rx_fifo_overflow(),
+    .rx_fifo_bad_frame(),
+    .rx_fifo_good_frame(),
+    .link_speed(),
+
+    /*
+     * Configuration
+     */
+    .cfg_ifg(8'd12),
+    .cfg_tx_enable(1'b1),
+    .cfg_rx_enable(1'b1)
+);
+
+// SFP+
+assign sfp_tx_disable = 1'b0;
+
+taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_sfp_eth();
+taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl();
+
+taxi_eth_mac_1g_fifo #(
+    .PADDING_EN(1),
+    .MIN_FRAME_LEN(64),
+    .TX_FIFO_DEPTH(16384),
+    .TX_FRAME_FIFO(1),
+    .RX_FIFO_DEPTH(16384),
+    .RX_FRAME_FIFO(1)
+)
+sfp_eth_mac_inst (
+    .rx_clk(sfp_gmii_clk),
+    .rx_rst(sfp_gmii_rst),
+    .tx_clk(sfp_gmii_clk),
+    .tx_rst(sfp_gmii_rst),
+    .logic_clk(clk),
+    .logic_rst(rst),
+
+    /*
+     * Transmit interface (AXI stream)
+     */
+    .s_axis_tx(axis_sfp_eth),
+    .m_axis_tx_cpl(axis_sfp_tx_cpl),
+
+    /*
+     * Receive interface (AXI stream)
+     */
+    .m_axis_rx(axis_sfp_eth),
+
+    /*
+     * GMII interface
+     */
+    .gmii_rxd(sfp_gmii_rxd),
+    .gmii_rx_dv(sfp_gmii_rx_dv),
+    .gmii_rx_er(sfp_gmii_rx_er),
+    .gmii_txd(sfp_gmii_txd),
+    .gmii_tx_en(sfp_gmii_tx_en),
+    .gmii_tx_er(sfp_gmii_tx_er),
+
+    /*
+     * Control
+     */
+    .rx_clk_enable(sfp_gmii_clk_en),
+    .tx_clk_enable(sfp_gmii_clk_en),
+    .rx_mii_select(1'b0),
+    .tx_mii_select(1'b0),
+
+    /*
+     * Status
+     */
+    .tx_error_underflow(),
+    .tx_fifo_overflow(),
+    .tx_fifo_bad_frame(),
+    .tx_fifo_good_frame(),
+    .rx_error_bad_frame(),
+    .rx_error_bad_fcs(),
+    .rx_fifo_overflow(),
+    .rx_fifo_bad_frame(),
+    .rx_fifo_good_frame(),
+
+    /*
+     * Configuration
+     */
+    .cfg_ifg(8'd12),
+    .cfg_tx_enable(1'b1),
+    .cfg_rx_enable(1'b1)
+);
+
+endmodule
+
+`resetall
diff --git a/example/KR260/fpga/tb/fpga_core/Makefile b/example/KR260/fpga/tb/fpga_core/Makefile
new file mode 100644
index 0000000..64acd4b
--- /dev/null
+++ b/example/KR260/fpga/tb/fpga_core/Makefile
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = fpga_core
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = $(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += ../../rtl/$(DUT).sv
+VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_fifo.f
+VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_1g_rgmii_fifo.f
+VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv
+VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_SIM := "1'b1"
+export PARAM_VENDOR := "\"XILINX\""
+export PARAM_FAMILY := "\"zynquplus\""
+export PARAM_USE_CLK90 := "1'b1"
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/example/KR260/fpga/tb/fpga_core/test_fpga_core.py b/example/KR260/fpga/tb/fpga_core/test_fpga_core.py
new file mode 100644
index 0000000..93802ea
--- /dev/null
+++ b/example/KR260/fpga/tb/fpga_core/test_fpga_core.py
@@ -0,0 +1,200 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: MIT
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.log import SimLog
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, Timer, Combine
+
+from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink, RgmiiPhy
+
+
+class TB:
+    def __init__(self, dut, speed=1000e6):
+        self.dut = dut
+
+        self.log = SimLog("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.sfp_gmii_clk, 8, units="ns").start())
+
+        self.baset_phy2 = RgmiiPhy(dut.phy2_rgmii_txd, dut.phy2_rgmii_tx_ctl, dut.phy2_rgmii_tx_clk,
+            dut.phy2_rgmii_rxd, dut.phy2_rgmii_rx_ctl, dut.phy2_rgmii_rx_clk, speed=speed)
+
+        self.baset_phy3 = RgmiiPhy(dut.phy3_rgmii_txd, dut.phy3_rgmii_tx_ctl, dut.phy3_rgmii_tx_clk,
+            dut.phy3_rgmii_rxd, dut.phy3_rgmii_rx_ctl, dut.phy3_rgmii_rx_clk, speed=speed)
+
+        self.sfp_source = GmiiSource(dut.sfp_gmii_rxd, dut.sfp_gmii_rx_er, dut.sfp_gmii_rx_dv,
+            dut.sfp_gmii_clk, dut.sfp_gmii_rst, dut.sfp_gmii_clk_en)
+        self.sfp_sink = GmiiSink(dut.sfp_gmii_txd, dut.sfp_gmii_tx_er, dut.sfp_gmii_tx_en,
+            dut.sfp_gmii_clk, dut.sfp_gmii_rst, dut.sfp_gmii_clk_en)
+
+        cocotb.start_soon(self._run_clk())
+
+    async def init(self):
+
+        self.dut.rst.setimmediatevalue(0)
+        self.dut.sfp_gmii_rst.setimmediatevalue(0)
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk)
+
+        self.dut.rst.value = 1
+        self.dut.sfp_gmii_rst.value = 1
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk)
+
+        self.dut.rst.value = 0
+        self.dut.sfp_gmii_rst.value = 0
+
+    async def _run_clk(self):
+        t = Timer(2, 'ns')
+        while True:
+            self.dut.clk.value = 1
+            await t
+            self.dut.clk90.value = 1
+            await t
+            self.dut.clk.value = 0
+            await t
+            self.dut.clk90.value = 0
+            await t
+
+
+async def mac_test(tb, source, sink):
+    tb.log.info("Test MAC")
+
+    tb.log.info("Multiple small packets")
+
+    count = 64
+
+    pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(GmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    tb.log.info("Multiple large packets")
+
+    count = 32
+
+    pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
+
+    for p in pkts:
+        await source.send(GmiiFrame.from_payload(p))
+
+    for k in range(count):
+        rx_frame = await sink.recv()
+
+        tb.log.info("RX frame: %s", rx_frame)
+
+        assert rx_frame.get_payload() == pkts[k]
+        assert rx_frame.check_fcs()
+        assert rx_frame.error is None
+
+    tb.log.info("MAC test done")
+
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.init()
+
+    tb.log.info("Start BASE-T MAC loopback test on PHY2")
+
+    phy2_test_cr = cocotb.start_soon(mac_test(tb, tb.baset_phy2.rx, tb.baset_phy2.tx))
+
+    tb.log.info("Start BASE-T MAC loopback test on PHY3")
+
+    phy3_test_cr = cocotb.start_soon(mac_test(tb, tb.baset_phy3.rx, tb.baset_phy3.tx))
+
+    tb.log.info("Start SFP MAC loopback test")
+
+    sfp_test_cr = cocotb.start_soon(mac_test(tb, tb.sfp_source, tb.sfp_sink))
+
+    await Combine(phy2_test_cr, phy3_test_cr, sfp_test_cr)
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_fpga_core(request):
+    dut = "fpga_core"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.sv"),
+        os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_fifo.f"),
+        os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_1g_rgmii_fifo.f"),
+        os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"),
+        os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['SIM'] = "1'b1"
+    parameters['VENDOR'] = "\"XILINX\""
+    parameters['FAMILY'] = "\"zynquplus\""
+    parameters['USE_CLK90'] = "1'b1"
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )