From d9cf440351c8510da7705f03ef4995d1aae0508c Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Tue, 17 Mar 2026 14:06:55 -0700
Subject: [PATCH] cndm: Initial commit of board control I2C logic

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 src/cndm/rtl/cndm_brd_ctrl_i2c.f              |   3 +
 src/cndm/rtl/cndm_brd_ctrl_i2c.sv             | 949 ++++++++++++++++++
 src/cndm/tb/cndm_brd_ctrl_i2c/Makefile        |  50 +
 .../test_cndm_brd_ctrl_i2c.py                 | 382 +++++++
 .../test_cndm_brd_ctrl_i2c.sv                 | 131 +++
 5 files changed, 1515 insertions(+)
 create mode 100644 src/cndm/rtl/cndm_brd_ctrl_i2c.f
 create mode 100644 src/cndm/rtl/cndm_brd_ctrl_i2c.sv
 create mode 100644 src/cndm/tb/cndm_brd_ctrl_i2c/Makefile
 create mode 100644 src/cndm/tb/cndm_brd_ctrl_i2c/test_cndm_brd_ctrl_i2c.py
 create mode 100644 src/cndm/tb/cndm_brd_ctrl_i2c/test_cndm_brd_ctrl_i2c.sv

diff --git a/src/cndm/rtl/cndm_brd_ctrl_i2c.f b/src/cndm/rtl/cndm_brd_ctrl_i2c.f
new file mode 100644
index 0000000..49358ac
--- /dev/null
+++ b/src/cndm/rtl/cndm_brd_ctrl_i2c.f
@@ -0,0 +1,3 @@
+cndm_brd_ctrl_i2c.sv
+../lib/taxi/src/axis/rtl/taxi_axis_if.sv
+../lib/taxi/src/lss/rtl/taxi_i2c_master.sv
diff --git a/src/cndm/rtl/cndm_brd_ctrl_i2c.sv b/src/cndm/rtl/cndm_brd_ctrl_i2c.sv
new file mode 100644
index 0000000..e2a1325
--- /dev/null
+++ b/src/cndm/rtl/cndm_brd_ctrl_i2c.sv
@@ -0,0 +1,949 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * Board control module
+ */
+module cndm_brd_ctrl_i2c #
+(
+    // Optical module config
+    parameter logic OPTIC_EN = 1'b1,
+    parameter OPTIC_CNT = 2,
+
+    // EEPROM config
+    parameter logic EEPROM_EN = 1'b1,
+    parameter EEPROM_IDX = OPTIC_EN ? OPTIC_CNT : 0,
+
+    // MAC in EEPROM config
+    parameter logic MAC_EEPROM_EN = EEPROM_EN,
+    parameter MAC_EEPROM_IDX = EEPROM_IDX,
+    parameter MAC_EEPROM_OFFSET = 0,
+    parameter MAC_COUNT = OPTIC_CNT,
+    parameter logic MAC_FROM_BASE = 1'b1,
+
+    // Serial number in EEPROM config
+    parameter logic SN_EEPROM_EN = EEPROM_EN,
+    parameter SN_EEPROM_IDX = EEPROM_IDX,
+    parameter SN_EEPROM_OFFSET = 0,
+    parameter SN_LEN = 16,
+
+    // PLL configuration
+    parameter logic PLL_EN = 1'b1,
+    parameter PLL_IDX = EEPROM_IDX + (EEPROM_EN ? 1 : 0),
+    // TODO
+
+    // Mux configuration
+    parameter logic MUX_EN = 1'b1,
+    parameter MUX_CNT = 1,
+    // I2C addresses of muxes
+    parameter logic [MUX_CNT-1:0][6:0] MUX_I2C_ADDR = 7'h74,
+
+    // I2C device config
+    // Optical module commands index list directly, so optical modules must be
+    // listed first and in order, folllowed by other devices
+    // Total nuber of devices
+    parameter DEV_CNT = PLL_IDX + (PLL_EN ? 1 : 0),
+    // Device I2C addresses
+    parameter logic [DEV_CNT-1:0][6:0] DEV_I2C_ADDR = {DEV_CNT{7'h50}},
+    // Device addressing configuration
+    // 31:24 - bank register offset
+    // 23:16 - page register offset
+    // 6 - uses multiple I2C addresses
+    // 5 - has bank register
+    // 4 - has page register
+    // 1:0 - address size (1, 2, 4, or 8 bytes)
+    // Examples:
+    // 2K EEPROM: 32'h00_00_0000
+    // 8K EEPROM: 32'h00_00_0040 (four I2C addresses)
+    // SFP: 32'h00_7f_0050 (two I2C addresses)
+    // QSFP-DD: 32'h7e_7f_0030
+    // Most general optic: 32'h7e_7f_0070
+    parameter logic [DEV_CNT-1:0][31:0] DEV_ADDR_CFG = {DEV_CNT{32'h7e_7f_0070}},
+    // Mux settings for each device
+    parameter logic [DEV_CNT-1:0][MUX_CNT-1:0][7:0] DEV_MUX_MASK = '0,
+
+    // Prescaler for I2C master
+    parameter I2C_PRESCALE = 125000/(400*4)
+)
+(
+    input  wire logic                clk,
+    input  wire logic                rst,
+
+    /*
+     * Board control command interface
+     */
+    taxi_axis_if.snk                 s_axis_cmd,
+    taxi_axis_if.src                 m_axis_rsp,
+
+    /*
+     * I2C interface
+     */
+    input  wire logic                i2c_scl_i,
+    output wire logic                i2c_scl_o,
+    input  wire logic                i2c_sda_i,
+    output wire logic                i2c_sda_o,
+
+    output wire logic [DEV_CNT-1:0]  dev_sel,
+    output wire logic [DEV_CNT-1:0]  dev_rst
+);
+
+// extract parameters
+localparam CMD_ID_W = s_axis_cmd.ID_W;
+
+localparam CL_DEV_IDX = $clog2(DEV_CNT);
+localparam CL_MUX_IDX = $clog2(MUX_CNT);
+
+typedef enum logic [15:0] {
+    CMD_BRD_OP_NOP = 16'h0000,
+
+    CMD_BRD_OP_FLASH_RD  = 16'h0100,
+    CMD_BRD_OP_FLASH_WR  = 16'h0101,
+    CMD_BRD_OP_FLASH_CMD = 16'h0108,
+
+    CMD_BRD_OP_EEPROM_RD = 16'h0200,
+    CMD_BRD_OP_EEPROM_WR = 16'h0201,
+
+    CMD_BRD_OP_OPTIC_RD = 16'h0300,
+    CMD_BRD_OP_OPTIC_WR = 16'h0301,
+
+    CMD_BRD_OP_HWID_SN_RD  = 16'h0400,
+    CMD_BRD_OP_HWID_VPD_RD = 16'h0410,
+    CMD_BRD_OP_HWID_MAC_RD = 16'h0480,
+
+    CMD_BRD_OP_PLL_STATUS_RD   = 16'h0500,
+    CMD_BRD_OP_PLL_TUNE_RAW_RD = 16'h0502,
+    CMD_BRD_OP_PLL_TUNE_RAW_WR = 16'h0503,
+    CMD_BRD_OP_PLL_TUNE_PPT_RD = 16'h0504,
+    CMD_BRD_OP_PLL_TUNE_PPT_WR = 16'h0505,
+
+    CMD_BRD_OP_I2C_RD = 16'h8100,
+    CMD_BRD_OP_I2C_WR = 16'h8101
+} cmd_opcode_t;
+
+typedef enum logic [4:0] {
+    STATE_IDLE,
+    STATE_START,
+    STATE_I2C_START,
+    STATE_I2C_SET_MUX,
+    STATE_I2C_SET_PAGE_1,
+    STATE_I2C_SET_PAGE_2,
+    STATE_I2C_SET_BANK_1,
+    STATE_I2C_SET_BANK_2,
+    STATE_I2C_SET_ADDR_1,
+    STATE_I2C_SET_ADDR_2,
+    STATE_I2C_RD_DATA,
+    STATE_I2C_WR_DATA,
+    STATE_SEND_RSP,
+    STATE_PAD_RSP
+} state_t;
+
+state_t state_reg = STATE_IDLE, state_next;
+state_t ret_state_reg = STATE_IDLE, ret_state_next;
+
+logic s_axis_cmd_tready_reg = 1'b0, s_axis_cmd_tready_next;
+
+assign s_axis_cmd.tready = s_axis_cmd_tready_reg;
+
+logic [31:0] m_axis_rsp_tdata_reg = '0, m_axis_rsp_tdata_next;
+logic m_axis_rsp_tvalid_reg = 1'b0, m_axis_rsp_tvalid_next;
+logic m_axis_rsp_tlast_reg = 1'b0, m_axis_rsp_tlast_next;
+logic [CMD_ID_W-1:0] m_axis_rsp_tid_reg = '0, m_axis_rsp_tid_next;
+
+assign m_axis_rsp.tdata  = m_axis_rsp_tdata_reg;
+assign m_axis_rsp.tkeep  = '1;
+assign m_axis_rsp.tstrb  = m_axis_rsp.tkeep;
+assign m_axis_rsp.tvalid = m_axis_rsp_tvalid_reg;
+assign m_axis_rsp.tlast  = m_axis_rsp_tlast_reg;
+assign m_axis_rsp.tid    = m_axis_rsp_tid_reg;
+assign m_axis_rsp.tdest  = '0;
+assign m_axis_rsp.tuser  = '0;
+
+// command RAM
+localparam CMD_AW = 4;
+
+logic [31:0] cmd_ram[2**CMD_AW] = '{default: '0};
+logic [31:0] cmd_ram_wr_data;
+logic [3:0] cmd_ram_wr_strb;
+logic [CMD_AW-1:0] cmd_ram_wr_addr;
+logic cmd_ram_wr_en;
+logic [CMD_AW-1:0] cmd_ram_rd_addr;
+wire [31:0] cmd_ram_rd_data = cmd_ram[cmd_ram_rd_addr];
+
+taxi_axis_if #(.DATA_W(12), .KEEP_W(1)) axis_i2c_cmd();
+taxi_axis_if #(.DATA_W(8)) axis_i2c_tx();
+taxi_axis_if #(.DATA_W(8)) axis_i2c_rx();
+
+localparam logic [11:0]
+    I2C_CMD_START        = 12'h080,
+    I2C_CMD_READ         = 12'h100,
+    I2C_CMD_WRITE        = 12'h200,
+    I2C_CMD_WRITE_MULTI  = 12'h400,
+    I2C_CMD_STOP         = 12'h800;
+
+taxi_i2c_master
+i2c_master_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+    * Host interface
+    */
+    .s_axis_cmd(axis_i2c_cmd),
+    .s_axis_tx(axis_i2c_tx),
+    .m_axis_rx(axis_i2c_rx),
+
+    /*
+    * I2C interface
+    */
+    .scl_i(i2c_scl_i),
+    .scl_o(i2c_scl_o),
+    .sda_i(i2c_sda_i),
+    .sda_o(i2c_sda_o),
+
+    /*
+    * Status
+    */
+    .busy(),
+    .bus_control(),
+    .bus_active(),
+    .missed_ack(),
+
+    /*
+    * Configuration
+    */
+    .prescale(16'(I2C_PRESCALE)),
+    .stop_on_idle(1'b0)
+);
+
+logic [11:0] axis_i2c_cmd_tdata_reg = '0, axis_i2c_cmd_tdata_next;
+logic axis_i2c_cmd_tvalid_reg = '0, axis_i2c_cmd_tvalid_next;
+
+assign axis_i2c_cmd.tdata  = axis_i2c_cmd_tdata_reg;
+assign axis_i2c_cmd.tkeep  = '1;
+assign axis_i2c_cmd.tstrb  = axis_i2c_cmd.tkeep;
+assign axis_i2c_cmd.tvalid = axis_i2c_cmd_tvalid_reg;
+assign axis_i2c_cmd.tlast  = 1'b1;
+assign axis_i2c_cmd.tid    = '0;
+assign axis_i2c_cmd.tdest  = '0;
+assign axis_i2c_cmd.tuser  = '0;
+
+logic [7:0] axis_i2c_tx_tdata_reg = '0, axis_i2c_tx_tdata_next;
+logic axis_i2c_tx_tlast_reg = '0, axis_i2c_tx_tlast_next;
+logic axis_i2c_tx_tvalid_reg = '0, axis_i2c_tx_tvalid_next;
+
+assign axis_i2c_tx.tdata  = axis_i2c_tx_tdata_reg;
+assign axis_i2c_tx.tkeep  = '1;
+assign axis_i2c_tx.tstrb  = axis_i2c_tx.tkeep;
+assign axis_i2c_tx.tvalid = axis_i2c_tx_tvalid_reg;
+assign axis_i2c_tx.tlast  = axis_i2c_tx_tlast_reg;
+assign axis_i2c_tx.tid    = '0;
+assign axis_i2c_tx.tdest  = '0;
+assign axis_i2c_tx.tuser  = '0;
+
+logic axis_i2c_rx_tready_reg = '0, axis_i2c_rx_tready_next;
+
+assign axis_i2c_rx.tready = axis_i2c_rx_tready_reg;
+
+logic [DEV_CNT-1:0] dev_sel_reg = '0, dev_sel_next;
+logic [DEV_CNT-1:0] dev_rst_reg = '0, dev_rst_next;
+
+assign dev_sel = dev_sel_reg;
+assign dev_rst = dev_rst_reg;
+
+logic cmd_frame_reg = 1'b0, cmd_frame_next;
+logic [3:0] cmd_wr_ptr_reg = '0, cmd_wr_ptr_next;
+logic rsp_frame_reg = 1'b0, rsp_frame_next;
+logic [3:0] rsp_rd_ptr_reg = '0, rsp_rd_ptr_next;
+
+logic drop_cmd_reg = 1'b0, drop_cmd_next;
+
+logic [15:0] opcode_reg = '0, opcode_next;
+logic [15:0] idx_reg = '0, idx_next;
+logic [31:0] flags_reg = '0, flags_next;
+logic [31:0] dw2_reg = '0, dw2_next;
+logic [31:0] dw3_reg = '0, dw3_next;
+logic [31:0] dw4_reg = '0, dw4_next;
+
+logic [5:0] cmd_ptr_reg = '0, cmd_ptr_next;
+logic [15:0] cnt_reg = '0, cnt_next;
+
+logic [CL_MUX_IDX-1:0] mux_idx_reg = '0, mux_idx_next;
+logic [CL_DEV_IDX-1:0] dev_idx_reg = '0, dev_idx_next;
+
+logic [6:0] i2c_addr_reg = '0, i2c_addr_next;
+logic [31:0] dev_addr_reg = '0, dev_addr_next;
+logic [7:0] dev_bank_reg = '0, dev_bank_next;
+logic [7:0] dev_page_reg = '0, dev_page_next;
+logic [31:0] dev_addr_cfg_reg = '0, dev_addr_cfg_next;
+logic [1:0] addr_ptr_reg = '0, addr_ptr_next;
+logic mode_write_reg = 1'b0, mode_write_next;
+
+always_comb begin
+    state_next = STATE_IDLE;
+    ret_state_next = ret_state_reg;
+
+    s_axis_cmd_tready_next = 1'b0;
+
+    m_axis_rsp_tdata_next = m_axis_rsp_tdata_reg;
+    m_axis_rsp_tvalid_next = m_axis_rsp_tvalid_reg && !m_axis_rsp.tready;
+    m_axis_rsp_tlast_next = m_axis_rsp_tlast_reg;
+    m_axis_rsp_tid_next = m_axis_rsp_tid_reg;
+
+    axis_i2c_cmd_tdata_next = axis_i2c_cmd_tdata_reg;
+    axis_i2c_cmd_tvalid_next = axis_i2c_cmd_tvalid_reg && !axis_i2c_cmd.tready;
+
+    axis_i2c_tx_tdata_next = axis_i2c_tx_tdata_reg;
+    axis_i2c_tx_tlast_next = axis_i2c_tx_tlast_reg;
+    axis_i2c_tx_tvalid_next = axis_i2c_tx_tvalid_reg && !axis_i2c_tx.tready;
+
+    axis_i2c_rx_tready_next = 1'b0;
+
+    dev_sel_next = dev_sel_reg;
+    dev_rst_next = dev_rst_reg;
+
+    cmd_ram_wr_data = s_axis_cmd.tdata;
+    cmd_ram_wr_strb = '1;
+    cmd_ram_wr_addr = cmd_wr_ptr_reg;
+    cmd_ram_wr_en = 1'b0;
+    cmd_ram_rd_addr = '0;
+
+    cmd_frame_next = cmd_frame_reg;
+    cmd_wr_ptr_next = cmd_wr_ptr_reg;
+    rsp_frame_next = rsp_frame_reg;
+    rsp_rd_ptr_next = rsp_rd_ptr_reg;
+
+    drop_cmd_next = drop_cmd_reg;
+
+    opcode_next = opcode_reg;
+    idx_next = idx_reg;
+    flags_next = flags_reg;
+    dw2_next = dw2_reg;
+    dw3_next = dw3_reg;
+    dw4_next = dw4_reg;
+
+    cmd_ptr_next = cmd_ptr_reg;
+    cnt_next = cnt_reg;
+
+    mux_idx_next = mux_idx_reg;
+    dev_idx_next = dev_idx_reg;
+
+    i2c_addr_next = i2c_addr_reg;
+    dev_addr_next = dev_addr_reg;
+    dev_bank_next = dev_bank_reg;
+    dev_page_next = dev_page_reg;
+    dev_addr_cfg_next = dev_addr_cfg_reg;
+    addr_ptr_next = addr_ptr_reg;
+    mode_write_next = mode_write_reg;
+
+    if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin
+        if (s_axis_cmd.tlast) begin
+            cmd_frame_next = 1'b0;
+            cmd_wr_ptr_next = '0;
+        end else begin
+            cmd_wr_ptr_next = cmd_wr_ptr_reg + 1;
+            cmd_frame_next = 1'b1;
+        end
+    end
+
+    case (state_reg)
+        STATE_IDLE: begin
+            s_axis_cmd_tready_next = !m_axis_rsp_tvalid_reg && !rsp_frame_reg;
+
+            cmd_ram_wr_data = s_axis_cmd.tdata;
+            cmd_ram_wr_strb = '1;
+            cmd_ram_wr_addr = cmd_wr_ptr_reg;
+            cmd_ram_wr_en = 1'b1;
+
+            // save some important fields
+            case (cmd_wr_ptr_reg)
+                4'd0: {opcode_next, idx_next} = s_axis_cmd.tdata;
+                4'd1: flags_next = s_axis_cmd.tdata;
+                4'd2: dw2_next = s_axis_cmd.tdata;
+                4'd3: dw3_next = s_axis_cmd.tdata;
+                4'd4: dw4_next = s_axis_cmd.tdata;
+                default: begin end
+            endcase
+
+            if (s_axis_cmd.tready && s_axis_cmd.tvalid && !drop_cmd_reg) begin
+                if (s_axis_cmd.tlast || &cmd_wr_ptr_reg) begin
+                    s_axis_cmd_tready_next = !s_axis_cmd.tlast;
+                    drop_cmd_next = !s_axis_cmd.tlast;
+                    state_next = STATE_START;
+                end else begin
+                    state_next = STATE_IDLE;
+                end
+            end else begin
+                state_next = STATE_IDLE;
+            end
+        end
+        STATE_START: begin
+            cmd_ptr_next = '0;
+            cnt_next = '0;
+
+            case (opcode_reg)
+                CMD_BRD_OP_NOP: begin
+                    // NOP
+                    m_axis_rsp_tdata_next = '0; // TODO
+                    m_axis_rsp_tvalid_next = 1'b1;
+                    m_axis_rsp_tlast_next = 1'b0;
+
+                    state_next = STATE_SEND_RSP;
+                end
+                CMD_BRD_OP_EEPROM_RD: begin
+                    if (EEPROM_EN) begin
+                        dev_idx_next = EEPROM_IDX;
+                        i2c_addr_next = DEV_I2C_ADDR[dev_idx_next];
+                        dev_addr_next = dw3_reg;
+                        dev_bank_next = dw2_reg[15:8];
+                        dev_page_next = dw2_reg[7:0];
+                        cnt_next = 16'(dw4_reg);
+                        cmd_ptr_next = 24;
+
+                        mode_write_next = 1'b0;
+
+                        ret_state_next = STATE_SEND_RSP;
+                        state_next = STATE_I2C_START;
+                    end else begin
+                        m_axis_rsp_tdata_next = '0; // TODO error code
+                        m_axis_rsp_tvalid_next = 1'b1;
+                        m_axis_rsp_tlast_next = 1'b0;
+
+                        state_next = STATE_PAD_RSP;
+                    end
+                end
+                CMD_BRD_OP_EEPROM_WR: begin
+                    if (EEPROM_EN) begin
+                        dev_idx_next = EEPROM_IDX;
+                        i2c_addr_next = DEV_I2C_ADDR[dev_idx_next];
+                        dev_addr_next = dw3_reg;
+                        dev_bank_next = dw2_reg[15:8];
+                        dev_page_next = dw2_reg[7:0];
+                        cnt_next = 16'(dw4_reg);
+                        cmd_ptr_next = 24;
+
+                        mode_write_next = 1'b1;
+
+                        ret_state_next = STATE_SEND_RSP;
+                        state_next = STATE_I2C_START;
+                    end else begin
+                        m_axis_rsp_tdata_next = '0; // TODO error code
+                        m_axis_rsp_tvalid_next = 1'b1;
+                        m_axis_rsp_tlast_next = 1'b0;
+
+                        state_next = STATE_PAD_RSP;
+                    end
+                end
+                CMD_BRD_OP_OPTIC_RD: begin
+                    if (OPTIC_EN) begin
+                        dev_idx_next = CL_DEV_IDX'(idx_reg);
+                        i2c_addr_next = DEV_I2C_ADDR[dev_idx_next];
+                        dev_addr_next = dw3_reg;
+                        dev_bank_next = dw2_reg[15:8];
+                        dev_page_next = dw2_reg[7:0];
+                        cnt_next = 16'(dw4_reg);
+                        cmd_ptr_next = 24;
+
+                        mode_write_next = 1'b0;
+
+                        ret_state_next = STATE_SEND_RSP;
+                        state_next = STATE_I2C_START;
+                    end else begin
+                        m_axis_rsp_tdata_next = '0; // TODO error code
+                        m_axis_rsp_tvalid_next = 1'b1;
+                        m_axis_rsp_tlast_next = 1'b0;
+
+                        state_next = STATE_PAD_RSP;
+                    end
+                end
+                CMD_BRD_OP_OPTIC_WR: begin
+                    if (OPTIC_EN) begin
+                        dev_idx_next = CL_DEV_IDX'(idx_reg);
+                        i2c_addr_next = DEV_I2C_ADDR[dev_idx_next];
+                        dev_addr_next = dw3_reg;
+                        dev_bank_next = dw2_reg[15:8];
+                        dev_page_next = dw2_reg[7:0];
+                        cnt_next = 16'(dw4_reg);
+                        cmd_ptr_next = 24;
+
+                        mode_write_next = 1'b1;
+
+                        ret_state_next = STATE_SEND_RSP;
+                        state_next = STATE_I2C_START;
+                    end else begin
+                        m_axis_rsp_tdata_next = '0; // TODO error code
+                        m_axis_rsp_tvalid_next = 1'b1;
+                        m_axis_rsp_tlast_next = 1'b0;
+
+                        state_next = STATE_PAD_RSP;
+                    end
+                end
+                CMD_BRD_OP_HWID_SN_RD: begin
+                    if (SN_EEPROM_EN) begin
+                        dev_idx_next = SN_EEPROM_IDX;
+                        i2c_addr_next = DEV_I2C_ADDR[dev_idx_next];
+                        dev_addr_next = SN_EEPROM_OFFSET;
+                        dev_bank_next = 0;
+                        dev_page_next = 0;
+                        cnt_next = SN_LEN;
+                        cmd_ptr_next = 24;
+
+                        // TODO write len
+
+                        mode_write_next = 1'b0;
+
+                        ret_state_next = STATE_SEND_RSP;
+                        state_next = STATE_I2C_START;
+                    end else begin
+                        m_axis_rsp_tdata_next = '0; // TODO error code
+                        m_axis_rsp_tvalid_next = 1'b1;
+                        m_axis_rsp_tlast_next = 1'b0;
+
+                        state_next = STATE_PAD_RSP;
+                    end
+                end
+                // CMD_BRD_OP_HWID_VPD_RD
+                CMD_BRD_OP_HWID_MAC_RD: begin
+                    if (MAC_EEPROM_EN) begin
+                        dev_idx_next = MAC_EEPROM_IDX;
+                        i2c_addr_next = DEV_I2C_ADDR[dev_idx_next];
+                        dev_addr_next = MAC_EEPROM_OFFSET;
+                        dev_bank_next = 0;
+                        dev_page_next = 0;
+                        cnt_next = 6;
+                        cmd_ptr_next = 26;
+
+                        // TODO write count, len
+
+                        mode_write_next = 1'b0;
+
+                        ret_state_next = STATE_SEND_RSP;
+                        state_next = STATE_I2C_START;
+                    end else begin
+                        m_axis_rsp_tdata_next = '0; // TODO error code
+                        m_axis_rsp_tvalid_next = 1'b1;
+                        m_axis_rsp_tlast_next = 1'b0;
+
+                        state_next = STATE_PAD_RSP;
+                    end
+                end
+                // CMD_BRD_OP_PLL_STATUS_RD
+                // CMD_BRD_OP_PLL_TUNE_RAW_RD
+                // CMD_BRD_OP_PLL_TUNE_RAW_WR
+                // CMD_BRD_OP_PLL_TUNE_PPT_RD
+                // CMD_BRD_OP_PLL_TUNE_PPT_WR
+                CMD_BRD_OP_I2C_RD: begin
+                    dev_idx_next = CL_DEV_IDX'(idx_reg);
+                    i2c_addr_next = DEV_I2C_ADDR[dev_idx_next];
+                    dev_addr_next = dw3_reg;
+                    dev_bank_next = dw2_reg[15:8];
+                    dev_page_next = dw2_reg[7:0];
+                    cnt_next = 16'(dw4_reg);
+                    cmd_ptr_next = 24;
+
+                    mode_write_next = 1'b0;
+
+                    ret_state_next = STATE_SEND_RSP;
+                    state_next = STATE_I2C_START;
+                end
+                CMD_BRD_OP_I2C_WR: begin
+                    dev_idx_next = CL_DEV_IDX'(idx_reg);
+                    i2c_addr_next = DEV_I2C_ADDR[dev_idx_next];
+                    dev_addr_next = dw3_reg;
+                    dev_bank_next = dw2_reg[15:8];
+                    dev_page_next = dw2_reg[7:0];
+                    cnt_next = 16'(dw4_reg);
+                    cmd_ptr_next = 24;
+
+                    mode_write_next = 1'b1;
+
+                    ret_state_next = STATE_SEND_RSP;
+                    state_next = STATE_I2C_START;
+                end
+                default: begin
+                    // unknown opcode
+                    m_axis_rsp_tdata_next = '0; // TODO error code
+                    m_axis_rsp_tvalid_next = 1'b1;
+                    m_axis_rsp_tlast_next = 1'b0;
+
+                    state_next = STATE_PAD_RSP;
+                end
+            endcase
+        end
+        STATE_I2C_START: begin
+            mux_idx_next = '0;
+            dev_sel_next[dev_idx_reg] = 1'b1;
+
+            dev_addr_cfg_next = DEV_ADDR_CFG[dev_idx_reg];
+            addr_ptr_next = dev_addr_cfg_next[1:0];
+
+            if (MUX_EN) begin
+                state_next = STATE_I2C_SET_MUX;
+            end else begin
+                if (dev_addr_cfg_next[5]) begin
+                    state_next = STATE_I2C_SET_BANK_1;
+                end else if (dev_addr_cfg_next[4]) begin
+                    state_next = STATE_I2C_SET_PAGE_1;
+                end else begin
+                    state_next = STATE_I2C_SET_ADDR_1;
+                end
+            end
+        end
+        STATE_I2C_SET_MUX: begin
+            // Configure I2C mux(es)
+            if (!axis_i2c_cmd_tvalid_reg && !axis_i2c_tx_tvalid_reg) begin
+                axis_i2c_cmd_tdata_next = 12'(MUX_I2C_ADDR[mux_idx_reg]) | I2C_CMD_START | I2C_CMD_WRITE | I2C_CMD_STOP;
+                axis_i2c_cmd_tvalid_next = 1'b1;
+
+                axis_i2c_tx_tdata_next = DEV_MUX_MASK[dev_idx_reg][mux_idx_reg];
+                axis_i2c_tx_tlast_next = 1'b1;
+                axis_i2c_tx_tvalid_next = 1'b1;
+
+                mux_idx_next = mux_idx_reg + 1;
+
+                if (mux_idx_reg == CL_MUX_IDX'(MUX_CNT-1)) begin
+                    if (dev_addr_cfg_next[5]) begin
+                        state_next = STATE_I2C_SET_BANK_1;
+                    end else if (dev_addr_cfg_next[4]) begin
+                        state_next = STATE_I2C_SET_PAGE_1;
+                    end else begin
+                        state_next = STATE_I2C_SET_ADDR_1;
+                    end
+                end else begin
+                    state_next = STATE_I2C_SET_MUX;
+                end
+            end else begin
+                state_next = STATE_I2C_SET_MUX;
+            end
+        end
+        STATE_I2C_SET_BANK_1: begin
+            // Select bank register
+            if (!axis_i2c_cmd_tvalid_reg && !axis_i2c_tx_tvalid_reg) begin
+                axis_i2c_cmd_tdata_next = 12'(i2c_addr_reg) | I2C_CMD_START | I2C_CMD_WRITE;
+                axis_i2c_cmd_tvalid_next = 1'b1;
+
+                axis_i2c_tx_tdata_next = dev_addr_cfg_reg[24 +: 8];
+                axis_i2c_tx_tlast_next = 1'b1;
+                axis_i2c_tx_tvalid_next = 1'b1;
+
+                state_next = STATE_I2C_SET_BANK_2;
+            end else begin
+                state_next = STATE_I2C_SET_BANK_1;
+            end
+        end
+        STATE_I2C_SET_BANK_2: begin
+            // Set bank register
+            if (!axis_i2c_cmd_tvalid_reg && !axis_i2c_tx_tvalid_reg) begin
+                axis_i2c_cmd_tdata_next = 12'(i2c_addr_reg) | I2C_CMD_WRITE;
+                axis_i2c_cmd_tvalid_next = 1'b1;
+
+                axis_i2c_tx_tdata_next = dev_bank_reg;
+                axis_i2c_tx_tlast_next = 1'b1;
+                axis_i2c_tx_tvalid_next = 1'b1;
+
+                if (dev_addr_cfg_next[4]) begin
+                    state_next = STATE_I2C_SET_PAGE_1;
+                end else begin
+                    state_next = STATE_I2C_SET_ADDR_1;
+                end
+            end else begin
+                state_next = STATE_I2C_SET_BANK_2;
+            end
+        end
+        STATE_I2C_SET_PAGE_1: begin
+            // Select page register
+            if (!axis_i2c_cmd_tvalid_reg && !axis_i2c_tx_tvalid_reg) begin
+                axis_i2c_cmd_tdata_next = 12'(i2c_addr_reg) | I2C_CMD_START | I2C_CMD_WRITE;
+                axis_i2c_cmd_tvalid_next = 1'b1;
+
+                axis_i2c_tx_tdata_next = dev_addr_cfg_reg[16 +: 8];
+                axis_i2c_tx_tlast_next = 1'b1;
+                axis_i2c_tx_tvalid_next = 1'b1;
+
+                state_next = STATE_I2C_SET_PAGE_2;
+            end else begin
+                state_next = STATE_I2C_SET_PAGE_1;
+            end
+        end
+        STATE_I2C_SET_PAGE_2: begin
+            // Set page register
+            if (!axis_i2c_cmd_tvalid_reg && !axis_i2c_tx_tvalid_reg) begin
+                axis_i2c_cmd_tdata_next = 12'(i2c_addr_reg) | I2C_CMD_WRITE;
+                axis_i2c_cmd_tvalid_next = 1'b1;
+
+                axis_i2c_tx_tdata_next = dev_page_reg;
+                axis_i2c_tx_tlast_next = 1'b1;
+                axis_i2c_tx_tvalid_next = 1'b1;
+
+                state_next = STATE_I2C_SET_ADDR_1;
+            end else begin
+                state_next = STATE_I2C_SET_PAGE_2;
+            end
+        end
+        STATE_I2C_SET_ADDR_1: begin
+            // Set device internal address
+            if (!axis_i2c_cmd_tvalid_reg && !axis_i2c_tx_tvalid_reg) begin
+                axis_i2c_cmd_tdata_next = 12'(i2c_addr_reg) | I2C_CMD_START | I2C_CMD_WRITE;
+                axis_i2c_cmd_tvalid_next = 1'b1;
+
+                axis_i2c_tx_tdata_next = dev_addr_reg[addr_ptr_reg*8 +: 8];
+                axis_i2c_tx_tlast_next = 1'b1;
+                axis_i2c_tx_tvalid_next = 1'b1;
+
+                addr_ptr_next = addr_ptr_reg - 1;
+
+                if (addr_ptr_reg == 0) begin
+                    if (mode_write_reg) begin
+                        state_next = STATE_I2C_WR_DATA;
+                    end else begin
+                        state_next = STATE_I2C_RD_DATA;
+                    end
+                end else begin
+                    state_next = STATE_I2C_SET_ADDR_2;
+                end
+            end else begin
+                state_next = STATE_I2C_SET_ADDR_1;
+            end
+        end
+        STATE_I2C_SET_ADDR_2: begin
+            // Set device internal address
+            if (!axis_i2c_cmd_tvalid_reg && !axis_i2c_tx_tvalid_reg) begin
+                axis_i2c_cmd_tdata_next = 12'(i2c_addr_reg) | I2C_CMD_WRITE;
+                axis_i2c_cmd_tvalid_next = 1'b1;
+
+                axis_i2c_tx_tdata_next = dev_addr_reg[addr_ptr_reg*8 +: 8];
+                axis_i2c_tx_tlast_next = 1'b1;
+                axis_i2c_tx_tvalid_next = 1'b1;
+
+                addr_ptr_next = addr_ptr_reg - 1;
+
+                if (addr_ptr_reg == 0) begin
+                    if (mode_write_reg) begin
+                        state_next = STATE_I2C_WR_DATA;
+                    end else begin
+                        state_next = STATE_I2C_RD_DATA;
+                    end
+                end else begin
+                    state_next = STATE_I2C_SET_ADDR_2;
+                end
+            end else begin
+                state_next = STATE_I2C_SET_ADDR_2;
+            end
+        end
+        STATE_I2C_RD_DATA: begin
+            // Copy data from I2C to RAM
+
+            // start I2C reads
+            if (!axis_i2c_cmd_tvalid_reg) begin
+                axis_i2c_cmd_tdata_next = 12'(i2c_addr_reg) | I2C_CMD_READ | ((cnt_reg == 0 || cnt_reg == 1) ? I2C_CMD_STOP : '0);
+                if (cnt_reg != 0) begin
+                    axis_i2c_cmd_tvalid_next = 1'b1;
+                    cnt_next = cnt_reg - 1;
+                end
+            end
+
+            // store data
+            axis_i2c_rx_tready_next = 1'b1;
+
+            cmd_ram_wr_data = {4{axis_i2c_rx.tdata}};
+            cmd_ram_wr_strb = '0;
+            cmd_ram_wr_strb[cmd_ptr_reg[1:0]] = 1'b1;
+            cmd_ram_wr_addr = cmd_ptr_reg[5:2];
+
+            if (axis_i2c_rx.tready && axis_i2c_rx.tvalid) begin
+                axis_i2c_rx_tready_next = 1'b0;
+                cmd_ram_wr_en = 1'b1;
+                cmd_ptr_next = cmd_ptr_reg + 1;
+                if (axis_i2c_rx.tlast) begin
+                    state_next = ret_state_reg;
+                end else begin
+                    state_next = STATE_I2C_RD_DATA;
+                end
+            end else begin
+                state_next = STATE_I2C_RD_DATA;
+            end
+        end
+        STATE_I2C_WR_DATA: begin
+            // Copy data from RAM to I2C
+            cmd_ram_rd_addr = cmd_ptr_reg[5:2];
+
+            if (!axis_i2c_cmd_tvalid_reg && !axis_i2c_tx_tvalid_reg) begin
+                cmd_ptr_next = cmd_ptr_reg + 1;
+
+                axis_i2c_cmd_tdata_next = 12'(i2c_addr_reg) | I2C_CMD_WRITE | ((cnt_reg == 0 || cnt_reg == 1) ? I2C_CMD_STOP : '0);
+                axis_i2c_cmd_tvalid_next = 1'b1;
+
+                axis_i2c_tx_tdata_next = cmd_ram_rd_data[cmd_ptr_reg[1:0]*8 +: 8];
+                axis_i2c_tx_tlast_next = 1'b1;
+                axis_i2c_tx_tvalid_next = 1'b1;
+
+                cnt_next = cnt_reg - 1;
+                if (cnt_reg == 0) begin
+                    state_next = ret_state_reg;
+                end else begin
+                    state_next = STATE_I2C_WR_DATA;
+                end
+            end else begin
+                state_next = STATE_I2C_WR_DATA;
+            end
+        end
+        STATE_SEND_RSP: begin
+            // send response in the form of an edited command
+            cmd_ram_rd_addr = rsp_rd_ptr_reg;
+            if (m_axis_rsp.tready || !m_axis_rsp.tvalid) begin
+                m_axis_rsp_tdata_next = cmd_ram_rd_data;
+                m_axis_rsp_tvalid_next = 1'b1;
+                m_axis_rsp_tlast_next = &rsp_rd_ptr_reg;
+
+                if (&rsp_rd_ptr_reg) begin
+                    state_next = STATE_IDLE;
+                end else begin
+                    state_next = STATE_SEND_RSP;
+                end
+            end else begin
+                state_next = STATE_SEND_RSP;
+            end
+        end
+        STATE_PAD_RSP: begin
+            // zero pad response
+            if (m_axis_rsp.tready || !m_axis_rsp.tvalid) begin
+                m_axis_rsp_tdata_next = '0;
+                m_axis_rsp_tvalid_next = 1'b1;
+                m_axis_rsp_tlast_next = &rsp_rd_ptr_reg;
+
+                if (&rsp_rd_ptr_reg) begin
+                    state_next = STATE_IDLE;
+                end else begin
+                    state_next = STATE_PAD_RSP;
+                end
+            end else begin
+                state_next = STATE_PAD_RSP;
+            end
+        end
+        default: begin
+            // unknown state; return to idle
+            state_next = STATE_IDLE;
+        end
+    endcase
+
+    if (drop_cmd_reg) begin
+        s_axis_cmd_tready_next = 1'b1;
+
+        if (s_axis_cmd.tready && s_axis_cmd.tvalid) begin
+            drop_cmd_next = !s_axis_cmd.tlast;
+        end
+    end
+
+    if (m_axis_rsp_tvalid_next && (!m_axis_rsp_tvalid_reg || m_axis_rsp.tready)) begin
+        if (m_axis_rsp_tlast_next) begin
+            rsp_rd_ptr_next = '0;
+        end else begin
+            rsp_rd_ptr_next = rsp_rd_ptr_reg + 1;
+            rsp_frame_next = 1'b1;
+        end
+    end
+
+    if (m_axis_rsp.tready && m_axis_rsp.tvalid) begin
+        if (m_axis_rsp.tlast) begin
+            rsp_frame_next = 1'b0;
+            rsp_rd_ptr_next = '0;
+        end
+    end
+end
+
+always_ff @(posedge clk) begin
+    if (cmd_ram_wr_en) begin
+        for (integer i = 0; i < 4; i = i + 1) begin
+            if (cmd_ram_wr_strb[i]) begin
+                cmd_ram[cmd_ram_wr_addr][i*8 +: 8] = cmd_ram_wr_data[i*8 +: 8];
+            end
+        end
+    end
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+    ret_state_reg <= ret_state_next;
+
+    s_axis_cmd_tready_reg <= s_axis_cmd_tready_next;
+
+    m_axis_rsp_tdata_reg <= m_axis_rsp_tdata_next;
+    m_axis_rsp_tvalid_reg <= m_axis_rsp_tvalid_next;
+    m_axis_rsp_tlast_reg <= m_axis_rsp_tlast_next;
+    m_axis_rsp_tid_reg <= m_axis_rsp_tid_next;
+
+    axis_i2c_cmd_tdata_reg <= axis_i2c_cmd_tdata_next;
+    axis_i2c_cmd_tvalid_reg <= axis_i2c_cmd_tvalid_next;
+
+    axis_i2c_tx_tdata_reg <= axis_i2c_tx_tdata_next;
+    axis_i2c_tx_tlast_reg <= axis_i2c_tx_tlast_next;
+    axis_i2c_tx_tvalid_reg <= axis_i2c_tx_tvalid_next;
+
+    axis_i2c_rx_tready_reg <= axis_i2c_rx_tready_next;
+
+    dev_sel_reg <= dev_sel_next;
+    dev_rst_reg <= dev_rst_next;
+
+    cmd_frame_reg <= cmd_frame_next;
+    cmd_wr_ptr_reg <= cmd_wr_ptr_next;
+    rsp_frame_reg <= rsp_frame_next;
+    rsp_rd_ptr_reg <= rsp_rd_ptr_next;
+
+    drop_cmd_reg <= drop_cmd_next;
+
+    opcode_reg <= opcode_next;
+    idx_reg <= idx_next;
+    flags_reg <= flags_next;
+    dw2_reg <= dw2_next;
+    dw3_reg <= dw3_next;
+    dw4_reg <= dw4_next;
+
+    cmd_ptr_reg <= cmd_ptr_next;
+    cnt_reg <= cnt_next;
+
+    mux_idx_reg <= mux_idx_next;
+    dev_idx_reg <= dev_idx_next;
+
+    i2c_addr_reg <= i2c_addr_next;
+    dev_addr_reg <= dev_addr_next;
+    dev_bank_reg <= dev_bank_next;
+    dev_page_reg <= dev_page_next;
+    dev_addr_cfg_reg <= dev_addr_cfg_next;
+    addr_ptr_reg <= addr_ptr_next;
+    mode_write_reg <= mode_write_next;
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+
+        s_axis_cmd_tready_reg <= 1'b0;
+        m_axis_rsp_tvalid_reg <= 1'b0;
+
+        axis_i2c_cmd_tvalid_reg <= 1'b0;
+        axis_i2c_tx_tvalid_reg <= 1'b0;
+        axis_i2c_rx_tready_reg <= 1'b0;
+
+        dev_sel_reg <= '0;
+        dev_rst_reg <= '0;
+
+        cmd_frame_reg <= 1'b0;
+        cmd_wr_ptr_reg <= '0;
+        rsp_frame_reg <= 1'b0;
+        rsp_rd_ptr_reg <= '0;
+
+        drop_cmd_reg <= 1'b0;
+    end
+end
+
+endmodule
+
+`resetall
diff --git a/src/cndm/tb/cndm_brd_ctrl_i2c/Makefile b/src/cndm/tb/cndm_brd_ctrl_i2c/Makefile
new file mode 100644
index 0000000..9920e2f
--- /dev/null
+++ b/src/cndm/tb/cndm_brd_ctrl_i2c/Makefile
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2026 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ns
+
+RTL_DIR = ../../rtl
+LIB_DIR = ../../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+DUT      = cndm_brd_ctrl_i2c
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+# export PARAM_DEFAULT_PRESCALE := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/src/cndm/tb/cndm_brd_ctrl_i2c/test_cndm_brd_ctrl_i2c.py b/src/cndm/tb/cndm_brd_ctrl_i2c/test_cndm_brd_ctrl_i2c.py
new file mode 100644
index 0000000..eb0d78c
--- /dev/null
+++ b/src/cndm/tb/cndm_brd_ctrl_i2c/test_cndm_brd_ctrl_i2c.py
@@ -0,0 +1,382 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+import os
+import struct
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+
+from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink
+from cocotbext.axi.utils import hexdump_str
+from cocotbext.i2c import I2cMemory
+
+
+CMD_BRD_OP_NOP = 0x0000
+
+CMD_BRD_OP_FLASH_RD  = 0x0100
+CMD_BRD_OP_FLASH_WR  = 0x0101
+CMD_BRD_OP_FLASH_CMD = 0x0108
+
+CMD_BRD_OP_EEPROM_RD = 0x0200
+CMD_BRD_OP_EEPROM_WR = 0x0201
+
+CMD_BRD_OP_OPTIC_RD = 0x0300
+CMD_BRD_OP_OPTIC_WR = 0x0301
+
+CMD_BRD_OP_HWID_SN_RD  = 0x0400
+CMD_BRD_OP_HWID_VPD_RD = 0x0410
+CMD_BRD_OP_HWID_MAC_RD = 0x0480
+
+CMD_BRD_OP_PLL_STATUS_RD   = 0x0500
+CMD_BRD_OP_PLL_TUNE_RAW_RD = 0x0502
+CMD_BRD_OP_PLL_TUNE_RAW_WR = 0x0503
+CMD_BRD_OP_PLL_TUNE_PPT_RD = 0x0504
+CMD_BRD_OP_PLL_TUNE_PPT_WR = 0x0505
+
+CMD_BRD_OP_I2C_RD = 0x8100
+CMD_BRD_OP_I2C_WR = 0x8101
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 4, units="ns").start())
+
+        self.brd_ctrl_cmd = AxiStreamSource(AxiStreamBus(dut.s_axis_cmd), dut.clk, dut.rst)
+        self.brd_ctrl_rsp = AxiStreamSink(AxiStreamBus(dut.m_axis_rsp), dut.clk, dut.rst)
+
+        self.i2c_eeprom = I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
+            scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x54, size=256)
+        self.sfp0 = I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
+            scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x50, size=256)
+        self.sfp1 = I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
+            scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x51, size=256)
+        self.si570 = I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
+            scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x5D, size=256)
+        self.mux1 = I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
+            scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x74, size=256)
+        self.mux2 = I2cMemory(sda=dut.i2c_sda_o, sda_o=dut.i2c_sda_i,
+            scl=dut.i2c_scl_o, scl_o=dut.i2c_scl_i, addr=0x75, size=256)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.i2c_eeprom.write_mem(0, bytes.fromhex("""
+        37 35 37 35 31 39 32 37 31 37 33 32 2d 36 39 39
+        39 36 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+        00 0a 35 03 72 c9 00 00 00 00 00 00 00 00 00 00
+        54 53 53 30 31 36 35 2d 30 32 20 20 20 20 20 20
+        5b 31 31 31 31 31 31 31 31 31 5d 20 20 20 20 20
+        57 65 64 2c 20 31 36 20 41 75 67 20 32 30 31 37
+        31 30 3a 33 35 3a 35 36 2b 30 38 30 30 20 20 20
+        ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+        ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+        ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+        ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+        ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+        ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+        4b 43 55 31 30 35 20 20 20 20 20 20 20 20 20 20
+        31 2e 31 20 20 20 20 20 20 20 20 20 20 20 20 20
+        ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+    """))
+
+    tb.sfp0.write_mem(0, bytes.fromhex("""
+        03 04 21 00 00 00 00 00 04 00 00 00 67 00 00 00
+        00 00 03 00 41 6d 70 68 65 6e 6f 6c 20 20 20 20
+        20 20 20 20 00 41 50 48 35 37 31 35 34 30 30 30
+        32 20 20 20 20 20 20 20 4b 20 20 20 01 00 00 f7
+        00 00 00 00 41 50 46 30 39 34 38 30 30 32 30 32
+        37 39 20 20 30 39 31 31 32 34 20 20 00 00 00 c1
+        ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+        ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00
+    """ + " ff"*128))
+
+    tb.sfp1.write_mem(0, bytes.fromhex("""
+        03 04 21 00 00 00 00 00 04 00 00 00 67 00 00 00
+        00 00 03 00 41 6d 70 68 65 6e 6f 6c 20 20 20 20
+        20 20 20 20 00 41 50 48 35 37 31 35 34 30 30 30
+        32 20 20 20 20 20 20 20 4b 20 20 20 01 00 00 f7
+        00 00 00 00 41 50 46 30 39 34 38 30 30 32 30 32
+        37 39 20 20 30 39 31 31 32 34 20 20 00 00 00 c1
+        ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+        ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00
+    """ + " ff"*128))
+
+    tb.si570.write_mem(0, bytes.fromhex("""
+        4f 02 32 a1 3d 20 00 01 c2 bb ff 84 82 07 c2 c0
+        00 00 00 00 c2 c0 00 00 00 07 c2 c0 00 00 00 0c
+        b9 09 80 00 00 00 00 00 00 00 00 00 00 00 00 00
+        00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+        00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+        00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+        00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+        00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+        20 7f 86 81 7b 81 03 00 10 08 00 00 00 00 02 bb
+        ff 84 82 00 00 00 62 00 00 00 00 00 00 00 00 00
+    """))
+
+    tb.log.info("Read MAC")
+    cmd = struct.pack("<HHLbbbbLLL",
+        0, # index
+        CMD_BRD_OP_HWID_MAC_RD, # opcode
+        0, # flags
+        0, # page
+        0, # bank
+        0, # dev addr offset
+        0, # rsvd
+        0, # addr
+        0, # len
+        0, # rsvd
+    )
+
+    await tb.brd_ctrl_cmd.send(cmd)
+    rsp = await tb.brd_ctrl_rsp.recv()
+
+    tb.log.info("Response: %s", rsp)
+    tb.log.info("MAC: %s", ':'.join(x.hex() for x in struct.unpack_from('6c', rsp.tdata, 24+2)))
+
+    tb.log.info("Read SN")
+    cmd = struct.pack("<HHLbbbbLLL",
+        0, # index
+        CMD_BRD_OP_HWID_SN_RD, # opcode
+        0, # flags
+        0, # page
+        0, # bank
+        0, # dev addr offset
+        0, # rsvd
+        0, # addr
+        0, # len
+        0, # rsvd
+    )
+
+    await tb.brd_ctrl_cmd.send(cmd)
+    rsp = await tb.brd_ctrl_rsp.recv()
+
+    tb.log.info("Response: %s", rsp)
+    tb.log.info("SN: %s", rsp.tdata[24:24+32].strip(b' \x00'))
+
+    tb.log.info("Read EEPROM")
+    cmd = struct.pack("<HHLbbbbLLL",
+        0, # index
+        CMD_BRD_OP_EEPROM_RD, # opcode
+        0, # flags
+        0, # page
+        0, # bank
+        0, # dev addr offset
+        0, # rsvd
+        0x00, # addr
+        32, # len
+        0, # rsvd
+    )
+
+    await tb.brd_ctrl_cmd.send(cmd)
+    rsp = await tb.brd_ctrl_rsp.recv()
+
+    tb.log.info("Response: %s", rsp)
+    tb.log.info("Data: %s", rsp.tdata[24:24+32])
+
+    tb.log.info("Read SFP0")
+    cmd = struct.pack("<HHLbbbbLLL",
+        0, # index
+        CMD_BRD_OP_OPTIC_RD, # opcode
+        0, # flags
+        0, # page
+        0, # bank
+        0, # dev addr offset
+        0, # rsvd
+        0x00, # addr
+        32, # len
+        0, # rsvd
+    )
+
+    await tb.brd_ctrl_cmd.send(cmd)
+    rsp = await tb.brd_ctrl_rsp.recv()
+
+    tb.log.info("Response: %s", rsp)
+    tb.log.info("Data: %s", rsp.tdata[24:24+32])
+
+    tb.log.info("Read SFP1")
+    cmd = struct.pack("<HHLbbbbLLL",
+        1, # index
+        CMD_BRD_OP_OPTIC_RD, # opcode
+        0, # flags
+        0, # page
+        0, # bank
+        0, # dev addr offset
+        0, # rsvd
+        0x00, # addr
+        32, # len
+        0, # rsvd
+    )
+
+    await tb.brd_ctrl_cmd.send(cmd)
+    rsp = await tb.brd_ctrl_rsp.recv()
+
+    tb.log.info("Response: %s", rsp)
+    tb.log.info("Data: %s", rsp.tdata[24:24+32])
+
+    tb.log.info("Write EEPROM")
+    data = b"EEPROM write data"
+
+    cmd = struct.pack("<HHLbbbbLLL",
+        0, # index
+        CMD_BRD_OP_EEPROM_WR, # opcode
+        0, # flags
+        0, # page
+        0, # bank
+        0, # dev addr offset
+        0, # rsvd
+        0x80, # addr
+        len(data), # len
+        0, # rsvd
+    )+data
+
+    await tb.brd_ctrl_cmd.send(cmd)
+    rsp = await tb.brd_ctrl_rsp.recv()
+
+    tb.log.info("Response: %s", rsp)
+
+    tb.log.info("Write SFP0")
+    data = b"SFP0 write data"
+
+    cmd = struct.pack("<HHLbbbbLLL",
+        0, # index
+        CMD_BRD_OP_OPTIC_WR, # opcode
+        0, # flags
+        0, # page
+        0, # bank
+        0, # dev addr offset
+        0, # rsvd
+        0x80, # addr
+        len(data), # len
+        0, # rsvd
+    )+data
+
+    await tb.brd_ctrl_cmd.send(cmd)
+    rsp = await tb.brd_ctrl_rsp.recv()
+
+    tb.log.info("Response: %s", rsp)
+
+    tb.log.info("Write SFP1")
+    data = b"SFP1 write data"
+
+    cmd = struct.pack("<HHLbbbbLLL",
+        1, # index
+        CMD_BRD_OP_OPTIC_WR, # opcode
+        0, # flags
+        0, # page
+        0, # bank
+        0, # dev addr offset
+        0, # rsvd
+        0x80, # addr
+        len(data), # len
+        0, # rsvd
+    )+data
+
+    await tb.brd_ctrl_cmd.send(cmd)
+    rsp = await tb.brd_ctrl_rsp.recv()
+
+    tb.log.info("Response: %s", rsp)
+
+    for k in range(1000):
+        await RisingEdge(dut.clk)
+
+    tb.log.info("EEPROM data:")
+    tb.log.info(hexdump_str(tb.i2c_eeprom.mem, 0, 256))
+
+    tb.log.info("PLL data:")
+    tb.log.info(hexdump_str(tb.si570.mem, 0, 256))
+
+    tb.log.info("SFP0 data:")
+    tb.log.info(hexdump_str(tb.sfp0.mem, 0, 256))
+
+    tb.log.info("SFP1 data:")
+    tb.log.info(hexdump_str(tb.sfp1.mem, 0, 256))
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
+taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_cndm_brd_ctrl_i2c(request):
+    dut = "cndm_brd_ctrl_i2c"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, f"{dut}.f"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )
diff --git a/src/cndm/tb/cndm_brd_ctrl_i2c/test_cndm_brd_ctrl_i2c.sv b/src/cndm/tb/cndm_brd_ctrl_i2c/test_cndm_brd_ctrl_i2c.sv
new file mode 100644
index 0000000..cefd82a
--- /dev/null
+++ b/src/cndm/tb/cndm_brd_ctrl_i2c/test_cndm_brd_ctrl_i2c.sv
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2026 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * I2C master testbench
+ */
+module test_cndm_brd_ctrl_i2c #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter logic OPTIC_EN = 1'b1,
+    parameter OPTIC_CNT = 2,
+
+    parameter logic EEPROM_EN = 1'b1,
+    parameter EEPROM_IDX = OPTIC_EN ? OPTIC_CNT : 0,
+
+    parameter logic MAC_EEPROM_EN = EEPROM_EN,
+    parameter MAC_EEPROM_IDX = EEPROM_IDX,
+    parameter MAC_EEPROM_OFFSET = 32,
+    parameter MAC_COUNT = OPTIC_CNT,
+    parameter logic MAC_FROM_BASE = 1'b1,
+
+    parameter logic SN_EEPROM_EN = EEPROM_EN,
+    parameter SN_EEPROM_IDX = EEPROM_IDX,
+    parameter SN_EEPROM_OFFSET = 0,
+    parameter SN_LEN = 32,
+
+    parameter logic PLL_EN = 1'b1,
+    parameter PLL_IDX = EEPROM_IDX + (EEPROM_EN ? 1 : 0),
+
+    parameter logic MUX_EN = 1'b1,
+    parameter MUX_CNT = 2,
+    parameter logic [MUX_CNT-1:0][6:0] MUX_I2C_ADDR = {7'h75, 7'h74},
+
+    parameter DEV_CNT = PLL_IDX + (PLL_EN ? 1 : 0),
+    parameter logic [DEV_CNT-1:0][6:0] DEV_I2C_ADDR = {7'h5D, 7'h54, 7'h51, 7'h50},
+    parameter logic [DEV_CNT-1:0][31:0] DEV_ADDR_CFG = {32'h00_00_0000, 32'h00_00_0040, 32'h7e_7f_0070, 32'h7e_7f_0070},
+    parameter logic [DEV_CNT-1:0][MUX_CNT-1:0][7:0] DEV_MUX_MASK = {{8'h00, 8'h01}, {8'h07, 8'h00}, {8'h00, 8'h08}, {8'h00, 8'h04}},
+
+    parameter I2C_PRESCALE = 2
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(
+    .DATA_W(32),
+    .KEEP_EN(1),
+    .ID_EN(1),
+    .ID_W(4),
+    .USER_EN(1),
+    .USER_W(1)
+) s_axis_cmd(), m_axis_rsp();
+
+logic i2c_scl_i;
+logic i2c_scl_o;
+logic i2c_sda_i;
+logic i2c_sda_o;
+
+logic [DEV_CNT-1:0] dev_sel;
+logic [DEV_CNT-1:0] dev_rst;
+
+cndm_brd_ctrl_i2c #(
+    .OPTIC_EN(OPTIC_EN),
+    .OPTIC_CNT(OPTIC_CNT),
+
+    .EEPROM_EN(EEPROM_EN),
+    .EEPROM_IDX(EEPROM_IDX),
+
+    .MAC_EEPROM_EN(MAC_EEPROM_EN),
+    .MAC_EEPROM_IDX(MAC_EEPROM_IDX),
+    .MAC_EEPROM_OFFSET(MAC_EEPROM_OFFSET),
+    .MAC_COUNT(MAC_COUNT),
+    .MAC_FROM_BASE(MAC_FROM_BASE),
+
+    .SN_EEPROM_EN(SN_EEPROM_EN),
+    .SN_EEPROM_IDX(SN_EEPROM_IDX),
+    .SN_EEPROM_OFFSET(SN_EEPROM_OFFSET),
+    .SN_LEN(SN_LEN),
+
+    .PLL_EN(PLL_EN),
+    .PLL_IDX(PLL_IDX),
+
+    .MUX_EN(MUX_EN),
+    .MUX_CNT(MUX_CNT),
+    .MUX_I2C_ADDR(MUX_I2C_ADDR),
+
+    .DEV_CNT(DEV_CNT),
+    .DEV_I2C_ADDR(DEV_I2C_ADDR),
+    .DEV_ADDR_CFG(DEV_ADDR_CFG),
+    .DEV_MUX_MASK(DEV_MUX_MASK),
+
+    .I2C_PRESCALE(I2C_PRESCALE)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Board control command interface
+     */
+    .s_axis_cmd(s_axis_cmd),
+    .m_axis_rsp(m_axis_rsp),
+
+    /*
+     * I2C interface
+     */
+    .i2c_scl_i(i2c_scl_i),
+    .i2c_scl_o(i2c_scl_o),
+    .i2c_sda_i(i2c_sda_i),
+    .i2c_sda_o(i2c_sda_o),
+
+    .dev_sel(dev_sel),
+    .dev_rst(dev_rst)
+);
+
+endmodule
+
+`resetall