mirror of
https://github.com/fpganinja/taxi.git
synced 2025-12-09 17:08:38 -08:00
example/VCU108: Add 25G MACs on QSFP28 port on VCU108
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -15,7 +15,12 @@ Authors:
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/*
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* FPGA core logic
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*/
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module fpga_core
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module fpga_core #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexu"
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)
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(
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/*
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* Clock: 125MHz
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@@ -56,10 +61,29 @@ module fpga_core
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output wire logic phy_gmii_tx_en,
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output wire logic phy_gmii_tx_er,
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output wire logic phy_reset_n,
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input wire logic phy_int_n
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input wire logic phy_int_n,
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/*
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* Ethernet: QSFP28
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*/
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input wire logic [3:0] qsfp_rx_p,
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input wire logic [3:0] qsfp_rx_n,
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output wire logic [3:0] qsfp_tx_p,
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output wire logic [3:0] qsfp_tx_n,
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input wire logic qsfp_mgt_refclk_0_p,
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input wire logic qsfp_mgt_refclk_0_n,
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// input wire logic qsfp_mgt_refclk_1_p,
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// input wire logic qsfp_mgt_refclk_1_n,
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// output wire logic qsfp_recclk_p,
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// output wire logic qsfp_recclk_n,
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output wire logic qsfp_modsell,
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output wire logic qsfp_resetl,
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input wire logic qsfp_modprsl,
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input wire logic qsfp_intl,
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output wire logic qsfp_lpmode
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);
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assign led = 8'(sw);
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// assign led = 8'(sw);
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// UART
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assign uart_rts = 0;
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@@ -110,9 +134,9 @@ taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
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taxi_eth_mac_1g_fifo #(
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.PADDING_EN(1),
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.MIN_FRAME_LEN(64),
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.TX_FIFO_DEPTH(4096),
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.TX_FIFO_DEPTH(16384),
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.TX_FRAME_FIFO(1),
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.RX_FIFO_DEPTH(4096),
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.RX_FIFO_DEPTH(16384),
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.RX_FRAME_FIFO(1)
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)
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eth_mac_inst (
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@@ -173,6 +197,296 @@ eth_mac_inst (
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.cfg_rx_enable(1'b1)
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);
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// QSFP28
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assign qsfp_modsell = 1'b0;
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assign qsfp_resetl = 1'b1;
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assign qsfp_lpmode = 1'b0;
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wire [3:0] qsfp_tx_clk;
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wire [3:0] qsfp_tx_rst;
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wire [3:0] qsfp_rx_clk;
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wire [3:0] qsfp_rx_rst;
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wire [3:0] qsfp_rx_status;
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assign led = {qsfp_rx_status, qsfp_rx_rst};
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wire qsfp_gtpowergood;
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wire qsfp_mgt_refclk_0;
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wire qsfp_mgt_refclk_0_int;
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wire qsfp_mgt_refclk_0_bufg;
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wire qsfp_rst;
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taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_tx[3:0]();
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taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[3:0]();
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taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[3:0]();
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if (SIM) begin
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assign qsfp_gtpowergood = 1'b1;
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assign qsfp_mgt_refclk_0 = qsfp_mgt_refclk_0_p;
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assign qsfp_mgt_refclk_0_int = qsfp_mgt_refclk_0_p;
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assign qsfp_mgt_refclk_0_bufg = qsfp_mgt_refclk_0_int;
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end else begin
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IBUFDS_GTE3 ibufds_gte3_qsfp_mgt_refclk_0_inst (
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.I (qsfp_mgt_refclk_0_p),
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.IB (qsfp_mgt_refclk_0_n),
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.CEB (1'b0),
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.O (qsfp_mgt_refclk_0),
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.ODIV2 (qsfp_mgt_refclk_0_int)
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);
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BUFG_GT bufg_gt_qsfp_mgt_refclk_0_inst (
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.CE (qsfp_gtpowergood),
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.CEMASK (1'b1),
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.CLR (1'b0),
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.CLRMASK (1'b1),
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.DIV (3'd0),
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.I (qsfp_mgt_refclk_0_int),
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.O (qsfp_mgt_refclk_0_bufg)
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);
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end
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taxi_sync_reset #(
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.N(4)
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)
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qsfp_sync_reset_inst (
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.clk(qsfp_mgt_refclk_0_bufg),
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.rst(rst),
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.out(qsfp_rst)
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);
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taxi_eth_mac_25g_us #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.CNT(4),
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// GT type
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.GT_TYPE("GTY"),
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// PHY parameters
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.PADDING_EN(1'b1),
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.DIC_EN(1'b1),
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.MIN_FRAME_LEN(64),
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.PTP_TS_EN(1'b0),
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.PTP_TS_FMT_TOD(1'b1),
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.PTP_TS_W(96),
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.PRBS31_EN(1'b0),
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.TX_SERDES_PIPELINE(1),
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.RX_SERDES_PIPELINE(1),
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.COUNT_125US(125000/6.4)
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)
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qsfp_mac_inst (
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.xcvr_ctrl_clk(clk),
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.xcvr_ctrl_rst(qsfp_rst),
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/*
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* Common
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*/
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.xcvr_gtpowergood_out(qsfp_gtpowergood),
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.xcvr_gtrefclk00_in(qsfp_mgt_refclk_0),
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.xcvr_qpll0lock_out(),
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.xcvr_qpll0clk_out(),
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.xcvr_qpll0refclk_out(),
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/*
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* Serial data
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*/
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.xcvr_txp(qsfp_tx_p),
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.xcvr_txn(qsfp_tx_n),
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.xcvr_rxp(qsfp_rx_p),
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.xcvr_rxn(qsfp_rx_n),
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/*
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* MAC clocks
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*/
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.rx_clk(qsfp_rx_clk),
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.rx_rst_in('0),
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.rx_rst_out(qsfp_rx_rst),
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.tx_clk(qsfp_tx_clk),
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.tx_rst_in('0),
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.tx_rst_out(qsfp_tx_rst),
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.ptp_sample_clk('0),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_qsfp_tx),
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.m_axis_tx_cpl(axis_qsfp_tx_cpl),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_qsfp_rx),
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/*
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* PTP clock
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*/
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.tx_ptp_ts('0),
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.tx_ptp_ts_step('0),
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.rx_ptp_ts('0),
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.rx_ptp_ts_step('0),
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/*
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* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
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*/
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.tx_lfc_req('0),
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.tx_lfc_resend('0),
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.rx_lfc_en('0),
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.rx_lfc_req(),
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.rx_lfc_ack('0),
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/*
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* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
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*/
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.tx_pfc_req('0),
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.tx_pfc_resend('0),
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.rx_pfc_en('0),
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.rx_pfc_req(),
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.rx_pfc_ack('0),
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/*
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* Pause interface
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*/
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.tx_lfc_pause_en('0),
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.tx_pause_req('0),
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.tx_pause_ack(),
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/*
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* Status
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*/
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.tx_start_packet(),
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.tx_error_underflow(),
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.rx_start_packet(),
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.rx_error_count(),
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.rx_error_bad_frame(),
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.rx_error_bad_fcs(),
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.rx_bad_block(),
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.rx_sequence_error(),
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.rx_block_lock(),
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.rx_high_ber(),
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.rx_status(qsfp_rx_status),
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.stat_tx_mcf(),
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.stat_rx_mcf(),
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.stat_tx_lfc_pkt(),
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.stat_tx_lfc_xon(),
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.stat_tx_lfc_xoff(),
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.stat_tx_lfc_paused(),
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.stat_tx_pfc_pkt(),
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.stat_tx_pfc_xon(),
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.stat_tx_pfc_xoff(),
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.stat_tx_pfc_paused(),
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.stat_rx_lfc_pkt(),
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.stat_rx_lfc_xon(),
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.stat_rx_lfc_xoff(),
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.stat_rx_lfc_paused(),
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.stat_rx_pfc_pkt(),
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.stat_rx_pfc_xon(),
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.stat_rx_pfc_xoff(),
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.stat_rx_pfc_paused(),
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/*
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* Configuration
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*/
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.cfg_ifg('{4{8'd12}}),
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.cfg_tx_enable('1),
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.cfg_rx_enable('1),
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.cfg_tx_prbs31_enable('0),
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.cfg_rx_prbs31_enable('0),
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.cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
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.cfg_mcf_rx_check_eth_dst_mcast('1),
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.cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
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.cfg_mcf_rx_check_eth_dst_ucast('0),
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.cfg_mcf_rx_eth_src('{4{48'd0}}),
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.cfg_mcf_rx_check_eth_src('0),
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.cfg_mcf_rx_eth_type('{4{16'h8808}}),
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.cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
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.cfg_mcf_rx_check_opcode_lfc('1),
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.cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
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.cfg_mcf_rx_check_opcode_pfc('1),
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.cfg_mcf_rx_forward('0),
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.cfg_mcf_rx_enable('0),
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.cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
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.cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
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.cfg_tx_lfc_eth_type('{4{16'h8808}}),
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.cfg_tx_lfc_opcode('{4{16'h0001}}),
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.cfg_tx_lfc_en('0),
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.cfg_tx_lfc_quanta('{4{16'hffff}}),
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.cfg_tx_lfc_refresh('{4{16'h7fff}}),
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.cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
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.cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
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.cfg_tx_pfc_eth_type('{4{16'h8808}}),
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.cfg_tx_pfc_opcode('{4{16'h0101}}),
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.cfg_tx_pfc_en('0),
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.cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
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.cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
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.cfg_rx_lfc_opcode('{4{16'h0001}}),
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.cfg_rx_lfc_en('0),
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.cfg_rx_pfc_opcode('{4{16'h0101}}),
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.cfg_rx_pfc_en('0)
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);
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for (genvar n = 0; n < 4; n = n + 1) begin : qsfp_ch
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taxi_axis_async_fifo #(
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.DEPTH(16384),
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.RAM_PIPELINE(2),
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.FRAME_FIFO(1),
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.USER_BAD_FRAME_VALUE(1'b1),
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.USER_BAD_FRAME_MASK(1'b1),
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.DROP_OVERSIZE_FRAME(1),
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.DROP_BAD_FRAME(1),
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.DROP_WHEN_FULL(1)
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)
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ch_fifo (
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/*
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* AXI4-Stream input (sink)
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*/
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.s_clk(qsfp_rx_clk[n]),
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.s_rst(qsfp_rx_rst[n]),
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.s_axis(axis_qsfp_rx[n]),
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/*
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* AXI4-Stream output (source)
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*/
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.m_clk(qsfp_tx_clk[n]),
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.m_rst(qsfp_tx_rst[n]),
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.m_axis(axis_qsfp_tx[n]),
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/*
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* Pause
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*/
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.s_pause_req(1'b0),
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.s_pause_ack(),
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.m_pause_req(1'b0),
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.m_pause_ack(),
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/*
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* Status
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*/
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.s_status_depth(),
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.s_status_depth_commit(),
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.s_status_overflow(),
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.s_status_bad_frame(),
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.s_status_good_frame(),
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.m_status_depth(),
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.m_status_depth_commit(),
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.m_status_overflow(),
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.m_status_bad_frame(),
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.m_status_good_frame()
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);
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end
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endmodule
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`resetall
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