From dd2a0d1bf3efd23f2b42244cf9c4ad3c563611c5 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 17 Feb 2025 00:13:06 -0800 Subject: [PATCH] example: Add example design for Arty A7 Signed-off-by: Alex Forencich --- example/Arty/fpga/README.md | 29 ++ example/Arty/fpga/common/vivado.mk | 153 +++++++++ example/Arty/fpga/fpga.xdc | 145 +++++++++ example/Arty/fpga/fpga/Makefile | 77 +++++ example/Arty/fpga/lib/taxi | 1 + example/Arty/fpga/rtl/fpga.sv | 290 ++++++++++++++++++ example/Arty/fpga/rtl/fpga_core.sv | 204 ++++++++++++ example/Arty/fpga/tb/fpga_core/Makefile | 52 ++++ .../Arty/fpga/tb/fpga_core/test_fpga_core.py | 200 ++++++++++++ 9 files changed, 1151 insertions(+) create mode 100644 example/Arty/fpga/README.md create mode 100644 example/Arty/fpga/common/vivado.mk create mode 100644 example/Arty/fpga/fpga.xdc create mode 100644 example/Arty/fpga/fpga/Makefile create mode 120000 example/Arty/fpga/lib/taxi create mode 100644 example/Arty/fpga/rtl/fpga.sv create mode 100644 example/Arty/fpga/rtl/fpga_core.sv create mode 100644 example/Arty/fpga/tb/fpga_core/Makefile create mode 100644 example/Arty/fpga/tb/fpga_core/test_fpga_core.py diff --git a/example/Arty/fpga/README.md b/example/Arty/fpga/README.md new file mode 100644 index 0000000..8515e04 --- /dev/null +++ b/example/Arty/fpga/README.md @@ -0,0 +1,29 @@ +# Taxi Example Design for Arty A7 + +## Introduction + +This example design targets the Digilent Arty A7 FPGA board. + +The design places a looped-back MAC on the BASE-T port, as well as a looped-back UART on the USB UART. + +* USB UART + * Looped-back UART +* RJ-45 Ethernet port with TI DP83848J PHY + * Looped-back MAC via MII + +## Board details + +* FPGA: XC7A35TICSG324-1L +* PHY: TI DP83848J via MII + +## How to build + +Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH. + +## How to test + +Run `make program` to program the board with Vivado. + +To test the looped-back UART, use any serial terminal software like minicom, screen, etc. The looped-back UART will echo typed text back without modification. + +To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems. diff --git a/example/Arty/fpga/common/vivado.mk b/example/Arty/fpga/common/vivado.mk new file mode 100644 index 0000000..07c56e2 --- /dev/null +++ b/example/Arty/fpga/common/vivado.mk @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: MIT +################################################################### +# +# Xilinx Vivado FPGA Makefile +# +# Copyright (c) 2016-2025 Alex Forencich +# +################################################################### +# +# Parameters: +# FPGA_TOP - Top module name +# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) +# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) +# SYN_FILES - list of source files +# INC_FILES - list of include files +# XDC_FILES - list of timing constraint files +# XCI_FILES - list of IP XCI files +# IP_TCL_FILES - list of IP TCL files (sourced during project creation) +# CONFIG_TCL_FILES - list of config TCL files (sourced before each build) +# +# Note: both SYN_FILES and INC_FILES support file list files. File list +# files are files with a .f extension that contain a list of additional +# files to include, one path relative to the .f file location per line. +# The .f files are processed recursively, and then the complete file list +# is de-duplicated, with later files in the list taking precedence. +# +# Example: +# +# FPGA_TOP = fpga +# FPGA_FAMILY = VirtexUltrascale +# FPGA_DEVICE = xcvu095-ffva2104-2-e +# SYN_FILES = rtl/fpga.v +# XDC_FILES = fpga.xdc +# XCI_FILES = ip/pcspma.xci +# include ../common/vivado.mk +# +################################################################### + +# phony targets +.PHONY: fpga vivado tmpclean clean distclean + +# prevent make from deleting intermediate files and reports +.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm +.SECONDARY: + +CONFIG ?= config.mk +-include $(CONFIG) + +FPGA_TOP ?= fpga +PROJECT ?= $(FPGA_TOP) +XDC_FILES ?= $(PROJECT).xdc + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES))) +INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES))) + +################################################################### +# Main Targets +# +# all: build everything (fpga) +# fpga: build FPGA config +# vivado: open project in Vivado +# tmpclean: remove intermediate files +# clean: remove output files and project files +# distclean: remove archived output files +################################################################### + +all: fpga + +fpga: $(PROJECT).bit + +vivado: $(PROJECT).xpr + vivado $(PROJECT).xpr + +tmpclean:: + -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl + +clean:: tmpclean + -rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl + -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt + +distclean:: clean + -rm -rf rev + +################################################################### +# Target implementations +################################################################### + +# Vivado project file + +# create fresh project if Makefile or IP files have changed +create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES) + rm -rf defines.v + touch defines.v + for x in $(DEFS); do echo '`define' $$x >> defines.v; done + echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ + echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@ + echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ + echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@ + for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done + for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +# source config TCL scripts if any source file has changed +update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES) + echo "open_project -quiet $(PROJECT).xpr" > $@ + for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done + +$(PROJECT).xpr: create_project.tcl update_config.tcl + vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) + +# synthesis run +$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr + echo "open_project $(PROJECT).xpr" > run_synth.tcl + echo "reset_run synth_1" >> run_synth.tcl + echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl + echo "wait_on_run synth_1" >> run_synth.tcl + vivado -nojournal -nolog -mode batch -source run_synth.tcl + +# implementation run +$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp + echo "open_project $(PROJECT).xpr" > run_impl.tcl + echo "reset_run impl_1" >> run_impl.tcl + echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl + echo "wait_on_run impl_1" >> run_impl.tcl + echo "open_run impl_1" >> run_impl.tcl + echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl + echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl + vivado -nojournal -nolog -mode batch -source run_impl.tcl + +# output files (including potentially bit, bin, ltx, and xsa) +$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp + echo "open_project $(PROJECT).xpr" > generate_bit.tcl + echo "open_run impl_1" >> generate_bit.tcl + echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl + echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl + echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl + vivado -nojournal -nolog -mode batch -source generate_bit.tcl + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . + ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin . + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi + mkdir -p rev + COUNT=100; \ + while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ + cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \ + if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \ + if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi diff --git a/example/Arty/fpga/fpga.xdc b/example/Arty/fpga/fpga.xdc new file mode 100644 index 0000000..b13330b --- /dev/null +++ b/example/Arty/fpga/fpga.xdc @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2014-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# XDC constraints for the Digilent Arty board +# part: xc7a35t-csg324-1 + +# General configuration +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS true [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] + +# 100 MHz clock +set_property -dict {LOC E3 IOSTANDARD LVCMOS33} [get_ports clk] +create_clock -period 10.000 -name clk [get_ports clk] + +# LEDs +set_property -dict {LOC G6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led0_r] +set_property -dict {LOC F6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led0_g] +set_property -dict {LOC E1 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led0_b] +set_property -dict {LOC G3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led1_r] +set_property -dict {LOC J4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led1_g] +set_property -dict {LOC G4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led1_b] +set_property -dict {LOC J3 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led2_r] +set_property -dict {LOC J2 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led2_g] +set_property -dict {LOC H4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led2_b] +set_property -dict {LOC K1 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led3_r] +set_property -dict {LOC H6 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led3_g] +set_property -dict {LOC K2 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led3_b] +set_property -dict {LOC H5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led4] +set_property -dict {LOC J5 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led5] +set_property -dict {LOC T9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led6] +set_property -dict {LOC T10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports led7] + +set_false_path -to [get_ports {led0_r led0_g led0_b led1_r led1_g led1_b led2_r led2_g led2_b led3_r led3_g led3_b led4 led5 led6 led7}] +set_output_delay 0 [get_ports {led0_r led0_g led0_b led1_r led1_g led1_b led2_r led2_g led2_b led3_r led3_g led3_b led4 led5 led6 led7}] + +# Reset button +set_property -dict {LOC C2 IOSTANDARD LVCMOS33} [get_ports reset_n] + +set_false_path -from [get_ports {reset_n}] +set_input_delay 0 [get_ports {reset_n}] + +# Push buttons +set_property -dict {LOC D9 IOSTANDARD LVCMOS33} [get_ports {btn[0]}] +set_property -dict {LOC C9 IOSTANDARD LVCMOS33} [get_ports {btn[1]}] +set_property -dict {LOC B9 IOSTANDARD LVCMOS33} [get_ports {btn[2]}] +set_property -dict {LOC B8 IOSTANDARD LVCMOS33} [get_ports {btn[3]}] + +set_false_path -from [get_ports {btn[*]}] +set_input_delay 0 [get_ports {btn[*]}] + +# Toggle switches +set_property -dict {LOC A8 IOSTANDARD LVCMOS33} [get_ports {sw[0]}] +set_property -dict {LOC C11 IOSTANDARD LVCMOS33} [get_ports {sw[1]}] +set_property -dict {LOC C10 IOSTANDARD LVCMOS33} [get_ports {sw[2]}] +set_property -dict {LOC A10 IOSTANDARD LVCMOS33} [get_ports {sw[3]}] + +set_false_path -from [get_ports {sw[*]}] +set_input_delay 0 [get_ports {sw[*]}] + +# GPIO +# PMOD JA +#set_property -dict {LOC G13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja1}] ;# PMOD JA pin 1 +#set_property -dict {LOC B11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja2}] ;# PMOD JA pin 2 +#set_property -dict {LOC A11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja3}] ;# PMOD JA pin 3 +#set_property -dict {LOC D12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja4}] ;# PMOD JA pin 4 +#set_property -dict {LOC D13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja7}] ;# PMOD JA pin 7 +#set_property -dict {LOC B18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja8}] ;# PMOD JA pin 8 +#set_property -dict {LOC A18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja9}] ;# PMOD JA pin 9 +#set_property -dict {LOC K16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_ja10}] ;# PMOD JA pin 10 +# PMOD JB +#set_property -dict {LOC E15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb1}] ;# PMOD JB pin 1 +#set_property -dict {LOC E16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb2}] ;# PMOD JB pin 2 +#set_property -dict {LOC D15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb3}] ;# PMOD JB pin 3 +#set_property -dict {LOC C15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb4}] ;# PMOD JB pin 4 +#set_property -dict {LOC J17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb7}] ;# PMOD JB pin 7 +#set_property -dict {LOC J18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb8}] ;# PMOD JB pin 8 +#set_property -dict {LOC K15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb9}] ;# PMOD JB pin 9 +#set_property -dict {LOC J15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jb10}] ;# PMOD JB pin 10 +# PMOD JC +#set_property -dict {LOC U12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc1}] ;# PMOD JC pin 1 +#set_property -dict {LOC V12 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc2}] ;# PMOD JC pin 2 +#set_property -dict {LOC V10 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc3}] ;# PMOD JC pin 3 +#set_property -dict {LOC V11 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc4}] ;# PMOD JC pin 4 +#set_property -dict {LOC U14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc7}] ;# PMOD JC pin 7 +#set_property -dict {LOC V14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc8}] ;# PMOD JC pin 8 +#set_property -dict {LOC T13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc9}] ;# PMOD JC pin 9 +#set_property -dict {LOC U13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jc10}] ;# PMOD JC pin 10 +# PMOD JD +#set_property -dict {LOC D4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd1}] ;# PMOD JD pin 1 +#set_property -dict {LOC D3 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd2}] ;# PMOD JD pin 2 +#set_property -dict {LOC F4 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd3}] ;# PMOD JD pin 3 +#set_property -dict {LOC F3 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd4}] ;# PMOD JD pin 4 +#set_property -dict {LOC E2 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd7}] ;# PMOD JD pin 7 +#set_property -dict {LOC D2 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd8}] ;# PMOD JD pin 8 +#set_property -dict {LOC H2 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd9}] ;# PMOD JD pin 9 +#set_property -dict {LOC G2 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {gpio_jd10}] ;# PMOD JD pin 10 + +# UART +set_property -dict {LOC D10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports uart_txd] +set_property -dict {LOC A9 IOSTANDARD LVCMOS33} [get_ports uart_rxd] + +set_false_path -to [get_ports {uart_txd}] +set_output_delay 0 [get_ports {uart_txd}] +set_false_path -from [get_ports {uart_rxd}] +set_input_delay 0 [get_ports {uart_rxd}] + +# Ethernet MII PHY +set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk] +set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}] +set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}] +set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}] +set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}] +set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv] +set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er] +set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk] +set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] +set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] +set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] +set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] +set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en] +set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col] +set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs] +set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk] +set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] +#set_property -dict {LOC K13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_mdio] +#set_property -dict {LOC F16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_mdc] + +create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk] +create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk] + +set_false_path -to [get_ports {phy_ref_clk phy_reset_n}] +set_output_delay 0 [get_ports {phy_ref_clk phy_reset_n}] + +#set_false_path -to [get_ports {phy_mdio phy_mdc}] +#set_output_delay 0 [get_ports {phy_mdio phy_mdc}] +#set_false_path -from [get_ports {phy_mdio}] +#set_input_delay 0 [get_ports {phy_mdio}] diff --git a/example/Arty/fpga/fpga/Makefile b/example/Arty/fpga/fpga/Makefile new file mode 100644 index 0000000..a603308 --- /dev/null +++ b/example/Arty/fpga/fpga/Makefile @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich +# + +# FPGA settings +FPGA_PART = xc7a35t-csg324-1 +FPGA_TOP = fpga +FPGA_ARCH = artix7 + +# Files for synthesis +SYN_FILES = ../rtl/fpga.sv +SYN_FILES += ../rtl/fpga_core.sv +SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_mii_fifo.f +SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv +SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv +SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv + +# XDC files +XDC_FILES = ../fpga.xdc +XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl +XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl +XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl + +include ../common/vivado.mk + +program: $(PROJECT).bit + echo "open_hw_manager" > program.tcl + echo "connect_hw_server" >> program.tcl + echo "open_hw_target" >> program.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl + echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl + echo "program_hw_devices [current_hw_device]" >> program.tcl + echo "exit" >> program.tcl + vivado -nojournal -nolog -mode batch -source program.tcl + +$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit + echo "write_cfgmem -force -format mcs -size 16 -interface SPIx4 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl + echo "exit" >> generate_mcs.tcl + vivado -nojournal -nolog -mode batch -source generate_mcs.tcl + mkdir -p rev + COUNT=100; \ + while [ -e rev/$*_rev$$COUNT.bit ]; \ + do COUNT=$$((COUNT+1)); done; \ + COUNT=$$((COUNT-1)); \ + for x in .mcs .prm; \ + do cp $*$$x rev/$*_rev$$COUNT$$x; \ + echo "Output: rev/$*_rev$$COUNT$$x"; done; + +flash: $(PROJECT).mcs $(PROJECT).prm + echo "open_hw_manager" > flash.tcl + echo "connect_hw_server" >> flash.tcl + echo "open_hw_target" >> flash.tcl + echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl + echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl + echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25ql128-spi-x1_x2_x4}] 0]" >> flash.tcl + echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl + echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl + echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl + echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl + echo "program_hw_devices [current_hw_device]" >> flash.tcl + echo "refresh_hw_device [current_hw_device]" >> flash.tcl + echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl + echo "boot_hw_device [current_hw_device]" >> flash.tcl + echo "exit" >> flash.tcl + vivado -nojournal -nolog -mode batch -source flash.tcl diff --git a/example/Arty/fpga/lib/taxi b/example/Arty/fpga/lib/taxi new file mode 120000 index 0000000..11a54ed --- /dev/null +++ b/example/Arty/fpga/lib/taxi @@ -0,0 +1 @@ +../../../../ \ No newline at end of file diff --git a/example/Arty/fpga/rtl/fpga.sv b/example/Arty/fpga/rtl/fpga.sv new file mode 100644 index 0000000..4105aaa --- /dev/null +++ b/example/Arty/fpga/rtl/fpga.sv @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2014-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA top-level module + */ +module fpga # +( + // simulation (set to avoid vendor primitives) + parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") + parameter VENDOR = "XILINX", + // device family + parameter FAMILY = "artix7" +) +( + /* + * Clock: 100MHz + * Reset: Push button, active low + */ + input wire logic clk, + input wire logic reset_n, + + /* + * GPIO + */ + input wire logic [3:0] sw, + input wire logic [3:0] btn, + output wire logic led0_r, + output wire logic led0_g, + output wire logic led0_b, + output wire logic led1_r, + output wire logic led1_g, + output wire logic led1_b, + output wire logic led2_r, + output wire logic led2_g, + output wire logic led2_b, + output wire logic led3_r, + output wire logic led3_g, + output wire logic led3_b, + output wire logic led4, + output wire logic led5, + output wire logic led6, + output wire logic led7, + + /* + * UART: 115200 bps, 8N1 + */ + input wire logic uart_rxd, + output wire logic uart_txd, + + /* + * Ethernet: 100BASE-T MII + */ + output wire logic phy_ref_clk, + input wire logic phy_rx_clk, + input wire logic [3:0] phy_rxd, + input wire logic phy_rx_dv, + input wire logic phy_rx_er, + input wire logic phy_tx_clk, + output wire logic [3:0] phy_txd, + output wire logic phy_tx_en, + input wire logic phy_col, + input wire logic phy_crs, + output wire logic phy_reset_n +); + +// Clock and reset + +wire clk_ibufg; + +// Internal 125 MHz clock +wire clk_mmcm_out; +wire clk_int; +wire rst_int; + +wire mmcm_rst = ~reset_n; +wire mmcm_locked; +wire mmcm_clkfb; + +IBUFG +clk_ibufg_inst( + .I(clk), + .O(clk_ibufg) +); + +wire clk_25mhz_mmcm_out; +wire clk_25mhz_int; + +// MMCM instance +MMCME2_BASE #( + // 100 MHz input + .CLKIN1_PERIOD(10.0), + .REF_JITTER1(0.010), + // 100 MHz input / 1 = 100 MHz PFD (range 10 MHz to 550 MHz) + .DIVCLK_DIVIDE(1), + // 100 MHz PFD * 10 = 1000 MHz VCO (range 600 MHz to 1200 MHz) + .CLKFBOUT_MULT_F(10), + .CLKFBOUT_PHASE(0), + // 1250 MHz VCO / 8 = 128 MHz, 0 degrees + .CLKOUT0_DIVIDE_F(8), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + // 1250 MHz VCO / 40 = 25 MHz, 0 degrees + .CLKOUT1_DIVIDE(40), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + // Not used + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + // Not used + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + // Not used + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT4_CASCADE("FALSE"), + // Not used + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + // Not used + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + + // optimized bandwidth + .BANDWIDTH("OPTIMIZED"), + // don't wait for lock during startup + .STARTUP_WAIT("FALSE") +) +clk_mmcm_inst ( + // 100 MHz input + .CLKIN1(clk_ibufg), + // direct clkfb feedback + .CLKFBIN(mmcm_clkfb), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + // 125 MHz, 0 degrees + .CLKOUT0(clk_mmcm_out), + .CLKOUT0B(), + // 25 MHz, 0 degrees + .CLKOUT1(clk_25mhz_mmcm_out), + .CLKOUT1B(), + // Not used + .CLKOUT2(), + .CLKOUT2B(), + // Not used + .CLKOUT3(), + .CLKOUT3B(), + // Not used + .CLKOUT4(), + // Not used + .CLKOUT5(), + // Not used + .CLKOUT6(), + // reset input + .RST(mmcm_rst), + // don't power down + .PWRDWN(1'b0), + // locked output + .LOCKED(mmcm_locked) +); + +BUFG +clk_bufg_inst ( + .I(clk_mmcm_out), + .O(clk_int) +); + +BUFG +clk_25mhz_bufg_inst ( + .I(clk_25mhz_mmcm_out), + .O(clk_25mhz_int) +); + +taxi_sync_reset #( + .N(4) +) +sync_reset_inst ( + .clk(clk_int), + .rst(~mmcm_locked), + .out(rst_int) +); + +// GPIO +wire [3:0] btn_int; +wire [3:0] sw_int; + +taxi_debounce_switch #( + .WIDTH(8), + .N(4), + .RATE(125000) +) +debounce_switch_inst ( + .clk(clk_int), + .rst(rst_int), + .in({btn, + sw}), + .out({btn_int, + sw_int}) +); + +wire uart_rxd_int; + +taxi_sync_signal #( + .WIDTH(1), + .N(2) +) +sync_signal_inst ( + .clk(clk_int), + .in({uart_rxd}), + .out({uart_rxd_int}) +); + +assign phy_ref_clk = clk_25mhz_int; + +fpga_core #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY) +) +core_inst ( + /* + * Clock: 125MHz + * Synchronous reset + */ + .clk(clk_int), + .rst(rst_int), + + /* + * GPIO + */ + .btn(btn_int), + .sw(sw_int), + .led0_r(led0_r), + .led0_g(led0_g), + .led0_b(led0_b), + .led1_r(led1_r), + .led1_g(led1_g), + .led1_b(led1_b), + .led2_r(led2_r), + .led2_g(led2_g), + .led2_b(led2_b), + .led3_r(led3_r), + .led3_g(led3_g), + .led3_b(led3_b), + .led4(led4), + .led5(led5), + .led6(led6), + .led7(led7), + + /* + * UART: 115200 bps, 8N1 + */ + .uart_rxd(uart_rxd_int), + .uart_txd(uart_txd), + + /* + * Ethernet: 100BASE-T MII + */ + .phy_rx_clk(phy_rx_clk), + .phy_rxd(phy_rxd), + .phy_rx_dv(phy_rx_dv), + .phy_rx_er(phy_rx_er), + .phy_tx_clk(phy_tx_clk), + .phy_txd(phy_txd), + .phy_tx_en(phy_tx_en), + .phy_col(phy_col), + .phy_crs(phy_crs), + .phy_reset_n(phy_reset_n) +); + +endmodule + +`resetall diff --git a/example/Arty/fpga/rtl/fpga_core.sv b/example/Arty/fpga/rtl/fpga_core.sv new file mode 100644 index 0000000..faf478a --- /dev/null +++ b/example/Arty/fpga/rtl/fpga_core.sv @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: MIT +/* + +Copyright (c) 2014-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * FPGA core logic + */ +module fpga_core # +( + // simulation (set to avoid vendor primitives) + parameter logic SIM = 1'b0, + // vendor ("GENERIC", "XILINX", "ALTERA") + parameter VENDOR = "XILINX", + // device family + parameter FAMILY = "artix7" +) +( + /* + * Clock: 125MHz + * Synchronous reset + */ + input wire logic clk, + input wire logic rst, + + /* + * GPIO + */ + input wire logic [3:0] btn, + input wire logic [3:0] sw, + output wire logic led0_r, + output wire logic led0_g, + output wire logic led0_b, + output wire logic led1_r, + output wire logic led1_g, + output wire logic led1_b, + output wire logic led2_r, + output wire logic led2_g, + output wire logic led2_b, + output wire logic led3_r, + output wire logic led3_g, + output wire logic led3_b, + output wire logic led4, + output wire logic led5, + output wire logic led6, + output wire logic led7, + + /* + * UART: 115200 bps, 8N1 + */ + input wire logic uart_rxd, + output wire logic uart_txd, + + /* + * Ethernet: 100BASE-T MII + */ + input wire logic phy_rx_clk, + input wire logic [3:0] phy_rxd, + input wire logic phy_rx_dv, + input wire logic phy_rx_er, + input wire logic phy_tx_clk, + output wire logic [3:0] phy_txd, + output wire logic phy_tx_en, + input wire logic phy_col, + input wire logic phy_crs, + output wire logic phy_reset_n +); + +// // Place first payload byte onto LEDs +// reg valid_last = 0; +// reg [7:0] led_reg = 0; + +// always @(posedge clk) begin +// if (rst) begin +// led_reg <= 0; +// end else begin +// if (tx_udp_payload_axis_tvalid) begin +// if (!valid_last) begin +// led_reg <= tx_udp_payload_axis_tdata; +// valid_last <= 1'b1; +// end +// if (tx_udp_payload_axis_tlast) begin +// valid_last <= 1'b0; +// end +// end +// end +// end + +//assign led = sw; +assign {led0_g, led1_g, led2_g, led3_g, led4, led5, led6, led7} = 0; +assign phy_reset_n = !rst; + +taxi_axis_if #(.DATA_W(8)) axis_uart(); + +taxi_uart +uut ( + .clk(clk), + .rst(rst), + + /* + * AXI4-Stream input (sink) + */ + .s_axis_tx(axis_uart), + + /* + * AXI4-Stream output (source) + */ + .m_axis_rx(axis_uart), + + /* + * UART interface + */ + .rxd(uart_rxd), + .txd(uart_txd), + + /* + * Status + */ + .tx_busy(), + .rx_busy(), + .rx_overrun_error(), + .rx_frame_error(), + + /* + * Configuration + */ + .prescale(16'(125000000/115200/8)) +); + +taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth(); +taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl(); + +taxi_eth_mac_mii_fifo #( + .SIM(SIM), + .VENDOR(VENDOR), + .FAMILY(FAMILY), + .PADDING_EN(1), + .MIN_FRAME_LEN(64), + .TX_FIFO_DEPTH(16384), + .TX_FRAME_FIFO(1), + .RX_FIFO_DEPTH(16384), + .RX_FRAME_FIFO(1) +) +eth_mac_inst ( + .rst(rst), + .logic_clk(clk), + .logic_rst(rst), + + /* + * Transmit interface (AXI stream) + */ + .s_axis_tx(axis_eth), + .m_axis_tx_cpl(axis_tx_cpl), + + /* + * Receive interface (AXI stream) + */ + .m_axis_rx(axis_eth), + + /* + * MII interface + */ + .mii_rx_clk(phy_rx_clk), + .mii_rxd(phy_rxd), + .mii_rx_dv(phy_rx_dv), + .mii_rx_er(phy_rx_er), + .mii_tx_clk(phy_tx_clk), + .mii_txd(phy_txd), + .mii_tx_en(phy_tx_en), + .mii_tx_er(), + + /* + * Status + */ + .tx_error_underflow(), + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), + + /* + * Configuration + */ + .cfg_ifg(8'd12), + .cfg_tx_enable(1'b1), + .cfg_rx_enable(1'b1) +); + +endmodule + +`resetall diff --git a/example/Arty/fpga/tb/fpga_core/Makefile b/example/Arty/fpga/tb/fpga_core/Makefile new file mode 100644 index 0000000..b795e35 --- /dev/null +++ b/example/Arty/fpga/tb/fpga_core/Makefile @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: MIT +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = fpga_core +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += ../../rtl/$(DUT).sv +VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_mii_fifo.f +VERILOG_SOURCES += ../../lib/taxi/rtl/lss/taxi_uart.f +VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv +VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv +VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_SIM := "1'b1" +export PARAM_VENDOR := "\"XILINX\"" +export PARAM_FAMILY := "\"artix7\"" + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/example/Arty/fpga/tb/fpga_core/test_fpga_core.py b/example/Arty/fpga/tb/fpga_core/test_fpga_core.py new file mode 100644 index 0000000..b9ecd92 --- /dev/null +++ b/example/Arty/fpga/tb/fpga_core/test_fpga_core.py @@ -0,0 +1,200 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: MIT +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import logging +import os + +import cocotb_test.simulator + +import cocotb +from cocotb.log import SimLog +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Combine + +from cocotbext.eth import GmiiFrame, MiiPhy +from cocotbext.uart import UartSource, UartSink + + +class TB: + def __init__(self, dut, speed=100e6): + self.dut = dut + + self.log = SimLog("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 8, units="ns").start()) + + self.mii_phy = MiiPhy(dut.phy_txd, None, dut.phy_tx_en, dut.phy_tx_clk, + dut.phy_rxd, dut.phy_rx_er, dut.phy_rx_dv, dut.phy_rx_clk, speed=speed) + + self.uart_source = UartSource(dut.uart_rxd, baud=115200, bits=8, stop_bits=1) + self.uart_sink = UartSink(dut.uart_txd, baud=115200, bits=8, stop_bits=1) + + dut.phy_crs.setimmediatevalue(0) + dut.phy_col.setimmediatevalue(0) + + dut.btn.setimmediatevalue(0) + dut.sw.setimmediatevalue(0) + + async def init(self): + + self.dut.rst.setimmediatevalue(0) + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 1 + + for k in range(10): + await RisingEdge(self.dut.clk) + + self.dut.rst.value = 0 + + +async def uart_test(tb, source, sink): + tb.log.info("Test UART") + + tx_data = b"FPGA Ninja" + + tb.log.info("UART TX: %s", tx_data) + + await source.write(tx_data) + + rx_data = bytearray() + + while len(rx_data) < len(tx_data): + rx_data.extend(await sink.read()) + + tb.log.info("UART RX: %s", rx_data) + + tb.log.info("UART test done") + + +async def mac_test(tb, phy): + tb.log.info("Test MAC") + + tb.log.info("Multiple small packets") + + count = 64 + + pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)] + + for p in pkts: + await phy.rx.send(GmiiFrame.from_payload(p)) + + for k in range(count): + rx_frame = await phy.tx.recv() + + tb.log.info("RX frame: %s", rx_frame) + + assert rx_frame.get_payload() == pkts[k] + assert rx_frame.check_fcs() + assert rx_frame.error is None + + tb.log.info("Multiple large packets") + + count = 32 + + pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)] + + for p in pkts: + await phy.rx.send(GmiiFrame.from_payload(p)) + + for k in range(count): + rx_frame = await phy.tx.recv() + + tb.log.info("RX frame: %s", rx_frame) + + assert rx_frame.get_payload() == pkts[k] + assert rx_frame.check_fcs() + assert rx_frame.error is None + + tb.log.info("MAC test done") + + +@cocotb.test() +async def run_test(dut): + + tb = TB(dut) + + await tb.init() + + tb.log.info("Start UART test") + + uart_test_cr = cocotb.start_soon(uart_test(tb, tb.uart_source, tb.uart_sink)) + + tb.log.info("Start MAC loopback test") + + mac_test_cr = cocotb.start_soon(mac_test(tb, tb.mii_phy)) + + await Combine(uart_test_cr, mac_test_cr) + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_fpga_core(request): + dut = "fpga_core" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_mii_fifo.f"), + os.path.join(lib_dir, "taxi", "rtl", "lss", "taxi_uart.f"), + os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), + os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), + os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['SIM'] = "1'b1" + parameters['VENDOR'] = "\"XILINX\"" + parameters['FAMILY'] = "\"artix7\"" + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + )