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example: Add example design for Arty A7
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
290
example/Arty/fpga/rtl/fpga.sv
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290
example/Arty/fpga/rtl/fpga.sv
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// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter VENDOR = "XILINX",
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// device family
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parameter FAMILY = "artix7"
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)
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(
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/*
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* Clock: 100MHz
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* Reset: Push button, active low
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*/
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input wire logic clk,
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input wire logic reset_n,
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/*
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* GPIO
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*/
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input wire logic [3:0] sw,
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input wire logic [3:0] btn,
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output wire logic led0_r,
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output wire logic led0_g,
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output wire logic led0_b,
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output wire logic led1_r,
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output wire logic led1_g,
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output wire logic led1_b,
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output wire logic led2_r,
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output wire logic led2_g,
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output wire logic led2_b,
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output wire logic led3_r,
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output wire logic led3_g,
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output wire logic led3_b,
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output wire logic led4,
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output wire logic led5,
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output wire logic led6,
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output wire logic led7,
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/*
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* UART: 115200 bps, 8N1
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*/
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input wire logic uart_rxd,
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output wire logic uart_txd,
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/*
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* Ethernet: 100BASE-T MII
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*/
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output wire logic phy_ref_clk,
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input wire logic phy_rx_clk,
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input wire logic [3:0] phy_rxd,
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input wire logic phy_rx_dv,
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input wire logic phy_rx_er,
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input wire logic phy_tx_clk,
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output wire logic [3:0] phy_txd,
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output wire logic phy_tx_en,
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input wire logic phy_col,
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input wire logic phy_crs,
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output wire logic phy_reset_n
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);
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// Clock and reset
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wire clk_ibufg;
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// Internal 125 MHz clock
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wire clk_mmcm_out;
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wire clk_int;
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wire rst_int;
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wire mmcm_rst = ~reset_n;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFG
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clk_ibufg_inst(
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.I(clk),
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.O(clk_ibufg)
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);
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wire clk_25mhz_mmcm_out;
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wire clk_25mhz_int;
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// MMCM instance
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MMCME2_BASE #(
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// 100 MHz input
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.CLKIN1_PERIOD(10.0),
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.REF_JITTER1(0.010),
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// 100 MHz input / 1 = 100 MHz PFD (range 10 MHz to 550 MHz)
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.DIVCLK_DIVIDE(1),
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// 100 MHz PFD * 10 = 1000 MHz VCO (range 600 MHz to 1200 MHz)
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.CLKFBOUT_MULT_F(10),
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.CLKFBOUT_PHASE(0),
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// 1250 MHz VCO / 8 = 128 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// 1250 MHz VCO / 40 = 25 MHz, 0 degrees
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.CLKOUT1_DIVIDE(40),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(0),
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// Not used
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.CLKOUT2_DIVIDE(1),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 100 MHz input
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.CLKIN1(clk_ibufg),
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// direct clkfb feedback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_mmcm_out),
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.CLKOUT0B(),
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// 25 MHz, 0 degrees
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.CLKOUT1(clk_25mhz_mmcm_out),
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.CLKOUT1B(),
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// Not used
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.CLKOUT2(),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_bufg_inst (
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.I(clk_mmcm_out),
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.O(clk_int)
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);
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BUFG
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clk_25mhz_bufg_inst (
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.I(clk_25mhz_mmcm_out),
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.O(clk_25mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_inst (
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.clk(clk_int),
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.rst(~mmcm_locked),
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.out(rst_int)
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);
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// GPIO
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wire [3:0] btn_int;
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wire [3:0] sw_int;
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taxi_debounce_switch #(
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.WIDTH(8),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_int),
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.rst(rst_int),
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.in({btn,
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sw}),
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.out({btn_int,
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sw_int})
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);
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wire uart_rxd_int;
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taxi_sync_signal #(
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.WIDTH(1),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_int),
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.in({uart_rxd}),
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.out({uart_rxd_int})
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);
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assign phy_ref_clk = clk_25mhz_int;
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fpga_core #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY)
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)
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core_inst (
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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.clk(clk_int),
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.rst(rst_int),
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/*
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* GPIO
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*/
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.btn(btn_int),
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.sw(sw_int),
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.led0_r(led0_r),
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.led0_g(led0_g),
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.led0_b(led0_b),
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.led1_r(led1_r),
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.led1_g(led1_g),
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.led1_b(led1_b),
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.led2_r(led2_r),
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.led2_g(led2_g),
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.led2_b(led2_b),
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.led3_r(led3_r),
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.led3_g(led3_g),
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.led3_b(led3_b),
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.led4(led4),
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.led5(led5),
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.led6(led6),
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.led7(led7),
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/*
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* UART: 115200 bps, 8N1
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*/
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.uart_rxd(uart_rxd_int),
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.uart_txd(uart_txd),
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/*
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* Ethernet: 100BASE-T MII
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*/
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.phy_rx_clk(phy_rx_clk),
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.phy_rxd(phy_rxd),
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.phy_rx_dv(phy_rx_dv),
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.phy_rx_er(phy_rx_er),
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.phy_tx_clk(phy_tx_clk),
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.phy_txd(phy_txd),
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.phy_tx_en(phy_tx_en),
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.phy_col(phy_col),
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.phy_crs(phy_crs),
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.phy_reset_n(phy_reset_n)
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);
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endmodule
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`resetall
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