From ddf1b37f4e23e612250a2e246ce7489c443ddac6 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 9 Apr 2025 12:17:46 -0700 Subject: [PATCH] example/Arty: Add XFCP to Arty example design for monitoring and control Signed-off-by: Alex Forencich --- example/Arty/fpga/README.md | 4 +- example/Arty/fpga/fpga/Makefile | 4 +- example/Arty/fpga/rtl/fpga_core.sv | 92 ++++++++++++++----- example/Arty/fpga/tb/fpga_core/Makefile | 4 +- .../Arty/fpga/tb/fpga_core/test_fpga_core.py | 29 +----- 5 files changed, 80 insertions(+), 53 deletions(-) diff --git a/example/Arty/fpga/README.md b/example/Arty/fpga/README.md index 8b27c4f..b05e68c 100644 --- a/example/Arty/fpga/README.md +++ b/example/Arty/fpga/README.md @@ -4,10 +4,10 @@ This example design targets the Digilent Arty A7 FPGA board. -The design places a looped-back MAC on the BASE-T port, as well as a looped-back UART on the USB UART. +The design places a looped-back MAC on the BASE-T port, as well as XFCP on the USB UART for monitoring and control. * USB UART - * Looped-back UART + * XFCP * RJ-45 Ethernet port with TI DP83848J PHY * Looped-back MAC via MII diff --git a/example/Arty/fpga/fpga/Makefile b/example/Arty/fpga/fpga/Makefile index 8ee0b52..35bb2f1 100644 --- a/example/Arty/fpga/fpga/Makefile +++ b/example/Arty/fpga/fpga/Makefile @@ -15,7 +15,9 @@ FPGA_ARCH = artix7 SYN_FILES = ../rtl/fpga.sv SYN_FILES += ../rtl/fpga_core.sv SYN_FILES += ../lib/taxi/rtl/eth/taxi_eth_mac_mii_fifo.f -SYN_FILES += ../lib/taxi/rtl/lss/taxi_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +SYN_FILES += ../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_reset.sv SYN_FILES += ../lib/taxi/rtl/sync/taxi_sync_signal.sv SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv diff --git a/example/Arty/fpga/rtl/fpga_core.sv b/example/Arty/fpga/rtl/fpga_core.sv index f9139af..229570e 100644 --- a/example/Arty/fpga/rtl/fpga_core.sv +++ b/example/Arty/fpga/rtl/fpga_core.sv @@ -78,46 +78,86 @@ module fpga_core # assign {led7, led6, led5, led4, led3_g, led2_g, led1_g, led0_g} = {sw, btn}; assign phy_reset_n = !rst; -taxi_axis_if #(.DATA_W(8)) axis_uart(); +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us(); -taxi_uart -uart_inst ( +taxi_xfcp_if_uart #( + .TX_FIFO_DEPTH(512), + .RX_FIFO_DEPTH(512) +) +xfcp_if_uart_inst ( .clk(clk), .rst(rst), - /* - * AXI4-Stream input (sink) - */ - .s_axis_tx(axis_uart), - - /* - * AXI4-Stream output (source) - */ - .m_axis_rx(axis_uart), - /* * UART interface */ - .rxd(uart_rxd), - .txd(uart_txd), + .uart_rxd(uart_rxd), + .uart_txd(uart_txd), /* - * Status + * XFCP downstream interface */ - .tx_busy(), - .rx_busy(), - .rx_overrun_error(), - .rx_frame_error(), + .xfcp_dsp_ds(xfcp_ds), + .xfcp_dsp_us(xfcp_us), /* * Configuration */ - .prescale(16'(125000000/115200)) + .prescale(16'(125000000/3000000)) +); + +taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[1](), xfcp_sw_us[1](); + +taxi_xfcp_switch #( + .XFCP_ID_STR("Arty A7"), + .XFCP_EXT_ID(0), + .XFCP_EXT_ID_STR("Taxi example"), + .PORTS($size(xfcp_sw_us)) +) +xfcp_sw_inst ( + .clk(clk), + .rst(rst), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_ds), + .xfcp_usp_us(xfcp_us), + + /* + * XFCP downstream ports + */ + .xfcp_dsp_ds(xfcp_sw_ds), + .xfcp_dsp_us(xfcp_sw_us) +); + +taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_mac_stat(); + +taxi_xfcp_mod_stats #( + .XFCP_ID_STR("Statistics"), + .XFCP_EXT_ID(0), + .XFCP_EXT_ID_STR(""), + .STAT_COUNT_W(64), + .STAT_PIPELINE(2) +) +xfcp_stats_inst ( + .clk(clk), + .rst(rst), + + /* + * XFCP upstream port + */ + .xfcp_usp_ds(xfcp_sw_ds[0]), + .xfcp_usp_us(xfcp_sw_us[0]), + + /* + * Statistics increment input + */ + .s_axis_stat(axis_mac_stat) ); taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth(); taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl(); -taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_stat(); taxi_eth_mac_mii_fifo #( .SIM(SIM), @@ -125,7 +165,11 @@ taxi_eth_mac_mii_fifo #( .FAMILY(FAMILY), .PADDING_EN(1), .MIN_FRAME_LEN(64), - .STAT_EN(1'b0), + .STAT_EN(1), + .STAT_TX_LEVEL(1), + .STAT_RX_LEVEL(1), + .STAT_ID_BASE(0), + .STAT_UPDATE_PERIOD(1024), .TX_FIFO_DEPTH(16384), .TX_FRAME_FIFO(1), .RX_FIFO_DEPTH(16384), @@ -164,7 +208,7 @@ eth_mac_inst ( */ .stat_clk(clk), .stat_rst(rst), - .m_axis_stat(axis_stat), + .m_axis_stat(axis_mac_stat), /* * Status diff --git a/example/Arty/fpga/tb/fpga_core/Makefile b/example/Arty/fpga/tb/fpga_core/Makefile index b795e35..720b220 100644 --- a/example/Arty/fpga/tb/fpga_core/Makefile +++ b/example/Arty/fpga/tb/fpga_core/Makefile @@ -20,7 +20,9 @@ MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += ../../rtl/$(DUT).sv VERILOG_SOURCES += ../../lib/taxi/rtl/eth/taxi_eth_mac_mii_fifo.f -VERILOG_SOURCES += ../../lib/taxi/rtl/lss/taxi_uart.f +VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_if_uart.f +VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_switch.sv +VERILOG_SOURCES += ../../lib/taxi/rtl/xfcp/taxi_xfcp_mod_stats.f VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_reset.sv VERILOG_SOURCES += ../../lib/taxi/rtl/sync/taxi_sync_signal.sv VERILOG_SOURCES += ../../lib/taxi/rtl/io/taxi_debounce_switch.sv diff --git a/example/Arty/fpga/tb/fpga_core/test_fpga_core.py b/example/Arty/fpga/tb/fpga_core/test_fpga_core.py index b9ecd92..9777723 100644 --- a/example/Arty/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/Arty/fpga/tb/fpga_core/test_fpga_core.py @@ -59,25 +59,6 @@ class TB: self.dut.rst.value = 0 -async def uart_test(tb, source, sink): - tb.log.info("Test UART") - - tx_data = b"FPGA Ninja" - - tb.log.info("UART TX: %s", tx_data) - - await source.write(tx_data) - - rx_data = bytearray() - - while len(rx_data) < len(tx_data): - rx_data.extend(await sink.read()) - - tb.log.info("UART RX: %s", rx_data) - - tb.log.info("UART test done") - - async def mac_test(tb, phy): tb.log.info("Test MAC") @@ -127,15 +108,11 @@ async def run_test(dut): await tb.init() - tb.log.info("Start UART test") - - uart_test_cr = cocotb.start_soon(uart_test(tb, tb.uart_source, tb.uart_sink)) - tb.log.info("Start MAC loopback test") mac_test_cr = cocotb.start_soon(mac_test(tb, tb.mii_phy)) - await Combine(uart_test_cr, mac_test_cr) + await Combine(mac_test_cr) await RisingEdge(dut.clk) await RisingEdge(dut.clk) @@ -169,7 +146,9 @@ def test_fpga_core(request): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), os.path.join(lib_dir, "taxi", "rtl", "eth", "taxi_eth_mac_mii_fifo.f"), - os.path.join(lib_dir, "taxi", "rtl", "lss", "taxi_uart.f"), + os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_if_uart.f"), + os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_switch.sv"), + os.path.join(lib_dir, "taxi", "rtl", "xfcp", "taxi_xfcp_mod_stats.f"), os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_reset.sv"), os.path.join(lib_dir, "taxi", "rtl", "sync", "taxi_sync_signal.sv"), os.path.join(lib_dir, "taxi", "rtl", "io", "taxi_debounce_switch.sv"),