From e35d2b2c0360fe290a85487d5fd88b0cd48d301b Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 4 Feb 2025 17:10:21 -0800 Subject: [PATCH] eth: Add 10G PHY module and testbench Signed-off-by: Alex Forencich --- rtl/eth/taxi_eth_phy_10g.f | 3 + rtl/eth/taxi_eth_phy_10g.sv | 158 +++++++++++ rtl/eth/taxi_eth_phy_10g_rx.f | 3 + rtl/eth/taxi_eth_phy_10g_rx.sv | 153 +++++++++++ rtl/eth/taxi_eth_phy_10g_rx_ber_mon.sv | 105 +++++++ rtl/eth/taxi_eth_phy_10g_rx_frame_sync.sv | 126 +++++++++ rtl/eth/taxi_eth_phy_10g_rx_if.f | 5 + rtl/eth/taxi_eth_phy_10g_rx_if.sv | 247 +++++++++++++++++ rtl/eth/taxi_eth_phy_10g_rx_watchdog.sv | 153 +++++++++++ rtl/eth/taxi_eth_phy_10g_tx.f | 3 + rtl/eth/taxi_eth_phy_10g_tx.sv | 127 +++++++++ rtl/eth/taxi_eth_phy_10g_tx_if.f | 2 + rtl/eth/taxi_eth_phy_10g_tx_if.sv | 154 +++++++++++ tb/eth/taxi_eth_phy_10g/Makefile | 56 ++++ tb/eth/taxi_eth_phy_10g/baser.py | 1 + .../taxi_eth_phy_10g/test_taxi_eth_phy_10g.py | 257 ++++++++++++++++++ 16 files changed, 1553 insertions(+) create mode 100644 rtl/eth/taxi_eth_phy_10g.f create mode 100644 rtl/eth/taxi_eth_phy_10g.sv create mode 100644 rtl/eth/taxi_eth_phy_10g_rx.f create mode 100644 rtl/eth/taxi_eth_phy_10g_rx.sv create mode 100644 rtl/eth/taxi_eth_phy_10g_rx_ber_mon.sv create mode 100644 rtl/eth/taxi_eth_phy_10g_rx_frame_sync.sv create mode 100644 rtl/eth/taxi_eth_phy_10g_rx_if.f create mode 100644 rtl/eth/taxi_eth_phy_10g_rx_if.sv create mode 100644 rtl/eth/taxi_eth_phy_10g_rx_watchdog.sv create mode 100644 rtl/eth/taxi_eth_phy_10g_tx.f create mode 100644 rtl/eth/taxi_eth_phy_10g_tx.sv create mode 100644 rtl/eth/taxi_eth_phy_10g_tx_if.f create mode 100644 rtl/eth/taxi_eth_phy_10g_tx_if.sv create mode 100644 tb/eth/taxi_eth_phy_10g/Makefile create mode 120000 tb/eth/taxi_eth_phy_10g/baser.py create mode 100644 tb/eth/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py diff --git a/rtl/eth/taxi_eth_phy_10g.f b/rtl/eth/taxi_eth_phy_10g.f new file mode 100644 index 0000000..08e1b15 --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g.f @@ -0,0 +1,3 @@ +taxi_eth_phy_10g.sv +taxi_eth_phy_10g_rx.f +taxi_eth_phy_10g_tx.f diff --git a/rtl/eth/taxi_eth_phy_10g.sv b/rtl/eth/taxi_eth_phy_10g.sv new file mode 100644 index 0000000..270094b --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g.sv @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 10G Ethernet PHY + */ +module taxi_eth_phy_10g # +( + parameter DATA_W = 64, + parameter CTRL_W = (DATA_W/8), + parameter HDR_W = 2, + parameter logic BIT_REVERSE = 1'b0, + parameter logic SCRAMBLER_DISABLE = 1'b0, + parameter logic PRBS31_EN = 1'b0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 7, + parameter COUNT_125US = 125000/6.4 +) +( + input wire logic rx_clk, + input wire logic rx_rst, + input wire logic tx_clk, + input wire logic tx_rst, + + /* + * XGMII interface + */ + input wire logic [DATA_W-1:0] xgmii_txd, + input wire logic [CTRL_W-1:0] xgmii_txc, + output wire logic [DATA_W-1:0] xgmii_rxd, + output wire logic [CTRL_W-1:0] xgmii_rxc, + + /* + * SERDES interface + */ + output wire logic [DATA_W-1:0] serdes_tx_data, + output wire logic [HDR_W-1:0] serdes_tx_hdr, + input wire logic [DATA_W-1:0] serdes_rx_data, + input wire logic [HDR_W-1:0] serdes_rx_hdr, + output wire logic serdes_rx_bitslip, + output wire logic serdes_rx_reset_req, + + /* + * Status + */ + output wire logic tx_bad_block, + output wire logic [6:0] rx_error_count, + output wire logic rx_bad_block, + output wire logic rx_sequence_error, + output wire logic rx_block_lock, + output wire logic rx_high_ber, + output wire logic rx_status, + + /* + * Configuration + */ + input wire logic cfg_tx_prbs31_enable = 1'b0, + input wire logic cfg_rx_prbs31_enable = 1'b0 +); + +taxi_eth_phy_10g_rx #( + .DATA_W(DATA_W), + .CTRL_W(CTRL_W), + .HDR_W(HDR_W), + .BIT_REVERSE(BIT_REVERSE), + .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE), + .PRBS31_EN(PRBS31_EN), + .SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) +) +eth_phy_10g_rx_inst ( + .clk(rx_clk), + .rst(rx_rst), + + /* + * XGMII interface + */ + .xgmii_rxd(xgmii_rxd), + .xgmii_rxc(xgmii_rxc), + + /* + * SERDES interface + */ + .serdes_rx_data(serdes_rx_data), + .serdes_rx_hdr(serdes_rx_hdr), + .serdes_rx_bitslip(serdes_rx_bitslip), + .serdes_rx_reset_req(serdes_rx_reset_req), + + /* + * Status + */ + .rx_error_count(rx_error_count), + .rx_bad_block(rx_bad_block), + .rx_sequence_error(rx_sequence_error), + .rx_block_lock(rx_block_lock), + .rx_high_ber(rx_high_ber), + .rx_status(rx_status), + + /* + * Configuration + */ + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) +); + +taxi_eth_phy_10g_tx #( + .DATA_W(DATA_W), + .CTRL_W(CTRL_W), + .HDR_W(HDR_W), + .BIT_REVERSE(BIT_REVERSE), + .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE), + .PRBS31_EN(PRBS31_EN), + .SERDES_PIPELINE(TX_SERDES_PIPELINE) +) +eth_phy_10g_tx_inst ( + .clk(tx_clk), + .rst(tx_rst), + + /* + * XGMII interface + */ + .xgmii_txd(xgmii_txd), + .xgmii_txc(xgmii_txc), + + /* + * SERDES interface + */ + .serdes_tx_data(serdes_tx_data), + .serdes_tx_hdr(serdes_tx_hdr), + + /* + * Status + */ + .tx_bad_block(tx_bad_block), + + /* + * Configuration + */ + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) +); + +endmodule + +`resetall diff --git a/rtl/eth/taxi_eth_phy_10g_rx.f b/rtl/eth/taxi_eth_phy_10g_rx.f new file mode 100644 index 0000000..e097e4a --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g_rx.f @@ -0,0 +1,3 @@ +taxi_eth_phy_10g_rx.sv +taxi_eth_phy_10g_rx_if.f +taxi_xgmii_baser_dec_64.sv diff --git a/rtl/eth/taxi_eth_phy_10g_rx.sv b/rtl/eth/taxi_eth_phy_10g_rx.sv new file mode 100644 index 0000000..ed38a3e --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g_rx.sv @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 10G Ethernet PHY RX + */ +module taxi_eth_phy_10g_rx # +( + parameter DATA_W = 64, + parameter CTRL_W = (DATA_W/8), + parameter HDR_W = 2, + parameter logic BIT_REVERSE = 1'b0, + parameter logic SCRAMBLER_DISABLE = 1'b0, + parameter logic PRBS31_EN = 1'b0, + parameter SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 7, + parameter COUNT_125US = 125000/6.4 +) +( + input wire logic clk, + input wire logic rst, + + /* + * XGMII interface + */ + output wire logic [DATA_W-1:0] xgmii_rxd, + output wire logic [CTRL_W-1:0] xgmii_rxc, + + /* + * SERDES interface + */ + input wire logic [DATA_W-1:0] serdes_rx_data, + input wire logic [HDR_W-1:0] serdes_rx_hdr, + output wire logic serdes_rx_bitslip, + output wire logic serdes_rx_reset_req, + + /* + * Status + */ + output wire logic [6:0] rx_error_count, + output wire logic rx_bad_block, + output wire logic rx_sequence_error, + output wire logic rx_block_lock, + output wire logic rx_high_ber, + output wire logic rx_status, + + /* + * Configuration + */ + input wire logic cfg_rx_prbs31_enable +); + +// check configuration +if (DATA_W != 64) + $fatal(0, "Error: Interface width must be 64"); + +if (CTRL_W * 8 != DATA_W) + $fatal(0, "Error: Interface requires byte (8-bit) granularity"); + +if (HDR_W != 2) + $fatal(0, "Error: HDR_W must be 2"); + +wire [DATA_W-1:0] encoded_rx_data; +wire [HDR_W-1:0] encoded_rx_hdr; + +taxi_eth_phy_10g_rx_if #( + .DATA_W(DATA_W), + .HDR_W(HDR_W), + .BIT_REVERSE(BIT_REVERSE), + .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE), + .PRBS31_EN(PRBS31_EN), + .SERDES_PIPELINE(SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) +) +eth_phy_10g_rx_if_inst ( + .clk(clk), + .rst(rst), + + /* + * 10GBASE-R encoded interface + */ + .encoded_rx_data(encoded_rx_data), + .encoded_rx_hdr(encoded_rx_hdr), + + /* + * SERDES interface + */ + .serdes_rx_data(serdes_rx_data), + .serdes_rx_hdr(serdes_rx_hdr), + .serdes_rx_bitslip(serdes_rx_bitslip), + .serdes_rx_reset_req(serdes_rx_reset_req), + + /* + * Status + */ + .rx_bad_block(rx_bad_block), + .rx_sequence_error(rx_sequence_error), + .rx_error_count(rx_error_count), + .rx_block_lock(rx_block_lock), + .rx_high_ber(rx_high_ber), + .rx_status(rx_status), + + /* + * Configuration + */ + .cfg_rx_prbs31_enable(cfg_rx_prbs31_enable) +); + +taxi_xgmii_baser_dec_64 #( + .DATA_W(DATA_W), + .CTRL_W(CTRL_W), + .HDR_W(HDR_W) +) +xgmii_baser_dec_inst ( + .clk(clk), + .rst(rst), + + /* + * 10GBASE-R encoded input + */ + .encoded_rx_data(encoded_rx_data), + .encoded_rx_hdr(encoded_rx_hdr), + + /* + * XGMII interface + */ + .xgmii_rxd(xgmii_rxd), + .xgmii_rxc(xgmii_rxc), + + /* + * Status + */ + .rx_bad_block(rx_bad_block), + .rx_sequence_error(rx_sequence_error) +); + +endmodule + +`resetall diff --git a/rtl/eth/taxi_eth_phy_10g_rx_ber_mon.sv b/rtl/eth/taxi_eth_phy_10g_rx_ber_mon.sv new file mode 100644 index 0000000..a4f5806 --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g_rx_ber_mon.sv @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 10G Ethernet PHY BER monitor + */ +module taxi_eth_phy_10g_rx_ber_mon # +( + parameter HDR_W = 2, + parameter COUNT_125US = 125000/6.4 +) +( + input wire logic clk, + input wire logic rst, + + /* + * SERDES interface + */ + input wire logic [HDR_W-1:0] serdes_rx_hdr, + + /* + * Status + */ + output wire logic rx_high_ber +); + +// check configuration +if (HDR_W != 2) + $fatal(0, "Error: HDR_W must be 2"); + +localparam COUNT_W = $clog2($rtoi(COUNT_125US)+1); +localparam logic [COUNT_W-1:0] COUNT_125US_INT = COUNT_W'($rtoi(COUNT_125US)); + +localparam [1:0] + SYNC_DATA = 2'b10, + SYNC_CTRL = 2'b01; + +logic [COUNT_W-1:0] time_count_reg = COUNT_125US_INT, time_count_next; +logic [3:0] ber_count_reg = 4'd0, ber_count_next; + +logic rx_high_ber_reg = 1'b0, rx_high_ber_next; + +assign rx_high_ber = rx_high_ber_reg; + +always_comb begin + if (time_count_reg > 0) begin + time_count_next = time_count_reg-1; + end else begin + time_count_next = time_count_reg; + end + ber_count_next = ber_count_reg; + + rx_high_ber_next = rx_high_ber_reg; + + if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin + // valid header + if (ber_count_reg != 4'd15) begin + if (time_count_reg == 0) begin + rx_high_ber_next = 1'b0; + end + end + end else begin + // invalid header + if (ber_count_reg == 4'd15) begin + rx_high_ber_next = 1'b1; + end else begin + ber_count_next = ber_count_reg + 1; + if (time_count_reg == 0) begin + rx_high_ber_next = 1'b0; + end + end + end + if (time_count_reg == 0) begin + // 125 us timer expired + ber_count_next = 4'd0; + time_count_next = COUNT_125US_INT; + end +end + +always_ff @(posedge clk) begin + time_count_reg <= time_count_next; + ber_count_reg <= ber_count_next; + rx_high_ber_reg <= rx_high_ber_next; + + if (rst) begin + time_count_reg <= COUNT_125US_INT; + ber_count_reg <= 4'd0; + rx_high_ber_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/rtl/eth/taxi_eth_phy_10g_rx_frame_sync.sv b/rtl/eth/taxi_eth_phy_10g_rx_frame_sync.sv new file mode 100644 index 0000000..3711b60 --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g_rx_frame_sync.sv @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 10G Ethernet PHY frame sync + */ +module taxi_eth_phy_10g_rx_frame_sync # +( + parameter HDR_W = 2, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 7 +) +( + input wire logic clk, + input wire logic rst, + + /* + * SERDES interface + */ + input wire logic [HDR_W-1:0] serdes_rx_hdr, + output wire logic serdes_rx_bitslip, + + /* + * Status + */ + output wire logic rx_block_lock +); + +localparam BITSLIP_MAX_CYCLES = BITSLIP_HIGH_CYCLES > BITSLIP_LOW_CYCLES ? BITSLIP_HIGH_CYCLES : BITSLIP_LOW_CYCLES; +localparam BITSLIP_COUNT_W = $clog2(BITSLIP_MAX_CYCLES); + +// check configuration +if (HDR_W != 2) + $fatal(0, "Error: HDR_W must be 2"); + +localparam [1:0] + SYNC_DATA = 2'b10, + SYNC_CTRL = 2'b01; + +logic [5:0] sh_count_reg = 6'd0, sh_count_next; +logic [3:0] sh_invalid_count_reg = 4'd0, sh_invalid_count_next; +logic [BITSLIP_COUNT_W-1:0] bitslip_count_reg = '0, bitslip_count_next; + +logic serdes_rx_bitslip_reg = 1'b0, serdes_rx_bitslip_next; + +logic rx_block_lock_reg = 1'b0, rx_block_lock_next; + +assign serdes_rx_bitslip = serdes_rx_bitslip_reg; +assign rx_block_lock = rx_block_lock_reg; + +always_comb begin + sh_count_next = sh_count_reg; + sh_invalid_count_next = sh_invalid_count_reg; + bitslip_count_next = bitslip_count_reg; + + serdes_rx_bitslip_next = serdes_rx_bitslip_reg; + + rx_block_lock_next = rx_block_lock_reg; + + if (bitslip_count_reg != 0) begin + bitslip_count_next = bitslip_count_reg-1; + end else if (serdes_rx_bitslip_reg) begin + serdes_rx_bitslip_next = 1'b0; + bitslip_count_next = BITSLIP_COUNT_W'(BITSLIP_LOW_CYCLES); + end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin + // valid header + sh_count_next = sh_count_reg + 1; + if (&sh_count_reg) begin + // valid count overflow, reset + sh_count_next = '0; + sh_invalid_count_next = '0; + if (sh_invalid_count_reg == 0) begin + rx_block_lock_next = 1'b1; + end + end + end else begin + // invalid header + sh_count_next = sh_count_reg + 1; + sh_invalid_count_next = sh_invalid_count_reg + 1; + if (!rx_block_lock_reg || &sh_invalid_count_reg) begin + // invalid count overflow, lost block lock + sh_count_next = '0; + sh_invalid_count_next = '0; + rx_block_lock_next = 1'b0; + + // slip one bit + serdes_rx_bitslip_next = 1'b1; + bitslip_count_next = BITSLIP_COUNT_W'(BITSLIP_HIGH_CYCLES); + end else if (&sh_count_reg) begin + // valid count overflow, reset + sh_count_next = '0; + sh_invalid_count_next = '0; + end + end +end + +always_ff @(posedge clk) begin + sh_count_reg <= sh_count_next; + sh_invalid_count_reg <= sh_invalid_count_next; + bitslip_count_reg <= bitslip_count_next; + serdes_rx_bitslip_reg <= serdes_rx_bitslip_next; + rx_block_lock_reg <= rx_block_lock_next; + + if (rst) begin + sh_count_reg <= '0; + sh_invalid_count_reg <= '0; + bitslip_count_reg <= '0; + serdes_rx_bitslip_reg <= 1'b0; + rx_block_lock_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/rtl/eth/taxi_eth_phy_10g_rx_if.f b/rtl/eth/taxi_eth_phy_10g_rx_if.f new file mode 100644 index 0000000..a3453b3 --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g_rx_if.f @@ -0,0 +1,5 @@ +taxi_eth_phy_10g_rx_if.sv +taxi_eth_phy_10g_rx_ber_mon.sv +taxi_eth_phy_10g_rx_frame_sync.sv +taxi_eth_phy_10g_rx_watchdog.sv +../lfsr/taxi_lfsr.sv diff --git a/rtl/eth/taxi_eth_phy_10g_rx_if.sv b/rtl/eth/taxi_eth_phy_10g_rx_if.sv new file mode 100644 index 0000000..092f15a --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g_rx_if.sv @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 10G Ethernet PHY RX IF + */ +module taxi_eth_phy_10g_rx_if # +( + parameter DATA_W = 64, + parameter HDR_W = 2, + parameter logic BIT_REVERSE = 1'b0, + parameter logic SCRAMBLER_DISABLE = 1'b0, + parameter logic PRBS31_EN = 1'b0, + parameter SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 7, + parameter COUNT_125US = 125000/6.4 +) +( + input wire logic clk, + input wire logic rst, + + /* + * 10GBASE-R encoded interface + */ + output wire logic [DATA_W-1:0] encoded_rx_data, + output wire logic [HDR_W-1:0] encoded_rx_hdr, + + /* + * SERDES interface + */ + input wire logic [DATA_W-1:0] serdes_rx_data, + input wire logic [HDR_W-1:0] serdes_rx_hdr, + output wire logic serdes_rx_bitslip, + output wire logic serdes_rx_reset_req, + + /* + * Status + */ + input wire logic rx_bad_block, + input wire logic rx_sequence_error, + output wire logic [6:0] rx_error_count, + output wire logic rx_block_lock, + output wire logic rx_high_ber, + output wire logic rx_status, + + /* + * Configuration + */ + input wire logic cfg_rx_prbs31_enable +); + +// check configuration +if (DATA_W != 64) + $fatal(0, "Error: Interface width must be 64"); + +if (HDR_W != 2) + $fatal(0, "Error: HDR_W must be 2"); + +wire [DATA_W-1:0] serdes_rx_data_rev, serdes_rx_data_int; +wire [HDR_W-1:0] serdes_rx_hdr_rev, serdes_rx_hdr_int; + +if (BIT_REVERSE) begin + for (genvar n = 0; n < DATA_W; n = n + 1) begin + assign serdes_rx_data_rev[n] = serdes_rx_data[DATA_W-n-1]; + end + + for (genvar n = 0; n < HDR_W; n = n + 1) begin + assign serdes_rx_hdr_rev[n] = serdes_rx_hdr[HDR_W-n-1]; + end +end else begin + assign serdes_rx_data_rev = serdes_rx_data; + assign serdes_rx_hdr_rev = serdes_rx_hdr; +end + +if (SERDES_PIPELINE > 0) begin + (* srl_style = "register" *) + logic [DATA_W-1:0] serdes_rx_data_pipe_reg[SERDES_PIPELINE-1:0]; + (* srl_style = "register" *) + logic [HDR_W-1:0] serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1:0]; + + for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin + initial begin + serdes_rx_data_pipe_reg[n] = '0; + serdes_rx_hdr_pipe_reg[n] = '0; + end + + always @(posedge clk) begin + serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1]; + serdes_rx_hdr_pipe_reg[n] <= n == 0 ? serdes_rx_hdr_rev : serdes_rx_hdr_pipe_reg[n-1]; + end + end + + assign serdes_rx_data_int = serdes_rx_data_pipe_reg[SERDES_PIPELINE-1]; + assign serdes_rx_hdr_int = serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1]; +end else begin + assign serdes_rx_data_int = serdes_rx_data_rev; + assign serdes_rx_hdr_int = serdes_rx_hdr_rev; +end + +wire [DATA_W-1:0] descrambled_rx_data; + +logic [DATA_W-1:0] encoded_rx_data_reg = '0; +logic [HDR_W-1:0] encoded_rx_hdr_reg = '0; + +logic [57:0] scrambler_state_reg = {58{1'b1}}; +wire [57:0] scrambler_state; + +logic [30:0] prbs31_state_reg = 31'h7fffffff; +wire [30:0] prbs31_state; +wire [DATA_W+HDR_W-1:0] prbs31_data; +logic [DATA_W+HDR_W-1:0] prbs31_data_reg = '0; + +logic [6:0] rx_error_count_reg = '0; +logic [5:0] rx_error_count_1_reg = '0; +logic [5:0] rx_error_count_2_reg = '0; +logic [5:0] rx_error_count_1_temp; +logic [5:0] rx_error_count_2_temp; + +taxi_lfsr #( + .LFSR_W(58), + .LFSR_POLY(58'h8000000001), + .LFSR_GALOIS(0), + .LFSR_FEED_FORWARD(1), + .REVERSE(1), + .DATA_W(DATA_W) +) +descrambler_inst ( + .data_in(serdes_rx_data_int), + .state_in(scrambler_state_reg), + .data_out(descrambled_rx_data), + .state_out(scrambler_state) +); + +taxi_lfsr #( + .LFSR_W(31), + .LFSR_POLY(31'h10000001), + .LFSR_GALOIS(0), + .LFSR_FEED_FORWARD(1), + .REVERSE(1), + .DATA_W(DATA_W+HDR_W) +) +prbs31_check_inst ( + .data_in(~{serdes_rx_data_int, serdes_rx_hdr_int}), + .state_in(prbs31_state_reg), + .data_out(prbs31_data), + .state_out(prbs31_state) +); + +always_comb begin + rx_error_count_1_temp = '0; + rx_error_count_2_temp = '0; + for (integer i = 0; i < DATA_W+HDR_W; i = i + 1) begin + if (i[0]) begin + rx_error_count_1_temp = rx_error_count_1_temp + 6'(prbs31_data_reg[i]); + end else begin + rx_error_count_2_temp = rx_error_count_2_temp + 6'(prbs31_data_reg[i]); + end + end +end + +always_ff @(posedge clk) begin + scrambler_state_reg <= scrambler_state; + + encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data; + encoded_rx_hdr_reg <= serdes_rx_hdr_int; + + if (PRBS31_EN) begin + if (cfg_rx_prbs31_enable) begin + prbs31_state_reg <= prbs31_state; + prbs31_data_reg <= prbs31_data; + end else begin + prbs31_data_reg <= '0; + end + + rx_error_count_1_reg <= rx_error_count_1_temp; + rx_error_count_2_reg <= rx_error_count_2_temp; + rx_error_count_reg <= rx_error_count_1_reg + rx_error_count_2_reg; + end else begin + rx_error_count_reg <= '0; + end +end + +assign encoded_rx_data = encoded_rx_data_reg; +assign encoded_rx_hdr = encoded_rx_hdr_reg; + +assign rx_error_count = rx_error_count_reg; + +wire serdes_rx_bitslip_int; +wire serdes_rx_reset_req_int; +assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_EN && cfg_rx_prbs31_enable); +assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_EN && cfg_rx_prbs31_enable); + +taxi_eth_phy_10g_rx_frame_sync #( + .HDR_W(HDR_W), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES) +) +eth_phy_10g_rx_frame_sync_inst ( + .clk(clk), + .rst(rst), + .serdes_rx_hdr(serdes_rx_hdr_int), + .serdes_rx_bitslip(serdes_rx_bitslip_int), + .rx_block_lock(rx_block_lock) +); + +taxi_eth_phy_10g_rx_ber_mon #( + .HDR_W(HDR_W), + .COUNT_125US(COUNT_125US) +) +eth_phy_10g_rx_ber_mon_inst ( + .clk(clk), + .rst(rst), + .serdes_rx_hdr(serdes_rx_hdr_int), + .rx_high_ber(rx_high_ber) +); + +taxi_eth_phy_10g_rx_watchdog #( + .HDR_W(HDR_W), + .COUNT_125US(COUNT_125US) +) +eth_phy_10g_rx_watchdog_inst ( + .clk(clk), + .rst(rst), + .serdes_rx_hdr(serdes_rx_hdr_int), + .serdes_rx_reset_req(serdes_rx_reset_req_int), + .rx_bad_block(rx_bad_block), + .rx_sequence_error(rx_sequence_error), + .rx_block_lock(rx_block_lock), + .rx_high_ber(rx_high_ber), + .rx_status(rx_status) +); + +endmodule + +`resetall diff --git a/rtl/eth/taxi_eth_phy_10g_rx_watchdog.sv b/rtl/eth/taxi_eth_phy_10g_rx_watchdog.sv new file mode 100644 index 0000000..130389a --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g_rx_watchdog.sv @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 10G Ethernet PHY serdes watchdog + */ +module taxi_eth_phy_10g_rx_watchdog # +( + parameter HDR_W = 2, + parameter COUNT_125US = 125000/6.4 +) +( + input wire logic clk, + input wire logic rst, + + /* + * SERDES interface + */ + input wire logic [HDR_W-1:0] serdes_rx_hdr, + output wire logic serdes_rx_reset_req, + + /* + * Monitor inputs + */ + input wire logic rx_bad_block, + input wire logic rx_sequence_error, + input wire logic rx_block_lock, + input wire logic rx_high_ber, + + /* + * Status + */ + output wire logic rx_status +); + +// check configuration +if (HDR_W != 2) + $fatal(0, "Error: HDR_W must be 2"); + +localparam COUNT_W = $clog2($rtoi(COUNT_125US)+1); +localparam logic [COUNT_W-1:0] COUNT_125US_INT = COUNT_W'($rtoi(COUNT_125US)); + +localparam [1:0] + SYNC_DATA = 2'b10, + SYNC_CTRL = 2'b01; + +logic [COUNT_W-1:0] time_count_reg = '0, time_count_next; +logic [3:0] error_count_reg = '0, error_count_next; +logic [3:0] status_count_reg = '0, status_count_next; + +logic saw_ctrl_sh_reg = 1'b0, saw_ctrl_sh_next; +logic [9:0] block_error_count_reg = '0, block_error_count_next; + +logic serdes_rx_reset_req_reg = 1'b0, serdes_rx_reset_req_next; + +logic rx_status_reg = 1'b0, rx_status_next; + +assign serdes_rx_reset_req = serdes_rx_reset_req_reg; + +assign rx_status = rx_status_reg; + +always_comb begin + error_count_next = error_count_reg; + status_count_next = status_count_reg; + + saw_ctrl_sh_next = saw_ctrl_sh_reg; + block_error_count_next = block_error_count_reg; + + serdes_rx_reset_req_next = 1'b0; + + rx_status_next = rx_status_reg; + + if (rx_block_lock) begin + if (serdes_rx_hdr == SYNC_CTRL) begin + saw_ctrl_sh_next = 1'b1; + end + if ((rx_bad_block || rx_sequence_error) && !(&block_error_count_reg)) begin + block_error_count_next = block_error_count_reg + 1; + end + end else begin + rx_status_next = 1'b0; + status_count_next = '0; + end + + if (time_count_reg != 0) begin + time_count_next = time_count_reg-1; + end else begin + time_count_next = COUNT_125US_INT; + + if (!saw_ctrl_sh_reg || &block_error_count_reg) begin + error_count_next = error_count_reg + 1; + status_count_next = '0; + end else begin + error_count_next = '0; + if (!(&status_count_reg)) begin + status_count_next = status_count_reg + 1; + end + end + + if (&error_count_reg) begin + error_count_next = '0; + serdes_rx_reset_req_next = 1'b1; + end + + if (&status_count_reg) begin + rx_status_next = 1'b1; + end + + saw_ctrl_sh_next = 1'b0; + block_error_count_next = '0; + end +end + +always_ff @(posedge clk) begin + time_count_reg <= time_count_next; + error_count_reg <= error_count_next; + status_count_reg <= status_count_next; + saw_ctrl_sh_reg <= saw_ctrl_sh_next; + block_error_count_reg <= block_error_count_next; + rx_status_reg <= rx_status_next; + + if (rst) begin + time_count_reg <= COUNT_125US_INT; + error_count_reg <= '0; + status_count_reg <= '0; + saw_ctrl_sh_reg <= 1'b0; + block_error_count_reg <= '0; + rx_status_reg <= 1'b0; + end +end + +always_ff @(posedge clk or posedge rst) begin + if (rst) begin + serdes_rx_reset_req_reg <= 1'b0; + end else begin + serdes_rx_reset_req_reg <= serdes_rx_reset_req_next; + end +end + +endmodule + +`resetall diff --git a/rtl/eth/taxi_eth_phy_10g_tx.f b/rtl/eth/taxi_eth_phy_10g_tx.f new file mode 100644 index 0000000..4938f32 --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g_tx.f @@ -0,0 +1,3 @@ +taxi_eth_phy_10g_tx.sv +taxi_eth_phy_10g_tx_if.f +taxi_xgmii_baser_enc_64.sv diff --git a/rtl/eth/taxi_eth_phy_10g_tx.sv b/rtl/eth/taxi_eth_phy_10g_tx.sv new file mode 100644 index 0000000..e076556 --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g_tx.sv @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 10G Ethernet PHY TX + */ +module taxi_eth_phy_10g_tx # +( + parameter DATA_W = 64, + parameter CTRL_W = (DATA_W/8), + parameter HDR_W = 2, + parameter logic BIT_REVERSE = 1'b0, + parameter logic SCRAMBLER_DISABLE = 1'b0, + parameter logic PRBS31_EN = 1'b0, + parameter SERDES_PIPELINE = 0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * XGMII interface + */ + input wire logic [DATA_W-1:0] xgmii_txd, + input wire logic [CTRL_W-1:0] xgmii_txc, + + /* + * SERDES interface + */ + output wire logic [DATA_W-1:0] serdes_tx_data, + output wire logic [HDR_W-1:0] serdes_tx_hdr, + + /* + * Status + */ + output wire logic tx_bad_block, + + /* + * Configuration + */ + input wire logic cfg_tx_prbs31_enable +); + +// check configuration +if (DATA_W != 64) + $fatal(0, "Error: Interface width must be 64"); + +if (CTRL_W * 8 != DATA_W) + $fatal(0, "Error: Interface requires byte (8-bit) granularity"); + +if (HDR_W != 2) + $fatal(0, "Error: HDR_W must be 2"); + +wire [DATA_W-1:0] encoded_tx_data; +wire [HDR_W-1:0] encoded_tx_hdr; + +taxi_xgmii_baser_enc_64 #( + .DATA_W(DATA_W), + .CTRL_W(CTRL_W), + .HDR_W(HDR_W) +) +xgmii_baser_enc_inst ( + .clk(clk), + .rst(rst), + + /* + * XGMII interface + */ + .xgmii_txd(xgmii_txd), + .xgmii_txc(xgmii_txc), + + /* + * 10GBASE-R encoded interface + */ + .encoded_tx_data(encoded_tx_data), + .encoded_tx_hdr(encoded_tx_hdr), + + /* + * Status + */ + .tx_bad_block(tx_bad_block) +); + +taxi_eth_phy_10g_tx_if #( + .DATA_W(DATA_W), + .HDR_W(HDR_W), + .BIT_REVERSE(BIT_REVERSE), + .SCRAMBLER_DISABLE(SCRAMBLER_DISABLE), + .PRBS31_EN(PRBS31_EN), + .SERDES_PIPELINE(SERDES_PIPELINE) +) +eth_phy_10g_tx_if_inst ( + .clk(clk), + .rst(rst), + + /* + * 10GBASE-R encoded interface + */ + .encoded_tx_data(encoded_tx_data), + .encoded_tx_hdr(encoded_tx_hdr), + + /* + * SERDES interface + */ + .serdes_tx_data(serdes_tx_data), + .serdes_tx_hdr(serdes_tx_hdr), + + /* + * Configuration + */ + .cfg_tx_prbs31_enable(cfg_tx_prbs31_enable) +); + +endmodule + +`resetall diff --git a/rtl/eth/taxi_eth_phy_10g_tx_if.f b/rtl/eth/taxi_eth_phy_10g_tx_if.f new file mode 100644 index 0000000..625f016 --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g_tx_if.f @@ -0,0 +1,2 @@ +taxi_eth_phy_10g_tx_if.sv +../lfsr/taxi_lfsr.sv diff --git a/rtl/eth/taxi_eth_phy_10g_tx_if.sv b/rtl/eth/taxi_eth_phy_10g_tx_if.sv new file mode 100644 index 0000000..f149537 --- /dev/null +++ b/rtl/eth/taxi_eth_phy_10g_tx_if.sv @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * 10G Ethernet PHY TX IF + */ +module taxi_eth_phy_10g_tx_if # +( + parameter DATA_W = 64, + parameter HDR_W = 2, + parameter logic BIT_REVERSE = 1'b0, + parameter logic SCRAMBLER_DISABLE = 1'b0, + parameter logic PRBS31_EN = 1'b0, + parameter SERDES_PIPELINE = 0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * 10GBASE-R encoded interface + */ + input wire logic [DATA_W-1:0] encoded_tx_data, + input wire logic [HDR_W-1:0] encoded_tx_hdr, + + /* + * SERDES interface + */ + output wire logic [DATA_W-1:0] serdes_tx_data, + output wire logic [HDR_W-1:0] serdes_tx_hdr, + + /* + * Configuration + */ + input wire logic cfg_tx_prbs31_enable +); + +// check configuration +if (DATA_W != 64) + $fatal(0, "Error: Interface width must be 64"); + +if (HDR_W != 2) + $fatal(0, "Error: HDR_W must be 2"); + +logic [57:0] scrambler_state_reg = '1; +wire [57:0] scrambler_state; +wire [DATA_W-1:0] scrambled_data; + +logic [30:0] prbs31_state_reg = 31'h7fffffff; +wire [30:0] prbs31_state; +wire [DATA_W+HDR_W-1:0] prbs31_data; + +logic [DATA_W-1:0] serdes_tx_data_reg = '0; +logic [HDR_W-1:0] serdes_tx_hdr_reg = '0; + +wire [DATA_W-1:0] serdes_tx_data_int; +wire [HDR_W-1:0] serdes_tx_hdr_int; + +if (BIT_REVERSE) begin + for (genvar n = 0; n < DATA_W; n = n + 1) begin + assign serdes_tx_data_int[n] = serdes_tx_data_reg[DATA_W-n-1]; + end + + for (genvar n = 0; n < HDR_W; n = n + 1) begin + assign serdes_tx_hdr_int[n] = serdes_tx_hdr_reg[HDR_W-n-1]; + end +end else begin + assign serdes_tx_data_int = serdes_tx_data_reg; + assign serdes_tx_hdr_int = serdes_tx_hdr_reg; +end + +if (SERDES_PIPELINE > 0) begin + (* srl_style = "register" *) + reg [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0]; + (* srl_style = "register" *) + reg [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0]; + + for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin + initial begin + serdes_tx_data_pipe_reg[n] = '0; + serdes_tx_hdr_pipe_reg[n] = '0; + end + + always @(posedge clk) begin + serdes_tx_data_pipe_reg[n] <= n == 0 ? serdes_tx_data_int : serdes_tx_data_pipe_reg[n-1]; + serdes_tx_hdr_pipe_reg[n] <= n == 0 ? serdes_tx_hdr_int : serdes_tx_hdr_pipe_reg[n-1]; + end + end + + assign serdes_tx_data = serdes_tx_data_pipe_reg[SERDES_PIPELINE-1]; + assign serdes_tx_hdr = serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1]; +end else begin + assign serdes_tx_data = serdes_tx_data_int; + assign serdes_tx_hdr = serdes_tx_hdr_int; +end + +taxi_lfsr #( + .LFSR_W(58), + .LFSR_POLY(58'h8000000001), + .LFSR_GALOIS(0), + .LFSR_FEED_FORWARD(0), + .REVERSE(1), + .DATA_W(DATA_W) +) +scrambler_inst ( + .data_in(encoded_tx_data), + .state_in(scrambler_state_reg), + .data_out(scrambled_data), + .state_out(scrambler_state) +); + +taxi_lfsr #( + .LFSR_W(31), + .LFSR_POLY(31'h10000001), + .LFSR_GALOIS(0), + .LFSR_FEED_FORWARD(0), + .REVERSE(1), + .DATA_W(DATA_W+HDR_W) +) +prbs31_gen_inst ( + .data_in('0), + .state_in(prbs31_state_reg), + .data_out(prbs31_data), + .state_out(prbs31_state) +); + +always_ff @(posedge clk) begin + scrambler_state_reg <= scrambler_state; + + if (PRBS31_EN && cfg_tx_prbs31_enable) begin + prbs31_state_reg <= prbs31_state; + + serdes_tx_data_reg <= ~prbs31_data[DATA_W+HDR_W-1:HDR_W]; + serdes_tx_hdr_reg <= ~prbs31_data[HDR_W-1:0]; + end else begin + serdes_tx_data_reg <= SCRAMBLER_DISABLE ? encoded_tx_data : scrambled_data; + serdes_tx_hdr_reg <= encoded_tx_hdr; + end +end + +endmodule + +`resetall diff --git a/tb/eth/taxi_eth_phy_10g/Makefile b/tb/eth/taxi_eth_phy_10g/Makefile new file mode 100644 index 0000000..8cd225c --- /dev/null +++ b/tb/eth/taxi_eth_phy_10g/Makefile @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2021-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps +export COCOTB_RESOLVE_X ?= RANDOM + +DUT = taxi_eth_phy_10g +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = $(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += ../../../rtl/eth/$(DUT).f + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_DATA_W := 64 +export PARAM_CTRL_W := $(shell expr $(PARAM_DATA_W) / 8 ) +export PARAM_HDR_W := 2 +export PARAM_BIT_REVERSE := "1'b0" +export PARAM_SCRAMBLER_DISABLE := "1'b0" +export PARAM_PRBS31_EN := "1'b1" +export PARAM_TX_SERDES_PIPELINE := 2 +export PARAM_RX_SERDES_PIPELINE := 2 +export PARAM_BITSLIP_HIGH_CYCLES := 0 +export PARAM_BITSLIP_LOW_CYCLES := 7 +export PARAM_COUNT_125US := 195 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/tb/eth/taxi_eth_phy_10g/baser.py b/tb/eth/taxi_eth_phy_10g/baser.py new file mode 120000 index 0000000..33a2368 --- /dev/null +++ b/tb/eth/taxi_eth_phy_10g/baser.py @@ -0,0 +1 @@ +../baser.py \ No newline at end of file diff --git a/tb/eth/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py b/tb/eth/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py new file mode 100644 index 0000000..83875f9 --- /dev/null +++ b/tb/eth/taxi_eth_phy_10g/test_taxi_eth_phy_10g.py @@ -0,0 +1,257 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2021-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import sys + +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.regression import TestFactory + +from cocotbext.eth import XgmiiSource, XgmiiSink, XgmiiFrame + +try: + from baser import BaseRSerdesSource, BaseRSerdesSink +except ImportError: + # attempt import from current directory + sys.path.insert(0, os.path.join(os.path.dirname(__file__))) + try: + from baser import BaseRSerdesSource, BaseRSerdesSink + finally: + del sys.path[0] + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.tx_clk, 6.4, units="ns").start()) + cocotb.start_soon(Clock(dut.rx_clk, 6.4, units="ns").start()) + + self.xgmii_source = XgmiiSource(dut.xgmii_txd, dut.xgmii_txc, dut.tx_clk, dut.tx_rst) + self.xgmii_sink = XgmiiSink(dut.xgmii_rxd, dut.xgmii_rxc, dut.rx_clk, dut.rx_rst) + + self.serdes_source = BaseRSerdesSource(dut.serdes_rx_data, dut.serdes_rx_hdr, dut.rx_clk, slip=dut.serdes_rx_bitslip) + self.serdes_sink = BaseRSerdesSink(dut.serdes_tx_data, dut.serdes_tx_hdr, dut.tx_clk) + + dut.cfg_tx_prbs31_enable.setimmediatevalue(0) + dut.cfg_rx_prbs31_enable.setimmediatevalue(0) + + async def reset(self): + self.dut.tx_rst.setimmediatevalue(0) + self.dut.rx_rst.setimmediatevalue(0) + await RisingEdge(self.dut.tx_clk) + await RisingEdge(self.dut.tx_clk) + self.dut.tx_rst.value = 1 + self.dut.rx_rst.value = 1 + await RisingEdge(self.dut.tx_clk) + await RisingEdge(self.dut.tx_clk) + self.dut.tx_rst.value = 0 + self.dut.rx_rst.value = 0 + await RisingEdge(self.dut.tx_clk) + await RisingEdge(self.dut.tx_clk) + + +async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12): + + tb = TB(dut) + + tb.xgmii_source.ifg = ifg + tb.serdes_source.ifg = ifg + + await tb.reset() + + tb.log.info("Wait for block lock") + while not int(dut.rx_block_lock.value): + await RisingEdge(dut.rx_clk) + + # clear out sink buffer + tb.xgmii_sink.clear() + + test_frames = [payload_data(x) for x in payload_lengths()] + + for test_data in test_frames: + test_frame = XgmiiFrame.from_payload(test_data) + await tb.serdes_source.send(test_frame) + + for test_data in test_frames: + rx_frame = await tb.xgmii_sink.recv() + + assert rx_frame.get_payload() == test_data + assert rx_frame.check_fcs() + + assert tb.xgmii_sink.empty() + + await RisingEdge(dut.rx_clk) + await RisingEdge(dut.rx_clk) + + +async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12): + + tb = TB(dut) + + tb.xgmii_source.ifg = ifg + tb.serdes_source.ifg = ifg + + await tb.reset() + + test_frames = [payload_data(x) for x in payload_lengths()] + + for test_data in test_frames: + test_frame = XgmiiFrame.from_payload(test_data) + await tb.xgmii_source.send(test_frame) + + for test_data in test_frames: + rx_frame = await tb.serdes_sink.recv() + + assert rx_frame.get_payload() == test_data + assert rx_frame.check_fcs() + + assert tb.serdes_sink.empty() + + await RisingEdge(dut.tx_clk) + await RisingEdge(dut.tx_clk) + + +async def run_test_rx_frame_sync(dut): + + tb = TB(dut) + + await tb.reset() + + tb.log.info("Wait for block lock") + while not int(dut.rx_block_lock.value): + await RisingEdge(dut.rx_clk) + + assert int(dut.rx_block_lock.value) + + tb.log.info("Change offset") + tb.serdes_source.bit_offset = 33 + + for k in range(100): + await RisingEdge(dut.rx_clk) + + tb.log.info("Check for lock lost") + assert not int(dut.rx_block_lock.value) + assert int(dut.rx_high_ber.value) + + for k in range(500): + await RisingEdge(dut.rx_clk) + + tb.log.info("Check for block lock") + assert int(dut.rx_block_lock.value) + + for k in range(300): + await RisingEdge(dut.rx_clk) + + tb.log.info("Check for high BER deassert") + assert not int(dut.rx_high_ber.value) + + await RisingEdge(dut.rx_clk) + await RisingEdge(dut.rx_clk) + + +def size_list(): + return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + +def cycle_en(): + return itertools.cycle([0, 0, 0, 1]) + + +if cocotb.SIM_NAME: + + for test in [run_test_rx, run_test_tx]: + + factory = TestFactory(test) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("ifg", [12]) + factory.generate_tests() + + factory = TestFactory(run_test_rx_frame_sync) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_taxi_eth_phy_10g(request): + dut = "taxi_eth_phy_10g" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = dut + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, "eth", f"{dut}.f"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['DATA_W'] = 64 + parameters['CTRL_W'] = parameters['DATA_W'] // 8 + parameters['HDR_W'] = 2 + parameters['BIT_REVERSE'] = "1'b0" + parameters['SCRAMBLER_DISABLE'] = "1'b0" + parameters['PRBS31_EN'] = "1'b1" + parameters['TX_SERDES_PIPELINE'] = 2 + parameters['RX_SERDES_PIPELINE'] = 2 + parameters['BITSLIP_HIGH_CYCLES'] = 0 + parameters['BITSLIP_LOW_CYCLES'] = 7 + parameters['COUNT_125US'] = int(1250/6.4) + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + extra_env['COCOTB_RESOLVE_X'] = 'RANDOM' + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + )