From e388cb22c6b77aa8920f4a7db2c131510c7a8d3d Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 20 Feb 2025 10:21:49 -0800 Subject: [PATCH] example/KR260: Update readme Signed-off-by: Alex Forencich --- example/KR260/fpga/README.md | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/example/KR260/fpga/README.md b/example/KR260/fpga/README.md index fbed460..0ed8177 100644 --- a/example/KR260/fpga/README.md +++ b/example/KR260/fpga/README.md @@ -4,10 +4,8 @@ This example design targets the Xilinx KR260 FPGA board. -The design places looped-back MACs on the BASE-T ports and SFP+ cage, as well as a looped-back UART on on the USB UART connection. +The design places looped-back MACs on the BASE-T ports and SFP+ cage. -* USB UART - * Looped-back UART * RJ-45 Ethernet ports with TI DP83867CSRGZ PHY * Looped-back MAC via RGMII * SFP+ cage