eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>

tb/eth/taxi_axis_baser_rx_64/Makefile

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+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2021-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = taxi_axis_baser_rx_64
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv
+VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv
+VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_DATA_W := 64
+export PARAM_HDR_W := 2
+export PARAM_PTP_TS_EN := 1
+export PARAM_PTP_TS_FMT_TOD := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

tb/eth/taxi_axis_baser_rx_64/baser.py

@@ -0,0 +1 @@
+../baser.py

tb/eth/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py

@@ -0,0 +1,187 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import sys
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge
+from cocotb.utils import get_time_from_sim_steps
+from cocotb.regression import TestFactory
+
+from cocotbext.eth import XgmiiFrame, PtpClockSimTime
+from cocotbext.axi import AxiStreamBus, AxiStreamSink
+
+try:
+    from baser import BaseRSerdesSource
+except ImportError:
+    # attempt import from current directory
+    sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
+    try:
+        from baser import BaseRSerdesSource
+    finally:
+        del sys.path[0]
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
+
+        self.source = BaseRSerdesSource(dut.encoded_rx_data, dut.encoded_rx_hdr, dut.clk, scramble=False)
+        self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst)
+
+        self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
+
+        dut.cfg_rx_enable.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
+
+    tb = TB(dut)
+
+    tb.source.ifg = ifg
+    tb.dut.cfg_rx_enable.value = 1
+
+    await tb.reset()
+
+    test_frames = [payload_data(x) for x in payload_lengths()]
+    tx_frames = []
+
+    for test_data in test_frames:
+        test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append)
+        await tb.source.send(test_frame)
+
+    for test_data in test_frames:
+        rx_frame = await tb.sink.recv()
+        tx_frame = tx_frames.pop(0)
+
+        frame_error = rx_frame.tuser & 1
+        ptp_ts = rx_frame.tuser >> 1
+        ptp_ts_ns = ptp_ts / 2**16
+
+        tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
+
+        if tx_frame.start_lane == 4:
+            # start in lane 4 reports 1 full cycle delay, so subtract half clock period
+            tx_frame_sfd_ns -= 3.2
+
+        tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
+        tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
+        tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns))
+
+        assert rx_frame.tdata == test_data
+        assert frame_error == 0
+        assert abs(ptp_ts_ns - tx_frame_sfd_ns - 6.4) < 0.01
+
+    assert tb.sink.empty()
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def size_list():
+    return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
+
+
+def incrementing_payload(length):
+    return bytearray(itertools.islice(itertools.cycle(range(256)), length))
+
+
+def cycle_en():
+    return itertools.cycle([0, 0, 0, 1])
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.add_option("payload_lengths", [size_list])
+    factory.add_option("payload_data", [incrementing_payload])
+    factory.add_option("ifg", [12, 0])
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_axis_baser_rx_64(request):
+    dut = "taxi_axis_baser_rx_64"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, "eth", f"{dut}.sv"),
+        os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"),
+        os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['DATA_W'] = 64
+    parameters['HDR_W'] = 2
+    parameters['PTP_TS_EN'] = 1
+    parameters['PTP_TS_FMT_TOD'] = 1
+    parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

tb/eth/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv

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+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream 10GBASE-R frame receiver testbench
+ */
+module test_taxi_axis_baser_rx_64 #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter DATA_W = 64,
+    parameter HDR_W = 2,
+    parameter logic PTP_TS_EN = 1'b0,
+    parameter logic PTP_TS_FMT_TOD = 1'b1,
+    parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
+
+logic clk;
+logic rst;
+
+logic [DATA_W-1:0] encoded_rx_data;
+logic [HDR_W-1:0] encoded_rx_hdr;
+
+taxi_axis_if #(.DATA_W(DATA_W), .USER_W(USER_W)) m_axis_rx();
+
+logic [PTP_TS_W-1:0] ptp_ts;
+
+logic cfg_rx_enable;
+
+logic [1:0] start_packet;
+logic error_bad_frame;
+logic error_bad_fcs;
+logic rx_bad_block;
+logic rx_sequence_error;
+
+taxi_axis_baser_rx_64 #(
+    .DATA_W(DATA_W),
+    .HDR_W(HDR_W),
+    .PTP_TS_EN(PTP_TS_EN),
+    .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
+    .PTP_TS_W(PTP_TS_W)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * 10GBASE-R encoded input
+     */
+    .encoded_rx_data(encoded_rx_data),
+    .encoded_rx_hdr(encoded_rx_hdr),
+
+    /*
+     * AXI4-Stream output (source)
+     */
+    .m_axis_rx(m_axis_rx),
+
+    /*
+     * PTP
+     */
+    .ptp_ts(ptp_ts),
+
+    /*
+     * Configuration
+     */
+    .cfg_rx_enable(cfg_rx_enable),
+
+    /*
+     * Status
+     */
+    .start_packet(start_packet),
+    .error_bad_frame(error_bad_frame),
+    .error_bad_fcs(error_bad_fcs),
+    .rx_bad_block(rx_bad_block),
+    .rx_sequence_error(rx_sequence_error)
+);
+
+endmodule
+
+`resetall