diff --git a/README.md b/README.md index 63298cc..238f1d7 100644 --- a/README.md +++ b/README.md @@ -30,6 +30,7 @@ To facilitate the dual-license model, contributions to the project can only be a * Single-port RAM * AXI lite * SV interface for AXI lite + * AXI lite to AXI adapter * Register slice * Width converter * Single-port RAM diff --git a/src/axi/rtl/taxi_axil_axi_adapter.f b/src/axi/rtl/taxi_axil_axi_adapter.f new file mode 100644 index 0000000..3d8749f --- /dev/null +++ b/src/axi/rtl/taxi_axil_axi_adapter.f @@ -0,0 +1,5 @@ +taxi_axil_axi_adapter.sv +taxi_axil_axi_adapter_rd.sv +taxi_axil_axi_adapter_wr.sv +taxi_axi_if.sv +taxi_axil_if.sv diff --git a/src/axi/rtl/taxi_axil_axi_adapter.sv b/src/axi/rtl/taxi_axil_axi_adapter.sv new file mode 100644 index 0000000..1967da4 --- /dev/null +++ b/src/axi/rtl/taxi_axil_axi_adapter.sv @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 lite to AXI4 adapter + */ +module taxi_axil_axi_adapter +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4 lite slave interface + */ + taxi_axil_if.wr_slv s_axil_wr, + taxi_axil_if.rd_slv s_axil_rd, + + /* + * AXI4 master interface + */ + taxi_axi_if.wr_mst m_axi_wr, + taxi_axi_if.rd_mst m_axi_rd +); + +taxi_axil_axi_adapter_wr +axil_axi_adapter_wr_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4 lite slave interface + */ + .s_axil_wr(s_axil_wr), + + /* + * AXI4 master interface + */ + .m_axi_wr(m_axi_wr) +); + +taxi_axil_axi_adapter_rd +axil_axi_adapter_rd_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4 lite slave interface + */ + .s_axil_rd(s_axil_rd), + + /* + * AXI4 master interface + */ + .m_axi_rd(m_axi_rd) +); + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axil_axi_adapter_rd.sv b/src/axi/rtl/taxi_axil_axi_adapter_rd.sv new file mode 100644 index 0000000..12dbc9e --- /dev/null +++ b/src/axi/rtl/taxi_axil_axi_adapter_rd.sv @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 lite to AXI4 adapter (read) + */ +module taxi_axil_axi_adapter_rd +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4-Lite slave interface + */ + taxi_axil_if.rd_slv s_axil_rd, + + /* + * AXI4 master interface + */ + taxi_axi_if.rd_mst m_axi_rd +); + +// extract parameters +localparam AXIL_DATA_W = s_axil_rd.DATA_W; +localparam ADDR_W = s_axil_rd.ADDR_W; +localparam AXIL_STRB_W = s_axil_rd.STRB_W; +localparam logic ARUSER_EN = s_axil_rd.ARUSER_EN && m_axi_rd.ARUSER_EN; +localparam ARUSER_W = s_axil_rd.ARUSER_W; +localparam logic RUSER_EN = s_axil_rd.RUSER_EN && m_axi_rd.RUSER_EN; +localparam RUSER_W = s_axil_rd.RUSER_W; + +localparam AXI_DATA_W = m_axi_rd.DATA_W; +localparam AXI_STRB_W = m_axi_rd.STRB_W; +localparam AXI_BURST_SIZE = $clog2(AXI_STRB_W); + +localparam AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_W); +localparam AXI_ADDR_BIT_OFFSET = $clog2(AXI_STRB_W); +localparam AXIL_BYTE_LANES = AXIL_STRB_W; +localparam AXI_BYTE_LANES = AXI_STRB_W; +localparam AXIL_BYTE_W = AXIL_DATA_W/AXIL_BYTE_LANES; +localparam AXI_BYTE_W = AXI_DATA_W/AXI_BYTE_LANES; +localparam AXIL_ADDR_MASK = {ADDR_W{1'b1}} << AXIL_ADDR_BIT_OFFSET; +localparam AXI_ADDR_MASK = {ADDR_W{1'b1}} << AXI_ADDR_BIT_OFFSET; + +// check configuration +if (AXIL_BYTE_W * AXIL_STRB_W != AXIL_DATA_W) + $fatal(0, "Error: AXI slave interface data width not evenly divisible (instance %m)"); + +if (AXI_BYTE_W * AXI_STRB_W != AXI_DATA_W) + $fatal(0, "Error: AXI master interface data width not evenly divisible (instance %m)"); + +if (AXIL_BYTE_W != AXI_BYTE_W) + $fatal(0, "Error: byte size mismatch (instance %m)"); + +if (2**$clog2(AXIL_BYTE_LANES) != AXIL_BYTE_LANES) + $fatal(0, "Error: AXI slave interface byte lane count must be even power of two (instance %m)"); + +if (2**$clog2(AXI_BYTE_LANES) != AXI_BYTE_LANES) + $fatal(0, "Error: AXI master interface byte lane count must be even power of two (instance %m)"); + +if (AXI_BYTE_LANES == AXIL_BYTE_LANES) begin : bypass + // same width; bypass + + assign m_axi_rd.arid = '0; + assign m_axi_rd.araddr = s_axil_rd.araddr; + assign m_axi_rd.arlen = '0; + assign m_axi_rd.arsize = 3'(AXI_BURST_SIZE); + assign m_axi_rd.arburst = 2'b01; + assign m_axi_rd.arlock = 1'b0; + assign m_axi_rd.arcache = 4'b0011; + assign m_axi_rd.arprot = s_axil_rd.arprot; + assign m_axi_rd.arqos = '0; + assign m_axi_rd.arregion = '0; + assign m_axi_rd.aruser = ARUSER_EN ? s_axil_rd.aruser : '0; + assign m_axi_rd.arvalid = s_axil_rd.arvalid; + assign s_axil_rd.arready = m_axi_rd.arready; + + assign s_axil_rd.rdata = m_axi_rd.rdata; + assign s_axil_rd.rresp = m_axi_rd.rresp; + assign s_axil_rd.ruser = RUSER_EN ? m_axi_rd.ruser : '0; + assign s_axil_rd.rvalid = m_axi_rd.rvalid; + assign m_axi_rd.rready = s_axil_rd.rready; + +end else if (AXI_BYTE_LANES > AXIL_BYTE_LANES) begin : upsize + // output is wider; upsize + + localparam [0:0] + STATE_IDLE = 1'd0, + STATE_DATA = 1'd1; + + logic [0:0] state_reg = STATE_IDLE, state_next; + + logic s_axil_arready_reg = 1'b0, s_axil_arready_next; + logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = '0, s_axil_rdata_next; + logic [1:0] s_axil_rresp_reg = '0, s_axil_rresp_next; + logic [RUSER_W-1:0] s_axil_ruser_reg = '0, s_axil_ruser_next; + logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next; + + logic [ADDR_W-1:0] m_axi_araddr_reg = '0, m_axi_araddr_next; + logic [2:0] m_axi_arprot_reg = '0, m_axi_arprot_next; + logic [ARUSER_W-1:0] m_axi_aruser_reg = '0, m_axi_aruser_next; + logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next; + logic m_axi_rready_reg = 1'b0, m_axi_rready_next; + + assign s_axil_rd.arready = s_axil_arready_reg; + assign s_axil_rd.rdata = s_axil_rdata_reg; + assign s_axil_rd.rresp = s_axil_rresp_reg; + assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0; + assign s_axil_rd.rvalid = s_axil_rvalid_reg; + + assign m_axi_rd.arid = '0; + assign m_axi_rd.araddr = m_axi_araddr_reg; + assign m_axi_rd.arlen = '0; + assign m_axi_rd.arsize = 3'(AXI_BURST_SIZE); + assign m_axi_rd.arburst = 2'b01; + assign m_axi_rd.arlock = 1'b0; + assign m_axi_rd.arcache = 4'b0011; + assign m_axi_rd.arprot = m_axi_arprot_reg; + assign m_axi_rd.arqos = '0; + assign m_axi_rd.arregion = '0; + assign m_axi_rd.aruser = ARUSER_EN ? m_axi_aruser_reg : '0; + assign m_axi_rd.arvalid = m_axi_arvalid_reg; + assign m_axi_rd.rready = m_axi_rready_reg; + + always_comb begin + state_next = STATE_IDLE; + + s_axil_arready_next = 1'b0; + s_axil_rdata_next = s_axil_rdata_reg; + s_axil_rresp_next = s_axil_rresp_reg; + s_axil_ruser_next = s_axil_ruser_reg; + s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rd.rready; + m_axi_araddr_next = m_axi_araddr_reg; + m_axi_arprot_next = m_axi_arprot_reg; + m_axi_aruser_next = m_axi_aruser_reg; + m_axi_arvalid_next = m_axi_arvalid_reg && !m_axi_rd.arready; + m_axi_rready_next = 1'b0; + + case (state_reg) + STATE_IDLE: begin + s_axil_arready_next = !m_axi_rd.arvalid; + + if (s_axil_rd.arready && s_axil_rd.arvalid) begin + s_axil_arready_next = 1'b0; + m_axi_araddr_next = s_axil_rd.araddr; + m_axi_arprot_next = s_axil_rd.arprot; + m_axi_aruser_next = s_axil_rd.aruser; + m_axi_arvalid_next = 1'b1; + m_axi_rready_next = !m_axi_rd.rvalid; + state_next = STATE_DATA; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + m_axi_rready_next = !s_axil_rd.rvalid; + + if (m_axi_rd.rready && m_axi_rd.rvalid) begin + m_axi_rready_next = 1'b0; + s_axil_rdata_next = m_axi_rd.rdata[m_axi_araddr_reg[AXI_ADDR_BIT_OFFSET - 1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_W +: AXIL_DATA_W]; + s_axil_rresp_next = m_axi_rd.rresp; + s_axil_ruser_next = m_axi_rd.ruser; + s_axil_rvalid_next = 1'b1; + s_axil_arready_next = !m_axi_rd.arvalid; + state_next = STATE_IDLE; + end else begin + state_next = STATE_DATA; + end + end + endcase + end + + always_ff @(posedge clk) begin + state_reg <= state_next; + + s_axil_arready_reg <= s_axil_arready_next; + s_axil_rdata_reg <= s_axil_rdata_next; + s_axil_rresp_reg <= s_axil_rresp_next; + s_axil_ruser_reg <= s_axil_ruser_next; + s_axil_rvalid_reg <= s_axil_rvalid_next; + + m_axi_araddr_reg <= m_axi_araddr_next; + m_axi_arprot_reg <= m_axi_arprot_next; + m_axi_aruser_reg <= m_axi_aruser_next; + m_axi_arvalid_reg <= m_axi_arvalid_next; + m_axi_rready_reg <= m_axi_rready_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_axil_arready_reg <= 1'b0; + s_axil_rvalid_reg <= 1'b0; + + m_axi_arvalid_reg <= 1'b0; + m_axi_rready_reg <= 1'b0; + end + end + +end else begin : downsize + // output is narrower; downsize + + // output bus is wider + localparam DATA_W = AXIL_DATA_W; + localparam STRB_W = AXIL_STRB_W; + // required number of segments in wider bus + localparam SEG_COUNT = AXIL_BYTE_LANES / AXI_BYTE_LANES; + localparam SEG_COUNT_W = $clog2(SEG_COUNT); + // data width and keep width per segment + localparam SEG_DATA_W = DATA_W / SEG_COUNT; + localparam SEG_STRB_W = STRB_W / SEG_COUNT; + + localparam [0:0] + STATE_IDLE = 1'd0, + STATE_DATA = 1'd1; + + logic [0:0] state_reg = STATE_IDLE, state_next; + + logic [SEG_COUNT_W-1:0] current_seg_reg = '0, current_seg_next; + + logic s_axil_arready_reg = 1'b0, s_axil_arready_next; + logic [AXIL_DATA_W-1:0] s_axil_rdata_reg = '0, s_axil_rdata_next; + logic [1:0] s_axil_rresp_reg = '0, s_axil_rresp_next; + logic [RUSER_W-1:0] s_axil_ruser_reg = '0, s_axil_ruser_next; + logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next; + + logic [ADDR_W-1:0] m_axi_araddr_reg = '0, m_axi_araddr_next; + logic [2:0] m_axi_arprot_reg = '0, m_axi_arprot_next; + logic [ARUSER_W-1:0] m_axi_aruser_reg = '0, m_axi_aruser_next; + logic m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next; + logic m_axi_rready_reg = 1'b0, m_axi_rready_next; + + assign s_axil_rd.arready = s_axil_arready_reg; + assign s_axil_rd.rdata = s_axil_rdata_reg; + assign s_axil_rd.rresp = s_axil_rresp_reg; + assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0; + assign s_axil_rd.rvalid = s_axil_rvalid_reg; + + assign m_axi_rd.arid = '0; + assign m_axi_rd.araddr = m_axi_araddr_reg; + assign m_axi_rd.arlen = '0; + assign m_axi_rd.arsize = 3'(AXI_BURST_SIZE); + assign m_axi_rd.arburst = 2'b01; + assign m_axi_rd.arlock = 1'b0; + assign m_axi_rd.arcache = 4'b0011; + assign m_axi_rd.arprot = m_axi_arprot_reg; + assign m_axi_rd.arqos = '0; + assign m_axi_rd.arregion = '0; + assign m_axi_rd.aruser = ARUSER_EN ? m_axi_aruser_reg : '0; + assign m_axi_rd.arvalid = m_axi_arvalid_reg; + assign m_axi_rd.rready = m_axi_rready_reg; + + always_comb begin + state_next = STATE_IDLE; + + current_seg_next = current_seg_reg; + + s_axil_arready_next = 1'b0; + s_axil_rdata_next = s_axil_rdata_reg; + s_axil_rresp_next = s_axil_rresp_reg; + s_axil_ruser_next = s_axil_ruser_reg; + s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rd.rready; + m_axi_araddr_next = m_axi_araddr_reg; + m_axi_arprot_next = m_axi_arprot_reg; + m_axi_aruser_next = m_axi_aruser_reg; + m_axi_arvalid_next = m_axi_arvalid_reg && !m_axi_rd.arready; + m_axi_rready_next = 1'b0; + + case (state_reg) + STATE_IDLE: begin + s_axil_arready_next = !m_axi_rd.arvalid; + + current_seg_next = s_axil_rd.araddr[AXI_ADDR_BIT_OFFSET +: SEG_COUNT_W]; + s_axil_rresp_next = 2'd0; + + if (s_axil_rd.arready && s_axil_rd.arvalid) begin + s_axil_arready_next = 1'b0; + m_axi_araddr_next = s_axil_rd.araddr; + m_axi_arprot_next = s_axil_rd.arprot; + m_axi_aruser_next = s_axil_rd.aruser; + m_axi_arvalid_next = 1'b1; + m_axi_rready_next = !m_axi_rd.rvalid; + state_next = STATE_DATA; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + m_axi_rready_next = !s_axil_rd.rvalid; + + if (m_axi_rd.rready && m_axi_rd.rvalid) begin + m_axi_rready_next = 1'b0; + m_axi_araddr_next = (m_axi_araddr_reg & AXI_ADDR_MASK) + SEG_STRB_W; + s_axil_rdata_next[current_seg_reg*SEG_DATA_W +: SEG_DATA_W] = m_axi_rd.rdata; + s_axil_ruser_next = m_axi_rd.ruser; + current_seg_next = current_seg_reg + 1; + if (m_axi.rresp != 0) begin + s_axil_rresp_next = m_axi_rd.rresp; + end + if (current_seg_reg == SEG_COUNT_W'(SEG_COUNT-1)) begin + s_axil_rvalid_next = 1'b1; + s_axil_arready_next = !m_axi_rd.arvalid; + state_next = STATE_IDLE; + end else begin + m_axi_arvalid_next = 1'b1; + state_next = STATE_DATA; + end + end else begin + state_next = STATE_DATA; + end + end + endcase + end + + always_ff @(posedge clk) begin + state_reg <= state_next; + + current_seg_reg <= current_seg_next; + + s_axil_arready_reg <= s_axil_arready_next; + s_axil_rdata_reg <= s_axil_rdata_next; + s_axil_rresp_reg <= s_axil_rresp_next; + s_axil_ruser_reg <= s_axil_ruser_next; + s_axil_rvalid_reg <= s_axil_rvalid_next; + + m_axi_araddr_reg <= m_axi_araddr_next; + m_axi_arprot_reg <= m_axi_arprot_next; + m_axi_aruser_reg <= m_axi_aruser_next; + m_axi_arvalid_reg <= m_axi_arvalid_next; + m_axi_rready_reg <= m_axi_rready_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_axil_arready_reg <= 1'b0; + s_axil_rvalid_reg <= 1'b0; + + m_axi_arvalid_reg <= 1'b0; + m_axi_rready_reg <= 1'b0; + end + end + +end + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axil_axi_adapter_wr.sv b/src/axi/rtl/taxi_axil_axi_adapter_wr.sv new file mode 100644 index 0000000..2ae7643 --- /dev/null +++ b/src/axi/rtl/taxi_axil_axi_adapter_wr.sv @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 lite to AXI4 adapter (write) + */ +module taxi_axil_axi_adapter_wr +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4-Lite slave interface + */ + taxi_axil_if.wr_slv s_axil_wr, + + /* + * AXI4 master interface + */ + taxi_axi_if.wr_mst m_axi_wr +); + +// extract parameters +localparam AXIL_DATA_W = s_axil_wr.DATA_W; +localparam ADDR_W = s_axil_wr.ADDR_W; +localparam AXIL_STRB_W = s_axil_wr.STRB_W; +localparam logic AWUSER_EN = s_axil_wr.AWUSER_EN && m_axi_wr.AWUSER_EN; +localparam AWUSER_W = s_axil_wr.AWUSER_W; +localparam logic WUSER_EN = s_axil_wr.WUSER_EN && m_axi_wr.WUSER_EN; +localparam WUSER_W = s_axil_wr.WUSER_W; +localparam logic BUSER_EN = s_axil_wr.BUSER_EN && m_axi_wr.BUSER_EN; +localparam BUSER_W = s_axil_wr.BUSER_W; + +localparam AXI_DATA_W = m_axi_wr.DATA_W; +localparam AXI_STRB_W = m_axi_wr.STRB_W; +localparam AXI_BURST_SIZE = $clog2(AXI_STRB_W); + +localparam S_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_W); +localparam M_ADDR_BIT_OFFSET = $clog2(AXI_STRB_W); +localparam S_BYTE_LANES = AXIL_STRB_W; +localparam M_BYTE_LANES = AXI_STRB_W; +localparam S_BYTE_W = AXIL_DATA_W/S_BYTE_LANES; +localparam M_BYTE_W = AXI_DATA_W/M_BYTE_LANES; +localparam S_ADDR_MASK = {ADDR_W{1'b1}} << S_ADDR_BIT_OFFSET; +localparam M_ADDR_MASK = {ADDR_W{1'b1}} << M_ADDR_BIT_OFFSET; + +// check configuration +if (S_BYTE_W * AXIL_STRB_W != AXIL_DATA_W) + $fatal(0, "Error: AXI slave interface data width not evenly divisible (instance %m)"); + +if (M_BYTE_W * AXI_STRB_W != AXI_DATA_W) + $fatal(0, "Error: AXI master interface data width not evenly divisible (instance %m)"); + +if (S_BYTE_W != M_BYTE_W) + $fatal(0, "Error: byte size mismatch (instance %m)"); + +if (2**$clog2(S_BYTE_LANES) != S_BYTE_LANES) + $fatal(0, "Error: AXI slave interface byte lane count must be even power of two (instance %m)"); + +if (2**$clog2(M_BYTE_LANES) != M_BYTE_LANES) + $fatal(0, "Error: AXI master interface byte lane count must be even power of two (instance %m)"); + +if (M_BYTE_LANES == S_BYTE_LANES) begin : bypass + // same width; bypass + + assign m_axi_wr.awid = '0; + assign m_axi_wr.awaddr = s_axil_wr.awaddr; + assign m_axi_wr.awlen = '0; + assign m_axi_wr.awsize = 3'(AXI_BURST_SIZE); + assign m_axi_wr.awburst = 2'b01; + assign m_axi_wr.awlock = 1'b0; + assign m_axi_wr.awcache = 4'b0011; + assign m_axi_wr.awprot = s_axil_wr.awprot; + assign m_axi_wr.awqos = '0; + assign m_axi_wr.awregion = '0; + assign m_axi_wr.awuser = AWUSER_EN ? s_axil_wr.awuser : '0; + assign m_axi_wr.awvalid = s_axil_wr.awvalid; + assign s_axil_wr.awready = m_axi_wr.awready; + + assign m_axi_wr.wdata = s_axil_wr.wdata; + assign m_axi_wr.wstrb = s_axil_wr.wstrb; + assign m_axi_wr.wlast = 1'b1; + assign m_axi_wr.wuser = WUSER_EN ? s_axil_wr.wuser : '0; + assign m_axi_wr.wvalid = s_axil_wr.wvalid; + assign s_axil_wr.wready = m_axi_wr.wready; + + assign s_axil_wr.bresp = m_axi_wr.bresp; + assign s_axil_wr.buser = BUSER_EN ? m_axi_wr.buser : '0; + assign s_axil_wr.bvalid = m_axi_wr.bvalid; + assign m_axi_wr.bready = s_axil_wr.bready; + +end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize + // output is wider; upsize + + localparam [0:0] + STATE_IDLE = 1'd0, + STATE_DATA = 1'd1; + + logic [0:0] state_reg = STATE_IDLE, state_next; + + logic s_axil_awready_reg = 1'b0, s_axil_awready_next; + logic s_axil_wready_reg = 1'b0, s_axil_wready_next; + + logic [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next; + logic [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next; + logic [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next; + logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next; + logic [AXI_DATA_W-1:0] m_axi_wdata_reg = '0, m_axi_wdata_next; + logic [AXI_STRB_W-1:0] m_axi_wstrb_reg = '0, m_axi_wstrb_next; + logic [WUSER_W-1:0] m_axi_wuser_reg = '0, m_axi_wuser_next; + logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next; + + assign s_axil_wr.awready = s_axil_awready_reg; + assign s_axil_wr.wready = s_axil_wready_reg; + + assign m_axi_wr.awid = '0; + assign m_axi_wr.awaddr = m_axi_awaddr_reg; + assign m_axi_wr.awlen = '0; + assign m_axi_wr.awsize = 3'(AXI_BURST_SIZE); + assign m_axi_wr.awburst = 2'b01; + assign m_axi_wr.awlock = 1'b0; + assign m_axi_wr.awcache = 4'b0011; + assign m_axi_wr.awprot = m_axi_awprot_reg; + assign m_axi_wr.awqos = '0; + assign m_axi_wr.awregion = '0; + assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0; + assign m_axi_wr.awvalid = m_axi_awvalid_reg; + assign m_axi_wr.wdata = m_axi_wdata_reg; + assign m_axi_wr.wstrb = m_axi_wstrb_reg; + assign m_axi_wr.wlast = '1; + assign m_axi_wr.wuser = WUSER_EN ? m_axi_wuser_reg : '0; + assign m_axi_wr.wvalid = m_axi_wvalid_reg; + + // B channel passthrough + assign s_axil_wr.bresp = m_axi_wr.bresp; + assign s_axil_wr.buser = BUSER_EN ? m_axi_wr.buser : '0; + assign s_axil_wr.bvalid = m_axi_wr.bvalid; + assign m_axi_wr.bready = s_axil_wr.bready; + + always_comb begin + state_next = STATE_IDLE; + + s_axil_awready_next = 1'b0; + s_axil_wready_next = 1'b0; + m_axi_awaddr_next = m_axi_awaddr_reg; + m_axi_awprot_next = m_axi_awprot_reg; + m_axi_awuser_next = m_axi_awuser_reg; + m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_wr.awready; + m_axi_wdata_next = m_axi_wdata_reg; + m_axi_wstrb_next = m_axi_wstrb_reg; + m_axi_wuser_next = m_axi_wuser_reg; + m_axi_wvalid_next = m_axi_wvalid_reg && !m_axi_wr.wready; + + case (state_reg) + STATE_IDLE: begin + s_axil_awready_next = !m_axi_wr.awvalid; + + if (s_axil_wr.awready && s_axil_wr.awvalid) begin + s_axil_awready_next = 1'b0; + m_axi_awaddr_next = s_axil_wr.awaddr; + m_axi_awprot_next = s_axil_wr.awprot; + m_axi_awuser_next = s_axil_wr.awuser; + m_axi_awvalid_next = 1'b1; + s_axil_wready_next = !m_axi_wr.wvalid; + state_next = STATE_DATA; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + s_axil_wready_next = !m_axi_wr.wvalid; + + if (s_axil_wr.wready && s_axil_wr.wvalid) begin + s_axil_wready_next = 1'b0; + m_axi_wdata_next = {(M_BYTE_LANES/S_BYTE_LANES){s_axil_wr.wdata}}; + m_axi_wstrb_next = '0; + m_axi_wstrb_next[m_axi_awaddr_reg[M_ADDR_BIT_OFFSET - 1:S_ADDR_BIT_OFFSET] * AXIL_STRB_W +: AXIL_STRB_W] = s_axil_wr.wstrb; + m_axi_wuser_next = s_axil_wr.wuser; + m_axi_wvalid_next = 1'b1; + s_axil_awready_next = !m_axi_wr.awvalid; + state_next = STATE_IDLE; + end else begin + state_next = STATE_DATA; + end + end + default: begin + state_next = STATE_IDLE; + end + endcase + end + + always_ff @(posedge clk) begin + state_reg <= state_next; + + s_axil_awready_reg <= s_axil_awready_next; + s_axil_wready_reg <= s_axil_wready_next; + + m_axi_awaddr_reg <= m_axi_awaddr_next; + m_axi_awprot_reg <= m_axi_awprot_next; + m_axi_awuser_reg <= m_axi_awuser_next; + m_axi_awvalid_reg <= m_axi_awvalid_next; + m_axi_wdata_reg <= m_axi_wdata_next; + m_axi_wstrb_reg <= m_axi_wstrb_next; + m_axi_wuser_reg <= m_axi_wuser_next; + m_axi_wvalid_reg <= m_axi_wvalid_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_axil_awready_reg <= 1'b0; + s_axil_wready_reg <= 1'b0; + + m_axi_awvalid_reg <= 1'b0; + m_axi_wvalid_reg <= 1'b0; + end + end + +end else begin : downsize + // output is narrower; downsize + + // output bus is wider + localparam DATA_W = AXIL_DATA_W; + localparam STRB_W = AXIL_STRB_W; + // required number of segments in wider bus + localparam SEG_COUNT = S_BYTE_LANES / M_BYTE_LANES; + localparam SEG_COUNT_W = $clog2(SEG_COUNT); + // data width and keep width per segment + localparam SEG_DATA_W = DATA_W / SEG_COUNT; + localparam SEG_STRB_W = STRB_W / SEG_COUNT; + + localparam [1:0] + STATE_IDLE = 2'd0, + STATE_DATA = 2'd1, + STATE_RESP = 2'd3; + + logic [1:0] state_reg = STATE_IDLE, state_next; + + logic [DATA_W-1:0] data_reg = '0, data_next; + logic [STRB_W-1:0] strb_reg = '0, strb_next; + + logic [SEG_COUNT_W-1:0] current_seg_reg = 0, current_seg_next; + + logic s_axil_awready_reg = 1'b0, s_axil_awready_next; + logic s_axil_wready_reg = 1'b0, s_axil_wready_next; + logic [1:0] s_axil_bresp_reg = '0, s_axil_bresp_next; + logic [BUSER_W-1:0] s_axil_buser_reg = '0, s_axil_buser_next; + logic s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next; + + logic [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next; + logic [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next; + logic [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next; + logic m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next; + logic [AXI_DATA_W-1:0] m_axi_wdata_reg = '0, m_axi_wdata_next; + logic [AXI_STRB_W-1:0] m_axi_wstrb_reg = '0, m_axi_wstrb_next; + logic [WUSER_W-1:0] m_axi_wuser_reg = '0, m_axi_wuser_next; + logic m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next; + logic m_axi_bready_reg = 1'b0, m_axi_bready_next; + + assign s_axil_wr.awready = s_axil_awready_reg; + assign s_axil_wr.wready = s_axil_wready_reg; + assign s_axil_wr.bresp = s_axil_bresp_reg; + assign s_axil_wr.buser = BUSER_EN ? s_axil_buser_reg : '0; + assign s_axil_wr.bvalid = s_axil_bvalid_reg; + + assign m_axi_wr.awid = '0; + assign m_axi_wr.awaddr = m_axi_awaddr_reg; + assign m_axi_wr.awlen = '0; + assign m_axi_wr.awsize = 3'(AXI_BURST_SIZE); + assign m_axi_wr.awburst = 2'b01; + assign m_axi_wr.awlock = 1'b0; + assign m_axi_wr.awcache = 4'b0011; + assign m_axi_wr.awprot = m_axi_awprot_reg; + assign m_axi_wr.awqos = '0; + assign m_axi_wr.awregion = '0; + assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0; + assign m_axi_wr.awvalid = m_axi_awvalid_reg; + assign m_axi_wr.wdata = m_axi_wdata_reg; + assign m_axi_wr.wstrb = m_axi_wstrb_reg; + assign m_axi_wr.wlast = '1; + assign m_axi_wr.wuser = WUSER_EN ? m_axi_wuser_reg : '0; + assign m_axi_wr.wvalid = m_axi_wvalid_reg; + assign m_axi_wr.bready = m_axi_bready_reg; + + always_comb begin + state_next = STATE_IDLE; + + data_next = data_reg; + strb_next = strb_reg; + + current_seg_next = current_seg_reg; + + s_axil_awready_next = 1'b0; + s_axil_wready_next = 1'b0; + s_axil_bresp_next = s_axil_bresp_reg; + s_axil_buser_next = s_axil_buser_reg; + s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_wr.bready; + m_axi_awaddr_next = m_axi_awaddr_reg; + m_axi_awprot_next = m_axi_awprot_reg; + m_axi_awuser_next = m_axi_awuser_reg; + m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_wr.awready; + m_axi_wdata_next = m_axi_wdata_reg; + m_axi_wstrb_next = m_axi_wstrb_reg; + m_axi_wuser_next = m_axi_wuser_reg; + m_axi_wvalid_next = m_axi_wvalid_reg && !m_axi_wr.wready; + m_axi_bready_next = 1'b0; + + // master output is narrower; may need several cycles + case (state_reg) + STATE_IDLE: begin + s_axil_awready_next = !m_axi_wr.awvalid; + + current_seg_next = s_axil_wr.awaddr[M_ADDR_BIT_OFFSET +: SEG_COUNT_W]; + s_axil_bresp_next = 2'd0; + + if (s_axil_wr.awready && s_axil_wr.awvalid) begin + s_axil_awready_next = 1'b0; + m_axi_awaddr_next = s_axil_wr.awaddr; + m_axi_awprot_next = s_axil_wr.awprot; + m_axi_awuser_next = s_axil_wr.awuser; + m_axi_awvalid_next = 1'b1; + s_axil_wready_next = !m_axi_wr.wvalid; + state_next = STATE_DATA; + end else begin + state_next = STATE_IDLE; + end + end + STATE_DATA: begin + s_axil_wready_next = !m_axi_wr.wvalid; + + if (s_axil_wr.wready && s_axil_wr.wvalid) begin + s_axil_wready_next = 1'b0; + data_next = s_axil_wr.wdata; + strb_next = s_axil_wr.wstrb; + m_axi_wdata_next = data_next[current_seg_reg*SEG_DATA_W +: SEG_DATA_W]; + m_axi_wstrb_next = strb_next[current_seg_reg*SEG_STRB_W +: SEG_STRB_W]; + m_axi_wuser_next = s_axil_wr.wuser; + m_axi_wvalid_next = 1'b1; + m_axi_bready_next = !s_axil_wr.bvalid; + current_seg_next = current_seg_reg + 1; + state_next = STATE_RESP; + end else begin + state_next = STATE_DATA; + end + end + STATE_RESP: begin + m_axi_bready_next = !s_axil_wr.bvalid; + + if (m_axi_wr.bready && m_axi_wr.bvalid) begin + m_axi_bready_next = 1'b0; + m_axi_awaddr_next = (m_axi_awaddr_reg & M_ADDR_MASK) + SEG_STRB_W; + m_axi_wdata_next = data_next[current_seg_reg*SEG_DATA_W +: SEG_DATA_W]; + m_axi_wstrb_next = strb_next[current_seg_reg*SEG_STRB_W +: SEG_STRB_W]; + s_axil_buser_next = m_axi_wr.buser; + current_seg_next = current_seg_reg + 1; + if (m_axi.bresp != 0) begin + s_axil_bresp_next = m_axi_wr.bresp; + end + if (current_seg_reg == 0) begin + s_axil_bvalid_next = 1'b1; + s_axil_awready_next = !m_axi_wr.awvalid; + state_next = STATE_IDLE; + end else begin + m_axi_awvalid_next = 1'b1; + m_axi_wvalid_next = 1'b1; + state_next = STATE_RESP; + end + end else begin + state_next = STATE_RESP; + end + end + default: begin + state_next = STATE_IDLE; + end + endcase + end + + always_ff @(posedge clk) begin + state_reg <= state_next; + + data_reg <= data_next; + strb_reg <= strb_next; + + current_seg_reg <= current_seg_next; + + s_axil_awready_reg <= s_axil_awready_next; + s_axil_wready_reg <= s_axil_wready_next; + s_axil_bresp_reg <= s_axil_bresp_next; + s_axil_buser_reg <= s_axil_buser_next; + s_axil_bvalid_reg <= s_axil_bvalid_next; + + m_axi_awaddr_reg <= m_axi_awaddr_next; + m_axi_awprot_reg <= m_axi_awprot_next; + m_axi_awuser_reg <= m_axi_awuser_next; + m_axi_awvalid_reg <= m_axi_awvalid_next; + m_axi_wdata_reg <= m_axi_wdata_next; + m_axi_wstrb_reg <= m_axi_wstrb_next; + m_axi_wuser_reg <= m_axi_wuser_next; + m_axi_wvalid_reg <= m_axi_wvalid_next; + m_axi_bready_reg <= m_axi_bready_next; + + if (rst) begin + state_reg <= STATE_IDLE; + + s_axil_awready_reg <= 1'b0; + s_axil_wready_reg <= 1'b0; + s_axil_bvalid_reg <= 1'b0; + + m_axi_awvalid_reg <= 1'b0; + m_axi_wvalid_reg <= 1'b0; + m_axi_bready_reg <= 1'b0; + end + end + +end + +endmodule + +`resetall diff --git a/src/axi/tb/taxi_axil_axi_adapter/Makefile b/src/axi/tb/taxi_axil_axi_adapter/Makefile new file mode 100644 index 0000000..7e43a03 --- /dev/null +++ b/src/axi/tb/taxi_axil_axi_adapter/Makefile @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = taxi_axil_axi_adapter +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_ADDR_W := 32 +export PARAM_AXIL_DATA_W := 32 +export PARAM_AXIL_STRB_W := $(shell expr $(PARAM_AXIL_DATA_W) / 8 ) +export PARAM_AXI_DATA_W := 32 +export PARAM_AXI_STRB_W := $(shell expr $(PARAM_AXI_DATA_W) / 8 ) +export PARAM_AXI_ID_W := 8 +export PARAM_AWUSER_EN := 0 +export PARAM_AWUSER_W := 1 +export PARAM_WUSER_EN := 0 +export PARAM_WUSER_W := 1 +export PARAM_BUSER_EN := 0 +export PARAM_BUSER_W := 1 +export PARAM_ARUSER_EN := 0 +export PARAM_ARUSER_W := 1 +export PARAM_RUSER_EN := 0 +export PARAM_RUSER_W := 1 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/axi/tb/taxi_axil_axi_adapter/test_taxi_axil_axi_adapter.py b/src/axi/tb/taxi_axil_axi_adapter/test_taxi_axil_axi_adapter.py new file mode 100644 index 0000000..5cf564d --- /dev/null +++ b/src/axi/tb/taxi_axil_axi_adapter/test_taxi_axil_axi_adapter.py @@ -0,0 +1,247 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import random + +import cocotb_test.simulator +import pytest + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiBus, AxiLiteBus, AxiLiteMaster, AxiRam + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) + + self.axil_master = AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil), dut.clk, dut.rst) + self.axi_ram = AxiRam(AxiBus.from_entity(dut.m_axi), dut.clk, dut.rst, size=2**16) + + def set_idle_generator(self, generator=None): + if generator: + self.axil_master.write_if.aw_channel.set_pause_generator(generator()) + self.axil_master.write_if.w_channel.set_pause_generator(generator()) + self.axil_master.read_if.ar_channel.set_pause_generator(generator()) + self.axi_ram.write_if.b_channel.set_pause_generator(generator()) + self.axi_ram.read_if.r_channel.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.axil_master.write_if.b_channel.set_pause_generator(generator()) + self.axil_master.read_if.r_channel.set_pause_generator(generator()) + self.axi_ram.write_if.aw_channel.set_pause_generator(generator()) + self.axi_ram.write_if.w_channel.set_pause_generator(generator()) + self.axi_ram.read_if.ar_channel.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + byte_lanes = tb.axil_master.write_if.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): + tb.log.info("length %d, offset %d", length, offset) + addr = offset+0x1000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.axi_ram.write(addr-128, b'\xaa'*(length+256)) + + await tb.axil_master.write(addr, test_data) + + tb.log.debug("%s", tb.axi_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48)) + + assert tb.axi_ram.read(addr, length) == test_data + assert tb.axi_ram.read(addr-1, 1) == b'\xaa' + assert tb.axi_ram.read(addr+length, 1) == b'\xaa' + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + byte_lanes = tb.axil_master.write_if.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): + tb.log.info("length %d, offset %d", length, offset) + addr = offset+0x1000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.axi_ram.write(addr, test_data) + + data = await tb.axil_master.read(addr, length) + + assert data.data == test_data + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + async def worker(master, offset, aperture, count=16): + for k in range(count): + length = random.randint(1, min(32, aperture)) + addr = offset+random.randint(0, aperture-length) + test_data = bytearray([x % 256 for x in range(length)]) + + await Timer(random.randint(1, 100), 'ns') + + await master.write(addr, test_data) + + await Timer(random.randint(1, 100), 'ns') + + data = await master.read(addr, length) + assert data.data == test_data + + workers = [] + + for k in range(16): + workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16))) + + while workers: + await workers.pop(0).join() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if cocotb.SIM_NAME: + + for test in [run_test_write, run_test_read]: + + factory = TestFactory(test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.generate_tests() + + factory = TestFactory(run_stress_test) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize("axi_data_w", [8, 16, 32]) +@pytest.mark.parametrize("axil_data_w", [8, 16, 32]) +def test_taxi_axil_axi_adapter(request, axil_data_w, axi_data_w): + dut = "taxi_axil_axi_adapter" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.f"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['ADDR_W'] = 32 + parameters['AXIL_DATA_W'] = axil_data_w + parameters['AXIL_STRB_W'] = parameters['AXIL_DATA_W'] // 8 + parameters['AXI_DATA_W'] = axi_data_w + parameters['AXI_STRB_W'] = parameters['AXI_DATA_W'] // 8 + parameters['AXI_ID_W'] = 8 + parameters['AWUSER_EN'] = 0 + parameters['AWUSER_W'] = 1 + parameters['WUSER_EN'] = 0 + parameters['WUSER_W'] = 1 + parameters['BUSER_EN'] = 0 + parameters['BUSER_W'] = 1 + parameters['ARUSER_EN'] = 0 + parameters['ARUSER_W'] = 1 + parameters['RUSER_EN'] = 0 + parameters['RUSER_W'] = 1 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/axi/tb/taxi_axil_axi_adapter/test_taxi_axil_axi_adapter.sv b/src/axi/tb/taxi_axil_axi_adapter/test_taxi_axil_axi_adapter.sv new file mode 100644 index 0000000..b452967 --- /dev/null +++ b/src/axi/tb/taxi_axil_axi_adapter/test_taxi_axil_axi_adapter.sv @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4-Lite to AXI4 adapter testbench + */ +module test_taxi_axil_axi_adapter # +( + /* verilator lint_off WIDTHTRUNC */ + parameter ADDR_W = 32, + parameter AXIL_DATA_W = 32, + parameter AXIL_STRB_W = (S_DATA_W/8), + parameter AXI_DATA_W = 32, + parameter AXI_STRB_W = (M_DATA_W/8), + parameter AXI_ID_W = 8, + parameter logic AWUSER_EN = 1'b0, + parameter AWUSER_W = 1, + parameter logic WUSER_EN = 1'b0, + parameter WUSER_W = 1, + parameter logic BUSER_EN = 1'b0, + parameter BUSER_W = 1, + parameter logic ARUSER_EN = 1'b0, + parameter ARUSER_W = 1, + parameter logic RUSER_EN = 1'b0, + parameter RUSER_W = 1 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +logic clk; +logic rst; + +taxi_axil_if #( + .DATA_W(AXIL_DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(AXIL_STRB_W), + .AWUSER_EN(AWUSER_EN), + .AWUSER_W(AWUSER_W), + .WUSER_EN(WUSER_EN), + .WUSER_W(WUSER_W), + .BUSER_EN(BUSER_EN), + .BUSER_W(BUSER_W), + .ARUSER_EN(ARUSER_EN), + .ARUSER_W(ARUSER_W), + .RUSER_EN(RUSER_EN), + .RUSER_W(RUSER_W) +) s_axil(); + +taxi_axi_if #( + .DATA_W(AXI_DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(AXI_STRB_W), + .ID_W(AXI_ID_W), + .AWUSER_EN(AWUSER_EN), + .AWUSER_W(AWUSER_W), + .WUSER_EN(WUSER_EN), + .WUSER_W(WUSER_W), + .BUSER_EN(BUSER_EN), + .BUSER_W(BUSER_W), + .ARUSER_EN(ARUSER_EN), + .ARUSER_W(ARUSER_W), + .RUSER_EN(RUSER_EN), + .RUSER_W(RUSER_W) +) m_axi(); + +taxi_axil_axi_adapter +uut ( + .clk(clk), + .rst(rst), + + /* + * AXI4 slave interface + */ + .s_axil_wr(s_axil), + .s_axil_rd(s_axil), + + /* + * AXI4 master interface + */ + .m_axi_wr(m_axi), + .m_axi_rd(m_axi) +); + +endmodule + +`resetall