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eth: Add support for synchronous gearbox to PHY, MAC+PHY, and GT wrappers

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-05-30 21:14:54 -07:00
parent f31ba113d2
commit e4762b7a8c
76 changed files with 3853 additions and 1090 deletions
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766
src/eth/rtl/taxi_axis_baser_rx_64.sv
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@@ -19,6 +19,7 @@ module taxi_axis_baser_rx_64 #
(
parameter DATA_W = 64,
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter logic PTP_TS_EN = 1'b0,
parameter logic PTP_TS_FMT_TOD = 1'b1,
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64
@@ -31,7 +32,9 @@ module taxi_axis_baser_rx_64 #
* 10GBASE-R encoded input
*/
input wire logic [DATA_W-1:0] encoded_rx_data,
input wire logic encoded_rx_data_valid,
input wire logic [HDR_W-1:0] encoded_rx_hdr,
input wire logic encoded_rx_hdr_valid,
/*
* Receive interface (AXI stream)
@@ -344,122 +347,145 @@ always_comb begin
stat_rx_err_bad_fcs_next = 1'b0;
stat_rx_err_preamble_next = 1'b0;
// counter to measure frame length
if (&frame_len_reg[15:3] == 0) begin
if (input_type_d0[3]) begin
frame_len_next = frame_len_reg + 16'(input_type_d0[2:0]);
if (GBX_IF_EN && !encoded_rx_data_valid) begin
// data from gearbox not valid - hold state
state_next = state_reg;
end else begin
// counter to measure frame length
if (&frame_len_reg[15:3] == 0) begin
if (input_type_d0[3]) begin
frame_len_next = frame_len_reg + 16'(input_type_d0[2:0]);
end else begin
frame_len_next = frame_len_reg + 16'(KEEP_W);
end
end else begin
frame_len_next = frame_len_reg + 16'(KEEP_W);
frame_len_next = '1;
end
end else begin
frame_len_next = '1;
end
// counter for max frame length enforcement
if (frame_len_lim_reg[15:3] != 0) begin
frame_len_lim_next = frame_len_lim_reg - 16'(KEEP_W);
end else begin
frame_len_lim_next = '0;
end
// address and ethertype checks
if (&hdr_ptr_reg == 0) begin
hdr_ptr_next = hdr_ptr_reg + 1;
end
case (hdr_ptr_reg)
2'd0: begin
is_mcast_next = input_data_d1[0];
is_bcast_next = &input_data_d1[47:0];
// counter for max frame length enforcement
if (frame_len_lim_reg[15:3] != 0) begin
frame_len_lim_next = frame_len_lim_reg - 16'(KEEP_W);
end else begin
frame_len_lim_next = '0;
end
2'd1: is_8021q_next = {input_data_d1[39:32], input_data_d1[47:40]} == 16'h8100;
default: begin
// do nothing
// address and ethertype checks
if (&hdr_ptr_reg == 0) begin
hdr_ptr_next = hdr_ptr_reg + 1;
end
endcase
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1'b1;
frame_len_next = 16'(KEEP_W);
frame_len_lim_next = cfg_rx_max_pkt_len;
hdr_ptr_next = 0;
pre_ok_next = input_data_d1[63:8] == 56'hD5555555555555;
if (input_start_d1 && cfg_rx_enable) begin
// start condition
reset_crc = 1'b0;
stat_rx_byte_next = 4'(KEEP_W);
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_IDLE;
case (hdr_ptr_reg)
2'd0: begin
is_mcast_next = input_data_d1[0];
is_bcast_next = &input_data_d1[47:0];
end
end
STATE_PAYLOAD: begin
// read payload
m_axis_rx_tdata_next = input_data_d1;
m_axis_rx_tkeep_next = 8'hff;
m_axis_rx_tvalid_next = 1'b1;
m_axis_rx_tlast_next = 1'b0;
m_axis_rx_tuser_next = 1'b0;
if (input_type_d0[3]) begin
stat_rx_byte_next = 4'(input_type_d0[2:0]);
frame_oversize_next = frame_len_lim_reg < 16'(8+input_type_d0[2:0]);
end else begin
stat_rx_byte_next = 4'(KEEP_W);
frame_oversize_next = frame_len_lim_reg < 8;
2'd1: is_8021q_next = {input_data_d1[39:32], input_data_d1[47:40]} == 16'h8100;
default: begin
// do nothing
end
endcase
if (input_type_d0[3]) begin
// INPUT_TYPE_TERM_*
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1'b1;
end
if (PTP_TS_EN) begin
ptp_ts_out_next = (!PTP_TS_FMT_TOD || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg;
end
frame_len_next = 16'(KEEP_W);
frame_len_lim_next = cfg_rx_max_pkt_len;
hdr_ptr_next = 0;
if (input_type_d0 == INPUT_TYPE_DATA) begin
state_next = STATE_PAYLOAD;
end else if (input_type_d0[3]) begin
// INPUT_TYPE_TERM_*
if (input_type_d0 <= INPUT_TYPE_TERM_4) begin
// end this cycle
case (input_type_d0)
INPUT_TYPE_TERM_0: m_axis_rx_tkeep_next = 8'b00001111;
INPUT_TYPE_TERM_1: m_axis_rx_tkeep_next = 8'b00011111;
INPUT_TYPE_TERM_2: m_axis_rx_tkeep_next = 8'b00111111;
INPUT_TYPE_TERM_3: m_axis_rx_tkeep_next = 8'b01111111;
INPUT_TYPE_TERM_4: m_axis_rx_tkeep_next = 8'b11111111;
default: m_axis_rx_tkeep_next = 8'b11111111;
endcase
m_axis_rx_tlast_next = 1'b1;
if ((input_type_d0 == INPUT_TYPE_TERM_0 && crc_valid_save[7]) ||
(input_type_d0 == INPUT_TYPE_TERM_1 && crc_valid[0]) ||
(input_type_d0 == INPUT_TYPE_TERM_2 && crc_valid[1]) ||
(input_type_d0 == INPUT_TYPE_TERM_3 && crc_valid[2]) ||
(input_type_d0 == INPUT_TYPE_TERM_4 && crc_valid[3])) begin
// CRC valid
if (frame_oversize_next) begin
// too long
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_bad_next = 1'b1;
pre_ok_next = input_data_d1[63:8] == 56'hD5555555555555;
if (input_start_d1 && cfg_rx_enable) begin
// start condition
reset_crc = 1'b0;
stat_rx_byte_next = 4'(KEEP_W);
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// read payload
m_axis_rx_tdata_next = input_data_d1;
m_axis_rx_tkeep_next = 8'hff;
m_axis_rx_tvalid_next = 1'b1;
m_axis_rx_tlast_next = 1'b0;
m_axis_rx_tuser_next = 1'b0;
if (input_type_d0[3]) begin
stat_rx_byte_next = 4'(input_type_d0[2:0]);
frame_oversize_next = frame_len_lim_reg < 16'(8+input_type_d0[2:0]);
end else begin
stat_rx_byte_next = 4'(KEEP_W);
frame_oversize_next = frame_len_lim_reg < 8;
end
if (input_type_d0[3]) begin
// INPUT_TYPE_TERM_*
reset_crc = 1'b1;
end
if (PTP_TS_EN) begin
ptp_ts_out_next = (!PTP_TS_FMT_TOD || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg;
end
if (input_type_d0 == INPUT_TYPE_DATA) begin
state_next = STATE_PAYLOAD;
end else if (input_type_d0[3]) begin
// INPUT_TYPE_TERM_*
if (input_type_d0 <= INPUT_TYPE_TERM_4) begin
// end this cycle
case (input_type_d0)
INPUT_TYPE_TERM_0: m_axis_rx_tkeep_next = 8'b00001111;
INPUT_TYPE_TERM_1: m_axis_rx_tkeep_next = 8'b00011111;
INPUT_TYPE_TERM_2: m_axis_rx_tkeep_next = 8'b00111111;
INPUT_TYPE_TERM_3: m_axis_rx_tkeep_next = 8'b01111111;
INPUT_TYPE_TERM_4: m_axis_rx_tkeep_next = 8'b11111111;
default: m_axis_rx_tkeep_next = 8'b11111111;
endcase
m_axis_rx_tlast_next = 1'b1;
if ((input_type_d0 == INPUT_TYPE_TERM_0 && crc_valid_save[7]) ||
(input_type_d0 == INPUT_TYPE_TERM_1 && crc_valid[0]) ||
(input_type_d0 == INPUT_TYPE_TERM_2 && crc_valid[1]) ||
(input_type_d0 == INPUT_TYPE_TERM_3 && crc_valid[2]) ||
(input_type_d0 == INPUT_TYPE_TERM_4 && crc_valid[3])) begin
// CRC valid
if (frame_oversize_next) begin
// too long
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_bad_next = 1'b1;
end else begin
// length OK
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_good_next = 1'b1;
end
end else begin
// length OK
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_good_next = 1'b1;
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_next;
stat_rx_pkt_bad_next = 1'b1;
stat_rx_err_bad_fcs_next = 1'b1;
end
stat_rx_pkt_len_next = frame_len_next;
stat_rx_pkt_ucast_next = !is_mcast_reg;
stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_rx_pkt_bcast_next = is_bcast_reg;
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg;
state_next = STATE_IDLE;
end else begin
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_next;
stat_rx_pkt_bad_next = 1'b1;
stat_rx_err_bad_fcs_next = 1'b1;
// need extra cycle
state_next = STATE_LAST;
end
end else begin
// control or error characters in packet
m_axis_rx_tlast_next = 1'b1;
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_bad_next = 1'b1;
stat_rx_pkt_len_next = frame_len_next;
stat_rx_pkt_ucast_next = !is_mcast_reg;
@@ -468,85 +494,67 @@ always_comb begin
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_preamble_next = !pre_ok_reg;
stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_next;
reset_crc = 1'b1;
state_next = STATE_IDLE;
end else begin
// need extra cycle
state_next = STATE_LAST;
end
end else begin
// control or error characters in packet
end
STATE_LAST: begin
// last cycle of packet
m_axis_rx_tdata_next = input_data_d1;
m_axis_rx_tkeep_next = 8'hff;
m_axis_rx_tvalid_next = 1'b1;
m_axis_rx_tlast_next = 1'b1;
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_bad_next = 1'b1;
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_len_next = frame_len_next;
reset_crc = 1'b1;
case (input_type_d1)
INPUT_TYPE_TERM_5: m_axis_rx_tkeep_next = 8'b00000001;
INPUT_TYPE_TERM_6: m_axis_rx_tkeep_next = 8'b00000011;
INPUT_TYPE_TERM_7: m_axis_rx_tkeep_next = 8'b00000111;
default: m_axis_rx_tkeep_next = 8'b00000111;
endcase
if ((input_type_d1 == INPUT_TYPE_TERM_5 && crc_valid_save[4]) ||
(input_type_d1 == INPUT_TYPE_TERM_6 && crc_valid_save[5]) ||
(input_type_d1 == INPUT_TYPE_TERM_7 && crc_valid_save[6])) begin
// CRC valid
if (frame_oversize_reg) begin
// too long
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_bad_next = 1'b1;
end else begin
// length OK
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_good_next = 1'b1;
end
end else begin
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_fragment_next = frame_len_reg[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_reg;
stat_rx_pkt_bad_next = 1'b1;
stat_rx_err_bad_fcs_next = 1'b1;
end
stat_rx_pkt_len_next = frame_len_reg;
stat_rx_pkt_ucast_next = !is_mcast_reg;
stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_rx_pkt_bcast_next = is_bcast_reg;
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_next;
stat_rx_err_oversize_next = frame_oversize_reg;
stat_rx_err_preamble_next = !pre_ok_reg;
stat_rx_pkt_fragment_next = frame_len_next[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_next;
reset_crc = 1'b1;
state_next = STATE_IDLE;
end
end
STATE_LAST: begin
// last cycle of packet
m_axis_rx_tdata_next = input_data_d1;
m_axis_rx_tkeep_next = 8'hff;
m_axis_rx_tvalid_next = 1'b1;
m_axis_rx_tlast_next = 1'b1;
m_axis_rx_tuser_next = 1'b0;
reset_crc = 1'b1;
case (input_type_d1)
INPUT_TYPE_TERM_5: m_axis_rx_tkeep_next = 8'b00000001;
INPUT_TYPE_TERM_6: m_axis_rx_tkeep_next = 8'b00000011;
INPUT_TYPE_TERM_7: m_axis_rx_tkeep_next = 8'b00000111;
default: m_axis_rx_tkeep_next = 8'b00000111;
endcase
if ((input_type_d1 == INPUT_TYPE_TERM_5 && crc_valid_save[4]) ||
(input_type_d1 == INPUT_TYPE_TERM_6 && crc_valid_save[5]) ||
(input_type_d1 == INPUT_TYPE_TERM_7 && crc_valid_save[6])) begin
// CRC valid
if (frame_oversize_reg) begin
// too long
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_bad_next = 1'b1;
end else begin
// length OK
m_axis_rx_tuser_next = 1'b0;
stat_rx_pkt_good_next = 1'b1;
end
end else begin
m_axis_rx_tuser_next = 1'b1;
stat_rx_pkt_fragment_next = frame_len_reg[15:6] == 0;
stat_rx_pkt_jabber_next = frame_oversize_reg;
stat_rx_pkt_bad_next = 1'b1;
stat_rx_err_bad_fcs_next = 1'b1;
default: begin
// invalid state, return to idle
state_next = STATE_IDLE;
end
stat_rx_pkt_len_next = frame_len_reg;
stat_rx_pkt_ucast_next = !is_mcast_reg;
stat_rx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_rx_pkt_bcast_next = is_bcast_reg;
stat_rx_pkt_vlan_next = is_8021q_reg;
stat_rx_err_oversize_next = frame_oversize_reg;
stat_rx_err_preamble_next = !pre_ok_reg;
state_next = STATE_IDLE;
end
default: begin
// invalid state, return to idle
state_next = STATE_IDLE;
end
endcase
endcase
end
end
always_ff @(posedge clk) begin
@@ -587,245 +595,247 @@ always_ff @(posedge clk) begin
stat_rx_err_framing_reg <= 1'b0;
stat_rx_err_preamble_reg <= stat_rx_err_preamble_next;
delay_type_valid <= 1'b0;
if (!GBX_IF_EN || encoded_rx_data_valid) begin
delay_type_valid <= 1'b0;
swap_data <= encoded_rx_data_masked[63:32];
swap_data <= encoded_rx_data_masked[63:32];
input_start_swap <= 1'b0;
input_start_d0 <= input_start_swap;
input_start_swap <= 1'b0;
input_start_d0 <= input_start_swap;
if (PTP_TS_EN && PTP_TS_FMT_TOD) begin
// ns field rollover
ptp_ts_adj_reg[15:0] <= ptp_ts_reg[15:0];
{ptp_ts_borrow_reg, ptp_ts_adj_reg[45:16]} <= $signed({1'b0, ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
ptp_ts_adj_reg[47:46] <= 0;
ptp_ts_adj_reg[95:48] <= ptp_ts_reg[95:48] + 1;
end
if (PTP_TS_EN && PTP_TS_FMT_TOD) begin
// ns field rollover
ptp_ts_adj_reg[15:0] <= ptp_ts_reg[15:0];
{ptp_ts_borrow_reg, ptp_ts_adj_reg[45:16]} <= $signed({1'b0, ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
ptp_ts_adj_reg[47:46] <= 0;
ptp_ts_adj_reg[95:48] <= ptp_ts_reg[95:48] + 1;
end
// lane swapping and termination character detection
if (lanes_swapped) begin
if (delay_type_valid) begin
input_type_d0 <= delay_type;
end else if (encoded_rx_hdr[0] == SYNC_DATA[0]) begin
input_type_d0 <= INPUT_TYPE_DATA;
// lane swapping and termination character detection
if (lanes_swapped) begin
if (delay_type_valid) begin
input_type_d0 <= delay_type;
end else if (encoded_rx_hdr[0] == SYNC_DATA[0]) begin
input_type_d0 <= INPUT_TYPE_DATA;
end else begin
case (encoded_rx_data[7:4])
BLOCK_TYPE_TERM_0[7:4]: input_type_d0 <= INPUT_TYPE_TERM_4;
BLOCK_TYPE_TERM_1[7:4]: input_type_d0 <= INPUT_TYPE_TERM_5;
BLOCK_TYPE_TERM_2[7:4]: input_type_d0 <= INPUT_TYPE_TERM_6;
BLOCK_TYPE_TERM_3[7:4]: input_type_d0 <= INPUT_TYPE_TERM_7;
BLOCK_TYPE_TERM_4[7:4]: begin
delay_type_valid <= 1'b1;
input_type_d0 <= INPUT_TYPE_DATA;
end
BLOCK_TYPE_TERM_5[7:4]: begin
delay_type_valid <= 1'b1;
input_type_d0 <= INPUT_TYPE_DATA;
end
BLOCK_TYPE_TERM_6[7:4]: begin
delay_type_valid <= 1'b1;
input_type_d0 <= INPUT_TYPE_DATA;
end
BLOCK_TYPE_TERM_7[7:4]: begin
delay_type_valid <= 1'b1;
input_type_d0 <= INPUT_TYPE_DATA;
end
BLOCK_TYPE_CTRL[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_OS_4[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_OS_04[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_OS_0[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
default: begin
input_type_d0 <= INPUT_TYPE_ERROR;
end
endcase
end
if (delay_type_valid) begin
// mask off trailing data
input_data_d0 <= {32'd0, swap_data};
end else begin
input_data_d0 <= {encoded_rx_data_masked[31:0], swap_data};
end
end else begin
if (encoded_rx_hdr[0] == SYNC_DATA[0]) begin
input_type_d0 <= INPUT_TYPE_DATA;
end else begin
case (encoded_rx_data[7:4])
BLOCK_TYPE_CTRL[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_OS_4[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_OS_04[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_OS_0[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_TERM_0[7:4]: input_type_d0 <= INPUT_TYPE_TERM_0;
BLOCK_TYPE_TERM_1[7:4]: input_type_d0 <= INPUT_TYPE_TERM_1;
BLOCK_TYPE_TERM_2[7:4]: input_type_d0 <= INPUT_TYPE_TERM_2;
BLOCK_TYPE_TERM_3[7:4]: input_type_d0 <= INPUT_TYPE_TERM_3;
BLOCK_TYPE_TERM_4[7:4]: input_type_d0 <= INPUT_TYPE_TERM_4;
BLOCK_TYPE_TERM_5[7:4]: input_type_d0 <= INPUT_TYPE_TERM_5;
BLOCK_TYPE_TERM_6[7:4]: input_type_d0 <= INPUT_TYPE_TERM_6;
BLOCK_TYPE_TERM_7[7:4]: input_type_d0 <= INPUT_TYPE_TERM_7;
default: begin
input_type_d0 <= INPUT_TYPE_ERROR;
end
endcase
end
input_data_d0 <= encoded_rx_data_masked;
end
// start control character detection
if (encoded_rx_hdr == SYNC_CTRL && encoded_rx_data[7:0] == BLOCK_TYPE_START_0) begin
lanes_swapped <= 1'b0;
input_start_d0 <= 1'b1;
input_data_d0 <= encoded_rx_data_masked;
end else if (encoded_rx_hdr == SYNC_CTRL && (encoded_rx_data[7:0] == BLOCK_TYPE_START_4 || encoded_rx_data[7:0] == BLOCK_TYPE_OS_START)) begin
lanes_swapped <= 1'b1;
input_start_swap <= 1'b1;
end
if (encoded_rx_hdr == SYNC_DATA) begin
delay_type <= INPUT_TYPE_DATA;
end else if (encoded_rx_hdr == SYNC_CTRL) begin
case (encoded_rx_data[7:4])
BLOCK_TYPE_TERM_0[7:4]: input_type_d0 <= INPUT_TYPE_TERM_4;
BLOCK_TYPE_TERM_1[7:4]: input_type_d0 <= INPUT_TYPE_TERM_5;
BLOCK_TYPE_TERM_2[7:4]: input_type_d0 <= INPUT_TYPE_TERM_6;
BLOCK_TYPE_TERM_3[7:4]: input_type_d0 <= INPUT_TYPE_TERM_7;
BLOCK_TYPE_START_4[7:4]: delay_type <= INPUT_TYPE_START_0;
BLOCK_TYPE_OS_START[7:4]: delay_type <= INPUT_TYPE_START_0;
BLOCK_TYPE_TERM_0[7:4]: delay_type <= INPUT_TYPE_TERM_4;
BLOCK_TYPE_TERM_1[7:4]: delay_type <= INPUT_TYPE_TERM_5;
BLOCK_TYPE_TERM_2[7:4]: delay_type <= INPUT_TYPE_TERM_6;
BLOCK_TYPE_TERM_3[7:4]: delay_type <= INPUT_TYPE_TERM_7;
BLOCK_TYPE_TERM_4[7:4]: delay_type <= INPUT_TYPE_TERM_0;
BLOCK_TYPE_TERM_5[7:4]: delay_type <= INPUT_TYPE_TERM_1;
BLOCK_TYPE_TERM_6[7:4]: delay_type <= INPUT_TYPE_TERM_2;
BLOCK_TYPE_TERM_7[7:4]: delay_type <= INPUT_TYPE_TERM_3;
default: delay_type <= INPUT_TYPE_ERROR;
endcase
end else begin
delay_type <= INPUT_TYPE_ERROR;
end
// check for framing errors
stat_rx_err_framing_reg <= 1'b0;
if (encoded_rx_hdr == SYNC_DATA) begin
// data - must be in a frame
stat_rx_err_framing_reg <= !frame_reg;
end else if (encoded_rx_hdr == SYNC_CTRL) begin
// control - control only allowed between frames
frame_reg <= 1'b0;
case (encoded_rx_data[7:4])
BLOCK_TYPE_CTRL[7:4]: begin
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_OS_4[7:4]: begin
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_START_4[7:4]: begin
frame_reg <= 1'b1;
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_OS_START[7:4]: begin
frame_reg <= 1'b1;
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_OS_04[7:4]: begin
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_START_0[7:4]: begin
frame_reg <= 1'b1;
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_OS_0[7:4]: begin
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_TERM_0[7:4]: begin
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_1[7:4]: begin
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_2[7:4]: begin
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_3[7:4]: begin
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_4[7:4]: begin
delay_type_valid <= 1'b1;
input_type_d0 <= INPUT_TYPE_DATA;
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_5[7:4]: begin
delay_type_valid <= 1'b1;
input_type_d0 <= INPUT_TYPE_DATA;
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_6[7:4]: begin
delay_type_valid <= 1'b1;
input_type_d0 <= INPUT_TYPE_DATA;
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_7[7:4]: begin
delay_type_valid <= 1'b1;
input_type_d0 <= INPUT_TYPE_DATA;
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_CTRL[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_OS_4[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_OS_04[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_OS_0[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
default: begin
input_type_d0 <= INPUT_TYPE_ERROR;
// invalid block type
frame_reg <= 1'b0;
end
endcase
end
if (delay_type_valid) begin
// mask off trailing data
input_data_d0 <= {32'd0, swap_data};
end else begin
input_data_d0 <= {encoded_rx_data_masked[31:0], swap_data};
// invalid header
frame_reg <= 1'b0;
end
end else begin
if (encoded_rx_hdr[0] == SYNC_DATA[0]) begin
input_type_d0 <= INPUT_TYPE_DATA;
end else begin
case (encoded_rx_data[7:4])
BLOCK_TYPE_CTRL[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_OS_4[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_OS_04[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_OS_0[7:4]: input_type_d0 <= INPUT_TYPE_IDLE;
BLOCK_TYPE_TERM_0[7:4]: input_type_d0 <= INPUT_TYPE_TERM_0;
BLOCK_TYPE_TERM_1[7:4]: input_type_d0 <= INPUT_TYPE_TERM_1;
BLOCK_TYPE_TERM_2[7:4]: input_type_d0 <= INPUT_TYPE_TERM_2;
BLOCK_TYPE_TERM_3[7:4]: input_type_d0 <= INPUT_TYPE_TERM_3;
BLOCK_TYPE_TERM_4[7:4]: input_type_d0 <= INPUT_TYPE_TERM_4;
BLOCK_TYPE_TERM_5[7:4]: input_type_d0 <= INPUT_TYPE_TERM_5;
BLOCK_TYPE_TERM_6[7:4]: input_type_d0 <= INPUT_TYPE_TERM_6;
BLOCK_TYPE_TERM_7[7:4]: input_type_d0 <= INPUT_TYPE_TERM_7;
// check all block type bits to detect bad encodings
if (encoded_rx_hdr == SYNC_DATA) begin
// data - nothing encoded
end else if (encoded_rx_hdr == SYNC_CTRL) begin
// control - check for bad block types
case (encoded_rx_data[7:0])
BLOCK_TYPE_CTRL: begin end
BLOCK_TYPE_OS_4: begin end
BLOCK_TYPE_START_4: begin end
BLOCK_TYPE_OS_START: begin end
BLOCK_TYPE_OS_04: begin end
BLOCK_TYPE_START_0: begin end
BLOCK_TYPE_OS_0: begin end
BLOCK_TYPE_TERM_0: begin end
BLOCK_TYPE_TERM_1: begin end
BLOCK_TYPE_TERM_2: begin end
BLOCK_TYPE_TERM_3: begin end
BLOCK_TYPE_TERM_4: begin end
BLOCK_TYPE_TERM_5: begin end
BLOCK_TYPE_TERM_6: begin end
BLOCK_TYPE_TERM_7: begin end
default: begin
input_type_d0 <= INPUT_TYPE_ERROR;
// invalid block type
stat_rx_err_bad_block_reg <= 1'b1;
end
endcase
end
input_data_d0 <= encoded_rx_data_masked;
end
// start control character detection
if (encoded_rx_hdr == SYNC_CTRL && encoded_rx_data[7:0] == BLOCK_TYPE_START_0) begin
lanes_swapped <= 1'b0;
input_start_d0 <= 1'b1;
input_data_d0 <= encoded_rx_data_masked;
end else if (encoded_rx_hdr == SYNC_CTRL && (encoded_rx_data[7:0] == BLOCK_TYPE_START_4 || encoded_rx_data[7:0] == BLOCK_TYPE_OS_START)) begin
lanes_swapped <= 1'b1;
input_start_swap <= 1'b1;
end
if (encoded_rx_hdr == SYNC_DATA) begin
delay_type <= INPUT_TYPE_DATA;
end else if (encoded_rx_hdr == SYNC_CTRL) begin
case (encoded_rx_data[7:4])
BLOCK_TYPE_START_4[7:4]: delay_type <= INPUT_TYPE_START_0;
BLOCK_TYPE_OS_START[7:4]: delay_type <= INPUT_TYPE_START_0;
BLOCK_TYPE_TERM_0[7:4]: delay_type <= INPUT_TYPE_TERM_4;
BLOCK_TYPE_TERM_1[7:4]: delay_type <= INPUT_TYPE_TERM_5;
BLOCK_TYPE_TERM_2[7:4]: delay_type <= INPUT_TYPE_TERM_6;
BLOCK_TYPE_TERM_3[7:4]: delay_type <= INPUT_TYPE_TERM_7;
BLOCK_TYPE_TERM_4[7:4]: delay_type <= INPUT_TYPE_TERM_0;
BLOCK_TYPE_TERM_5[7:4]: delay_type <= INPUT_TYPE_TERM_1;
BLOCK_TYPE_TERM_6[7:4]: delay_type <= INPUT_TYPE_TERM_2;
BLOCK_TYPE_TERM_7[7:4]: delay_type <= INPUT_TYPE_TERM_3;
default: delay_type <= INPUT_TYPE_ERROR;
endcase
end else begin
delay_type <= INPUT_TYPE_ERROR;
end
// check for framing errors
stat_rx_err_framing_reg <= 1'b0;
if (encoded_rx_hdr == SYNC_DATA) begin
// data - must be in a frame
stat_rx_err_framing_reg <= !frame_reg;
end else if (encoded_rx_hdr == SYNC_CTRL) begin
// control - control only allowed between frames
frame_reg <= 1'b0;
case (encoded_rx_data[7:4])
BLOCK_TYPE_CTRL[7:4]: begin
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_OS_4[7:4]: begin
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_START_4[7:4]: begin
frame_reg <= 1'b1;
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_OS_START[7:4]: begin
frame_reg <= 1'b1;
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_OS_04[7:4]: begin
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_START_0[7:4]: begin
frame_reg <= 1'b1;
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_OS_0[7:4]: begin
stat_rx_err_framing_reg <= frame_reg;
end
BLOCK_TYPE_TERM_0[7:4]: begin
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_1[7:4]: begin
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_2[7:4]: begin
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_3[7:4]: begin
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_4[7:4]: begin
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_5[7:4]: begin
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_6[7:4]: begin
stat_rx_err_framing_reg <= !frame_reg;
end
BLOCK_TYPE_TERM_7[7:4]: begin
stat_rx_err_framing_reg <= !frame_reg;
end
default: begin
// invalid block type
frame_reg <= 1'b0;
end
endcase
end else begin
// invalid header
frame_reg <= 1'b0;
end
// check all block type bits to detect bad encodings
if (encoded_rx_hdr == SYNC_DATA) begin
// data - nothing encoded
end else if (encoded_rx_hdr == SYNC_CTRL) begin
// control - check for bad block types
case (encoded_rx_data[7:0])
BLOCK_TYPE_CTRL: begin end
BLOCK_TYPE_OS_4: begin end
BLOCK_TYPE_START_4: begin end
BLOCK_TYPE_OS_START: begin end
BLOCK_TYPE_OS_04: begin end
BLOCK_TYPE_START_0: begin end
BLOCK_TYPE_OS_0: begin end
BLOCK_TYPE_TERM_0: begin end
BLOCK_TYPE_TERM_1: begin end
BLOCK_TYPE_TERM_2: begin end
BLOCK_TYPE_TERM_3: begin end
BLOCK_TYPE_TERM_4: begin end
BLOCK_TYPE_TERM_5: begin end
BLOCK_TYPE_TERM_6: begin end
BLOCK_TYPE_TERM_7: begin end
default: begin
// invalid block type
stat_rx_err_bad_block_reg <= 1'b1;
end
endcase
end else begin
// invalid header
stat_rx_err_bad_block_reg <= 1'b1;
end
// capture timestamps
if (input_start_swap) begin
start_packet_reg <= 2'b10;
if (PTP_TS_FMT_TOD) begin
ptp_ts_reg[45:0] <= ptp_ts[45:0] + 46'(ts_inc_reg >> 1);
ptp_ts_reg[95:48] <= ptp_ts[95:48];
end else begin
ptp_ts_reg <= ptp_ts + PTP_TS_W'(ts_inc_reg >> 1);
// invalid header
stat_rx_err_bad_block_reg <= 1'b1;
end
// capture timestamps
if (input_start_swap) begin
start_packet_reg <= 2'b10;
if (PTP_TS_FMT_TOD) begin
ptp_ts_reg[45:0] <= ptp_ts[45:0] + 46'(ts_inc_reg >> 1);
ptp_ts_reg[95:48] <= ptp_ts[95:48];
end else begin
ptp_ts_reg <= ptp_ts + PTP_TS_W'(ts_inc_reg >> 1);
end
end
if (input_start_d0 && !lanes_swapped) begin
start_packet_reg <= 2'b01;
ptp_ts_reg <= ptp_ts;
end
input_type_d1 <= input_type_d0;
input_start_d1 <= input_start_d0;
input_data_d1 <= input_data_d0;
if (reset_crc) begin
crc_state <= '1;
end else begin
crc_state <= crc_next;
end
crc_valid_save <= crc_valid;
end
if (input_start_d0 && !lanes_swapped) begin
start_packet_reg <= 2'b01;
ptp_ts_reg <= ptp_ts;
end
input_type_d1 <= input_type_d0;
input_start_d1 <= input_start_d0;
input_data_d1 <= input_data_d0;
if (reset_crc) begin
crc_state <= '1;
end else begin
crc_state <= crc_next;
end
crc_valid_save <= crc_valid;
last_ts_reg <= (4+16)'(ptp_ts);
ts_inc_reg <= (4+16)'(ptp_ts) - last_ts_reg;

740
src/eth/rtl/taxi_axis_baser_tx_64.sv
View File

@@ -19,6 +19,8 @@ module taxi_axis_baser_tx_64 #
(
parameter DATA_W = 64,
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter GBX_CNT = 1,
parameter logic PADDING_EN = 1'b1,
parameter logic DIC_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
@@ -41,7 +43,12 @@ module taxi_axis_baser_tx_64 #
* 10GBASE-R encoded interface
*/
output wire logic [DATA_W-1:0] encoded_tx_data,
output wire logic encoded_tx_data_valid,
output wire logic [HDR_W-1:0] encoded_tx_hdr,
output wire logic encoded_tx_hdr_valid,
input wire logic [GBX_CNT-1:0] tx_gbx_req_start = '0,
input wire logic tx_gbx_req_stall = '0,
output wire logic [GBX_CNT-1:0] tx_gbx_start,
/*
* PTP
@@ -213,7 +220,10 @@ logic [31:0] crc_state_reg[7:0];
wire [31:0] crc_state_next[7:0];
logic [DATA_W-1:0] encoded_tx_data_reg = {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
logic encoded_tx_data_valid_reg = 1'b0;
logic [HDR_W-1:0] encoded_tx_hdr_reg = SYNC_CTRL;
logic encoded_tx_hdr_valid_reg = 1'b0;
logic [GBX_CNT-1:0] tx_gbx_start_reg = '0;
logic [DATA_W-1:0] output_data_reg = '0, output_data_next;
logic [3:0] output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;
@@ -235,10 +245,13 @@ logic stat_tx_err_underflow_reg = 1'b0, stat_tx_err_underflow_next;
logic [4+16-1:0] last_ts_reg = '0;
logic [4+16-1:0] ts_inc_reg = '0;
assign s_axis_tx.tready = s_axis_tx_tready_reg;
assign s_axis_tx.tready = s_axis_tx_tready_reg && (!GBX_IF_EN || !tx_gbx_req_stall);
assign encoded_tx_data = encoded_tx_data_reg;
assign encoded_tx_data_valid = GBX_IF_EN ? encoded_tx_data_valid_reg : 1'b1;
assign encoded_tx_hdr = encoded_tx_hdr_reg;
assign encoded_tx_hdr_valid = GBX_IF_EN ? encoded_tx_hdr_valid_reg : 1'b1;
assign tx_gbx_start = GBX_IF_EN ? tx_gbx_start_reg : '0;
assign m_axis_tx_cpl.tdata = PTP_TS_EN ? ((!PTP_TS_FMT_TOD || m_axis_tx_cpl_ts_borrow_reg) ? m_axis_tx_cpl_ts_reg : m_axis_tx_cpl_ts_adj_reg) : '0;
assign m_axis_tx_cpl.tkeep = 1'b1;
@@ -413,113 +426,126 @@ always_comb begin
frame_next = !s_axis_tx.tlast;
end
// counter for min frame length enforcement
if (frame_min_count_reg > MIN_LEN_W'(KEEP_W)) begin
frame_min_count_next = MIN_LEN_W'(frame_min_count_reg - KEEP_W);
if (GBX_IF_EN && tx_gbx_req_stall) begin
// gearbox stall - hold state
state_next = state_reg;
frame_start_next = frame_start_reg;
s_axis_tx_tready_next = s_axis_tx_tready_reg;
end else begin
frame_min_count_next = 0;
end
// counter to measure frame length
if (&frame_len_reg[15:3] == 0) begin
frame_len_next = frame_len_reg + 16'(KEEP_W);
end else begin
frame_len_next = '1;
end
// counter for max frame length enforcement
if (frame_len_lim_reg[15:3] != 0) begin
frame_len_lim_next = frame_len_lim_reg - 16'(KEEP_W);
end else begin
frame_len_lim_next = '0;
end
// address and ethertype checks
if (&hdr_ptr_reg == 0) begin
hdr_ptr_next = hdr_ptr_reg + 1;
end
case (hdr_ptr_reg)
2'd0: begin
is_mcast_next = s_tdata_reg[0];
is_bcast_next = &s_tdata_reg[47:0];
// counter for min frame length enforcement
if (frame_min_count_reg > MIN_LEN_W'(KEEP_W)) begin
frame_min_count_next = MIN_LEN_W'(frame_min_count_reg - KEEP_W);
end else begin
frame_min_count_next = 0;
end
2'd1: is_8021q_next = {s_tdata_reg[39:32], s_tdata_reg[47:40]} == 16'h8100;
default: begin
// do nothing
// counter to measure frame length
if (&frame_len_reg[15:3] == 0) begin
frame_len_next = frame_len_reg + 16'(KEEP_W);
end else begin
frame_len_next = '1;
end
endcase
if (ifg_cnt_reg[7:3] != 0) begin
ifg_cnt_next = ifg_cnt_reg - 8'(KEEP_W);
end else begin
ifg_cnt_next = '0;
end
// counter for max frame length enforcement
if (frame_len_lim_reg[15:3] != 0) begin
frame_len_lim_next = frame_len_lim_reg - 16'(KEEP_W);
end else begin
frame_len_lim_next = '0;
end
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_error_next = 1'b0;
frame_min_count_next = MIN_LEN_W'(MIN_FRAME_LEN-4-KEEP_W);
hdr_ptr_next = 0;
frame_len_next = 0;
frame_len_lim_next = cfg_tx_max_pkt_len;
reset_crc = 1'b1;
s_axis_tx_tready_next = 1'b1;
// address and ethertype checks
if (&hdr_ptr_reg == 0) begin
hdr_ptr_next = hdr_ptr_reg + 1;
end
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
case (hdr_ptr_reg)
2'd0: begin
is_mcast_next = s_tdata_reg[0];
is_bcast_next = &s_tdata_reg[47:0];
end
2'd1: is_8021q_next = {s_tdata_reg[39:32], s_tdata_reg[47:40]} == 16'h8100;
default: begin
// do nothing
end
endcase
s_tdata_next = s_axis_tx_tdata_masked;
s_empty_next = keep2empty(s_axis_tx.tkeep);
if (ifg_cnt_reg[7:3] != 0) begin
ifg_cnt_next = ifg_cnt_reg - 8'(KEEP_W);
end else begin
ifg_cnt_next = '0;
end
if (s_axis_tx.tvalid && cfg_tx_enable) begin
// Preamble and SFD
output_data_next = {ETH_SFD, {7{ETH_PRE}}};
output_type_next = OUTPUT_TYPE_START_0;
frame_start_next = 1'b1;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_error_next = 1'b0;
frame_min_count_next = MIN_LEN_W'(MIN_FRAME_LEN-4-KEEP_W);
hdr_ptr_next = 0;
frame_len_next = 0;
frame_len_lim_next = cfg_tx_max_pkt_len;
reset_crc = 1'b1;
s_axis_tx_tready_next = 1'b1;
state_next = STATE_PAYLOAD;
end else begin
swap_lanes_next = 1'b0;
ifg_count_next = 8'd0;
deficit_idle_count_next = 2'd0;
state_next = STATE_IDLE;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
s_tdata_next = s_axis_tx_tdata_masked;
s_empty_next = keep2empty(s_axis_tx.tkeep);
if (s_axis_tx.tvalid && cfg_tx_enable) begin
// Preamble and SFD
output_data_next = {ETH_SFD, {7{ETH_PRE}}};
output_type_next = OUTPUT_TYPE_START_0;
frame_start_next = 1'b1;
s_axis_tx_tready_next = 1'b1;
state_next = STATE_PAYLOAD;
end else begin
swap_lanes_next = 1'b0;
ifg_count_next = 8'd0;
deficit_idle_count_next = 2'd0;
state_next = STATE_IDLE;
end
end
end
STATE_PAYLOAD: begin
// transfer payload
update_crc = 1'b1;
s_axis_tx_tready_next = 1'b1;
STATE_PAYLOAD: begin
// transfer payload
update_crc = 1'b1;
s_axis_tx_tready_next = 1'b1;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_DATA;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_DATA;
s_tdata_next = s_axis_tx_tdata_masked;
s_empty_next = keep2empty(s_axis_tx.tkeep);
s_tdata_next = s_axis_tx_tdata_masked;
s_empty_next = keep2empty(s_axis_tx.tkeep);
stat_tx_byte_next = 4'(KEEP_W);
stat_tx_byte_next = 4'(KEEP_W);
if (s_axis_tx.tvalid && s_axis_tx.tlast) begin
frame_oversize_next = frame_len_lim_reg < 16'(8+8+4-keep2empty(s_axis_tx.tkeep));
end else begin
frame_oversize_next = frame_len_lim_reg < 8+8;
end
if (s_axis_tx.tvalid && s_axis_tx.tlast) begin
frame_oversize_next = frame_len_lim_reg < 16'(8+8+4-keep2empty(s_axis_tx.tkeep));
end else begin
frame_oversize_next = frame_len_lim_reg < 8+8;
end
if (!s_axis_tx.tvalid || s_axis_tx.tlast || frame_oversize_next) begin
s_axis_tx_tready_next = frame_next; // drop frame
frame_error_next = !s_axis_tx.tvalid || s_axis_tx.tuser[0] || frame_oversize_next;
stat_tx_err_user_next = s_axis_tx.tuser[0];
stat_tx_err_underflow_next = !s_axis_tx.tvalid;
if (!s_axis_tx.tvalid || s_axis_tx.tlast || frame_oversize_next) begin
s_axis_tx_tready_next = frame_next; // drop frame
frame_error_next = !s_axis_tx.tvalid || s_axis_tx.tuser[0] || frame_oversize_next;
stat_tx_err_user_next = s_axis_tx.tuser[0];
stat_tx_err_underflow_next = !s_axis_tx.tvalid;
if (PADDING_EN && frame_min_count_reg != 0) begin
if (frame_min_count_reg > MIN_LEN_W'(KEEP_W)) begin
s_empty_next = 0;
state_next = STATE_PAD;
end else begin
if (keep2empty(s_axis_tx.tkeep) > 3'(KEEP_W-frame_min_count_reg)) begin
s_empty_next = 3'(KEEP_W-frame_min_count_reg);
if (PADDING_EN && frame_min_count_reg != 0) begin
if (frame_min_count_reg > MIN_LEN_W'(KEEP_W)) begin
s_empty_next = 0;
state_next = STATE_PAD;
end else begin
if (keep2empty(s_axis_tx.tkeep) > 3'(KEEP_W-frame_min_count_reg)) begin
s_empty_next = 3'(KEEP_W-frame_min_count_reg);
end
if (frame_error_next) begin
state_next = STATE_ERR;
end else begin
state_next = STATE_FCS_1;
end
end
end else begin
if (frame_error_next) begin
state_next = STATE_ERR;
end else begin
@@ -527,57 +553,74 @@ always_comb begin
end
end
end else begin
if (frame_error_next) begin
state_next = STATE_PAYLOAD;
end
end
STATE_PAD: begin
// pad frame to MIN_FRAME_LEN
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_DATA;
s_tdata_next = 64'd0;
s_empty_next = 0;
stat_tx_byte_next = 4'(KEEP_W);
update_crc = 1'b1;
if (frame_min_count_reg > MIN_LEN_W'(KEEP_W)) begin
state_next = STATE_PAD;
end else begin
s_empty_next = 3'(KEEP_W-frame_min_count_reg);
if (frame_error_reg) begin
state_next = STATE_ERR;
end else begin
state_next = STATE_FCS_1;
end
end
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_PAD: begin
// pad frame to MIN_FRAME_LEN
s_axis_tx_tready_next = frame_next; // drop frame
STATE_FCS_1: begin
// last cycle
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_DATA;
output_data_next = fcs_output_data_0;
output_type_next = fcs_output_type_0;
s_tdata_next = 64'd0;
s_empty_next = 0;
update_crc = 1'b1;
stat_tx_byte_next = 4'(KEEP_W);
update_crc = 1'b1;
if (frame_min_count_reg > MIN_LEN_W'(KEEP_W)) begin
state_next = STATE_PAD;
end else begin
s_empty_next = 3'(KEEP_W-frame_min_count_reg);
if (frame_error_reg) begin
state_next = STATE_ERR;
ifg_count_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + 8'(deficit_idle_count_reg);
if (s_empty_reg <= 4) begin
stat_tx_byte_next = 4'(KEEP_W);
state_next = STATE_FCS_2;
end else begin
state_next = STATE_FCS_1;
stat_tx_byte_next = 12-s_empty_reg;
frame_len_next = frame_len_reg + 16'(12-s_empty_reg);
stat_tx_pkt_len_next = frame_len_next;
stat_tx_pkt_good_next = !frame_error_reg;
stat_tx_pkt_bad_next = frame_error_reg;
stat_tx_pkt_ucast_next = !is_mcast_reg;
stat_tx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_tx_pkt_bcast_next = is_bcast_reg;
stat_tx_pkt_vlan_next = is_8021q_reg;
stat_tx_err_oversize_next = frame_oversize_reg;
state_next = STATE_IFG;
end
end
end
STATE_FCS_1: begin
// last cycle
s_axis_tx_tready_next = frame_next; // drop frame
STATE_FCS_2: begin
// last cycle
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = fcs_output_data_0;
output_type_next = fcs_output_type_0;
output_data_next = fcs_output_data_1;
output_type_next = fcs_output_type_1;
update_crc = 1'b1;
stat_tx_byte_next = 4-s_empty_reg;
frame_len_next = frame_len_reg + 16'(4-s_empty_reg);
reset_crc = 1'b1;
ifg_count_next = (cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12) - ifg_offset + (swap_lanes_reg ? 8'd4 : 8'd0) + 8'(deficit_idle_count_reg);
if (s_empty_reg <= 4) begin
stat_tx_byte_next = 4'(KEEP_W);
state_next = STATE_FCS_2;
end else begin
stat_tx_byte_next = 12-s_empty_reg;
frame_len_next = frame_len_reg + 16'(12-s_empty_reg);
stat_tx_pkt_len_next = frame_len_next;
stat_tx_pkt_good_next = !frame_error_reg;
stat_tx_pkt_bad_next = frame_error_reg;
@@ -587,120 +630,97 @@ always_comb begin
stat_tx_pkt_vlan_next = is_8021q_reg;
stat_tx_err_oversize_next = frame_oversize_reg;
if (DIC_EN) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = 2'(ifg_count_next - 8'd4);
swap_lanes_next = 1'b1;
end else begin
deficit_idle_count_next = 2'(ifg_count_next);
ifg_count_next = 8'd0;
swap_lanes_next = 1'b0;
end
s_axis_tx_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tx_tready_next = 1'b1;
swap_lanes_next = ifg_count_next != 0;
state_next = STATE_IDLE;
end
end
end
STATE_ERR: begin
// terminate packet with error
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_ERROR;
ifg_count_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12;
stat_tx_pkt_len_next = frame_len_reg;
stat_tx_pkt_good_next = !frame_error_reg;
stat_tx_pkt_bad_next = frame_error_reg;
stat_tx_pkt_ucast_next = !is_mcast_reg;
stat_tx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_tx_pkt_bcast_next = is_bcast_reg;
stat_tx_pkt_vlan_next = is_8021q_reg;
stat_tx_err_oversize_next = frame_oversize_reg;
state_next = STATE_IFG;
end
end
STATE_FCS_2: begin
// last cycle
s_axis_tx_tready_next = frame_next; // drop frame
STATE_IFG: begin
// send IFG
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = fcs_output_data_1;
output_type_next = fcs_output_type_1;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
stat_tx_byte_next = 4-s_empty_reg;
frame_len_next = frame_len_reg + 16'(4-s_empty_reg);
reset_crc = 1'b1;
stat_tx_pkt_len_next = frame_len_next;
stat_tx_pkt_good_next = !frame_error_reg;
stat_tx_pkt_bad_next = frame_error_reg;
stat_tx_pkt_ucast_next = !is_mcast_reg;
stat_tx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_tx_pkt_bcast_next = is_bcast_reg;
stat_tx_pkt_vlan_next = is_8021q_reg;
stat_tx_err_oversize_next = frame_oversize_reg;
if (DIC_EN) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
if (ifg_count_reg > 8'd8) begin
ifg_count_next = ifg_count_reg - 8'd8;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = 2'(ifg_count_next - 8'd4);
swap_lanes_next = 1'b1;
ifg_count_next = 8'd0;
end
reset_crc = 1'b1;
if (DIC_EN) begin
if (ifg_count_next > 8'd7 || frame_reg) begin
state_next = STATE_IFG;
end else begin
deficit_idle_count_next = 2'(ifg_count_next);
ifg_count_next = 8'd0;
swap_lanes_next = 1'b0;
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = 2'(ifg_count_next - 8'd4);
swap_lanes_next = 1'b1;
end else begin
deficit_idle_count_next = 2'(ifg_count_next);
ifg_count_next = 8'd0;
swap_lanes_next = 1'b0;
end
s_axis_tx_tready_next = 1'b1;
state_next = STATE_IDLE;
end
s_axis_tx_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tx_tready_next = 1'b1;
swap_lanes_next = ifg_count_next != 0;
state_next = STATE_IDLE;
end
end
end
STATE_ERR: begin
// terminate packet with error
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_ERROR;
ifg_count_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12;
stat_tx_pkt_len_next = frame_len_reg;
stat_tx_pkt_good_next = !frame_error_reg;
stat_tx_pkt_bad_next = frame_error_reg;
stat_tx_pkt_ucast_next = !is_mcast_reg;
stat_tx_pkt_mcast_next = is_mcast_reg && !is_bcast_reg;
stat_tx_pkt_bcast_next = is_bcast_reg;
stat_tx_pkt_vlan_next = is_8021q_reg;
stat_tx_err_oversize_next = frame_oversize_reg;
state_next = STATE_IFG;
end
STATE_IFG: begin
// send IFG
s_axis_tx_tready_next = frame_next; // drop frame
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
if (ifg_count_reg > 8'd8) begin
ifg_count_next = ifg_count_reg - 8'd8;
end else begin
ifg_count_next = 8'd0;
end
reset_crc = 1'b1;
if (DIC_EN) begin
if (ifg_count_next > 8'd7 || frame_reg) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = 2'(ifg_count_next - 8'd4);
swap_lanes_next = 1'b1;
if (ifg_count_next > 8'd4 || frame_reg) begin
state_next = STATE_IFG;
end else begin
deficit_idle_count_next = 2'(ifg_count_next);
ifg_count_next = 8'd0;
swap_lanes_next = 1'b0;
s_axis_tx_tready_next = 1'b1;
swap_lanes_next = ifg_count_next != 0;
state_next = STATE_IDLE;
end
s_axis_tx_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4 || frame_reg) begin
state_next = STATE_IFG;
end else begin
s_axis_tx_tready_next = 1'b1;
swap_lanes_next = ifg_count_next != 0;
state_next = STATE_IDLE;
end
end
end
default: begin
// invalid state, return to idle
state_next = STATE_IDLE;
end
endcase
default: begin
// invalid state, return to idle
state_next = STATE_IDLE;
end
endcase
end
end
always_ff @(posedge clk) begin
@@ -746,33 +766,6 @@ always_ff @(posedge clk) begin
stat_tx_err_user_reg <= stat_tx_err_user_next;
stat_tx_err_underflow_reg <= stat_tx_err_underflow_next;
delay_type_valid <= 1'b0;
delay_type <= output_type_next ^ 4'd4;
swap_data <= output_data_next[63:32];
if (swap_lanes_reg) begin
output_data_reg <= {output_data_next[31:0], swap_data};
if (delay_type_valid) begin
output_type_reg <= delay_type;
end else if (output_type_next == OUTPUT_TYPE_START_0) begin
output_type_reg <= OUTPUT_TYPE_START_4;
end else if (output_type_next[3]) begin
// OUTPUT_TYPE_TERM_*
if (output_type_next[2]) begin
delay_type_valid <= 1'b1;
output_type_reg <= OUTPUT_TYPE_DATA;
end else begin
output_type_reg <= output_type_next ^ 4'd4;
end
end else begin
output_type_reg <= output_type_next;
end
end else begin
output_data_reg <= output_data_next;
output_type_reg <= output_type_next;
end
if (PTP_TS_EN && PTP_TS_FMT_TOD) begin
m_axis_tx_cpl_valid_reg <= m_axis_tx_cpl_valid_int_reg;
m_axis_tx_cpl_ts_adj_reg[15:0] <= m_axis_tx_cpl_ts_reg[15:0];
@@ -781,113 +774,151 @@ always_ff @(posedge clk) begin
m_axis_tx_cpl_ts_adj_reg[95:48] <= m_axis_tx_cpl_ts_reg[95:48] + 1;
end
if (frame_start_reg) begin
if (GBX_IF_EN && tx_gbx_req_stall) begin
// gearbox stall
encoded_tx_data_valid_reg <= 1'b0;
encoded_tx_hdr_valid_reg <= 1'b0;
end else begin
delay_type_valid <= 1'b0;
delay_type <= output_type_next ^ 4'd4;
swap_data <= output_data_next[63:32];
if (swap_lanes_reg) begin
if (PTP_TS_EN) begin
if (PTP_TS_FMT_TOD) begin
m_axis_tx_cpl_ts_reg[45:0] <= ptp_ts[45:0] + 46'(ts_inc_reg >> 1);
m_axis_tx_cpl_ts_reg[95:48] <= ptp_ts[95:48];
output_data_reg <= {output_data_next[31:0], swap_data};
if (delay_type_valid) begin
output_type_reg <= delay_type;
end else if (output_type_next == OUTPUT_TYPE_START_0) begin
output_type_reg <= OUTPUT_TYPE_START_4;
end else if (output_type_next[3]) begin
// OUTPUT_TYPE_TERM_*
if (output_type_next[2]) begin
delay_type_valid <= 1'b1;
output_type_reg <= OUTPUT_TYPE_DATA;
end else begin
m_axis_tx_cpl_ts_reg <= ptp_ts + PTP_TS_W'(ts_inc_reg >> 1);
output_type_reg <= output_type_next ^ 4'd4;
end
end else begin
output_type_reg <= output_type_next;
end
end else begin
output_data_reg <= output_data_next;
output_type_reg <= output_type_next;
end
if (frame_start_reg) begin
if (swap_lanes_reg) begin
if (PTP_TS_EN) begin
if (PTP_TS_FMT_TOD) begin
m_axis_tx_cpl_ts_reg[45:0] <= ptp_ts[45:0] + 46'(ts_inc_reg >> 1);
m_axis_tx_cpl_ts_reg[95:48] <= ptp_ts[95:48];
end else begin
m_axis_tx_cpl_ts_reg <= ptp_ts + PTP_TS_W'(ts_inc_reg >> 1);
end
end
start_packet_reg <= 2'b10;
end else begin
if (PTP_TS_EN) begin
m_axis_tx_cpl_ts_reg <= ptp_ts;
end
start_packet_reg <= 2'b01;
end
m_axis_tx_cpl_tag_reg <= s_axis_tx.tid;
if (TX_CPL_CTRL_IN_TUSER) begin
if (PTP_TS_FMT_TOD) begin
m_axis_tx_cpl_valid_int_reg <= (s_axis_tx.tuser >> 1) == 0;
end else begin
m_axis_tx_cpl_valid_reg <= (s_axis_tx.tuser >> 1) == 0;
end
end else begin
if (PTP_TS_FMT_TOD) begin
m_axis_tx_cpl_valid_int_reg <= 1'b1;
end else begin
m_axis_tx_cpl_valid_reg <= 1'b1;
end
end
start_packet_reg <= 2'b10;
end else begin
if (PTP_TS_EN) begin
m_axis_tx_cpl_ts_reg <= ptp_ts;
end
start_packet_reg <= 2'b01;
end
m_axis_tx_cpl_tag_reg <= s_axis_tx.tid;
if (TX_CPL_CTRL_IN_TUSER) begin
if (PTP_TS_FMT_TOD) begin
m_axis_tx_cpl_valid_int_reg <= (s_axis_tx.tuser >> 1) == 0;
end else begin
m_axis_tx_cpl_valid_reg <= (s_axis_tx.tuser >> 1) == 0;
case (output_type_reg)
OUTPUT_TYPE_IDLE: begin
encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
end else begin
if (PTP_TS_FMT_TOD) begin
m_axis_tx_cpl_valid_int_reg <= 1'b1;
end else begin
m_axis_tx_cpl_valid_reg <= 1'b1;
OUTPUT_TYPE_ERROR: begin
encoded_tx_data_reg <= {{8{CTRL_ERROR}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_START_0: begin
encoded_tx_data_reg <= {output_data_reg[63:8], BLOCK_TYPE_START_0};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_START_4: begin
encoded_tx_data_reg <= {output_data_reg[63:40], 4'd0, {4{CTRL_IDLE}}, BLOCK_TYPE_START_4};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_DATA: begin
encoded_tx_data_reg <= output_data_reg;
encoded_tx_hdr_reg <= SYNC_DATA;
end
OUTPUT_TYPE_TERM_0: begin
encoded_tx_data_reg <= {{7{CTRL_IDLE}}, 7'd0, BLOCK_TYPE_TERM_0};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_1: begin
encoded_tx_data_reg <= {{6{CTRL_IDLE}}, 6'd0, output_data_reg[7:0], BLOCK_TYPE_TERM_1};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_2: begin
encoded_tx_data_reg <= {{5{CTRL_IDLE}}, 5'd0, output_data_reg[15:0], BLOCK_TYPE_TERM_2};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_3: begin
encoded_tx_data_reg <= {{4{CTRL_IDLE}}, 4'd0, output_data_reg[23:0], BLOCK_TYPE_TERM_3};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_4: begin
encoded_tx_data_reg <= {{3{CTRL_IDLE}}, 3'd0, output_data_reg[31:0], BLOCK_TYPE_TERM_4};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_5: begin
encoded_tx_data_reg <= {{2{CTRL_IDLE}}, 2'd0, output_data_reg[39:0], BLOCK_TYPE_TERM_5};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_6: begin
encoded_tx_data_reg <= {{1{CTRL_IDLE}}, 1'd0, output_data_reg[47:0], BLOCK_TYPE_TERM_6};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_7: begin
encoded_tx_data_reg <= {output_data_reg[55:0], BLOCK_TYPE_TERM_7};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
default: begin
encoded_tx_data_reg <= {{8{CTRL_ERROR}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
endcase
encoded_tx_data_valid_reg <= 1'b1;
encoded_tx_hdr_valid_reg <= 1'b1;
crc_state_reg[0] <= crc_state_next[0];
crc_state_reg[1] <= crc_state_next[1];
crc_state_reg[2] <= crc_state_next[2];
crc_state_reg[3] <= crc_state_next[3];
crc_state_reg[4] <= crc_state_next[4];
crc_state_reg[5] <= crc_state_next[5];
crc_state_reg[6] <= crc_state_next[6];
if (update_crc) begin
crc_state_reg[7] <= crc_state_next[7];
end
if (reset_crc) begin
crc_state_reg[7] <= '1;
end
end
case (output_type_reg)
OUTPUT_TYPE_IDLE: begin
encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_ERROR: begin
encoded_tx_data_reg <= {{8{CTRL_ERROR}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_START_0: begin
encoded_tx_data_reg <= {output_data_reg[63:8], BLOCK_TYPE_START_0};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_START_4: begin
encoded_tx_data_reg <= {output_data_reg[63:40], 4'd0, {4{CTRL_IDLE}}, BLOCK_TYPE_START_4};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_DATA: begin
encoded_tx_data_reg <= output_data_reg;
encoded_tx_hdr_reg <= SYNC_DATA;
end
OUTPUT_TYPE_TERM_0: begin
encoded_tx_data_reg <= {{7{CTRL_IDLE}}, 7'd0, BLOCK_TYPE_TERM_0};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_1: begin
encoded_tx_data_reg <= {{6{CTRL_IDLE}}, 6'd0, output_data_reg[7:0], BLOCK_TYPE_TERM_1};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_2: begin
encoded_tx_data_reg <= {{5{CTRL_IDLE}}, 5'd0, output_data_reg[15:0], BLOCK_TYPE_TERM_2};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_3: begin
encoded_tx_data_reg <= {{4{CTRL_IDLE}}, 4'd0, output_data_reg[23:0], BLOCK_TYPE_TERM_3};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_4: begin
encoded_tx_data_reg <= {{3{CTRL_IDLE}}, 3'd0, output_data_reg[31:0], BLOCK_TYPE_TERM_4};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_5: begin
encoded_tx_data_reg <= {{2{CTRL_IDLE}}, 2'd0, output_data_reg[39:0], BLOCK_TYPE_TERM_5};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_6: begin
encoded_tx_data_reg <= {{1{CTRL_IDLE}}, 1'd0, output_data_reg[47:0], BLOCK_TYPE_TERM_6};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_7: begin
encoded_tx_data_reg <= {output_data_reg[55:0], BLOCK_TYPE_TERM_7};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
default: begin
encoded_tx_data_reg <= {{8{CTRL_ERROR}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
endcase
crc_state_reg[0] <= crc_state_next[0];
crc_state_reg[1] <= crc_state_next[1];
crc_state_reg[2] <= crc_state_next[2];
crc_state_reg[3] <= crc_state_next[3];
crc_state_reg[4] <= crc_state_next[4];
crc_state_reg[5] <= crc_state_next[5];
crc_state_reg[6] <= crc_state_next[6];
if (update_crc) begin
crc_state_reg[7] <= crc_state_next[7];
end
if (reset_crc) begin
crc_state_reg[7] <= '1;
end
tx_gbx_start_reg <= tx_gbx_req_start;
last_ts_reg <= (4+16)'(ptp_ts);
ts_inc_reg <= (4+16)'(ptp_ts) - last_ts_reg;
@@ -909,7 +940,10 @@ always_ff @(posedge clk) begin
m_axis_tx_cpl_valid_int_reg <= 1'b0;
encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
encoded_tx_data_valid_reg <= 1'b0;
encoded_tx_hdr_reg <= SYNC_CTRL;
encoded_tx_hdr_valid_reg <= 1'b0;
tx_gbx_start_reg <= '0;
output_data_reg <= '0;
output_type_reg <= OUTPUT_TYPE_IDLE;

22
src/eth/rtl/taxi_eth_mac_phy_10g.sv
View File

@@ -19,6 +19,8 @@ module taxi_eth_mac_phy_10g #
(
parameter DATA_W = 64,
parameter HDR_W = (DATA_W/32),
parameter logic TX_GBX_IF_EN = 1'b0,
parameter logic RX_GBX_IF_EN = TX_GBX_IF_EN,
parameter logic PADDING_EN = 1'b1,
parameter logic DIC_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
@@ -64,9 +66,16 @@ module taxi_eth_mac_phy_10g #
* SERDES interface
*/
output wire logic [DATA_W-1:0] serdes_tx_data,
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
input wire logic [DATA_W-1:0] serdes_rx_data,
input wire logic serdes_rx_data_valid = 1'b1,
input wire logic [HDR_W-1:0] serdes_rx_hdr,
input wire logic serdes_rx_hdr_valid = 1'b1,
output wire logic serdes_rx_bitslip,
output wire logic serdes_rx_reset_req,
@@ -220,6 +229,7 @@ taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(RX_USER_W)) axis_rx_int();
taxi_eth_mac_phy_10g_rx #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.GBX_IF_EN(RX_GBX_IF_EN),
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
.PTP_TS_W(PTP_TS_W),
@@ -244,7 +254,9 @@ eth_mac_phy_10g_rx_inst (
* SERDES interface
*/
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
@@ -288,6 +300,7 @@ eth_mac_phy_10g_rx_inst (
taxi_eth_mac_phy_10g_tx #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.GBX_IF_EN(TX_GBX_IF_EN),
.PADDING_EN(PADDING_EN),
.DIC_EN(DIC_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
@@ -314,7 +327,12 @@ eth_mac_phy_10g_tx_inst (
* SERDES interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
/*
* PTP
@@ -635,7 +653,7 @@ if (MAC_CTRL_EN) begin : mac_ctrl
.cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
.cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
.cfg_quanta_step(10'((DATA_W*256)/512)),
.cfg_quanta_clk_en(1'b1),
.cfg_quanta_clk_en(!RX_GBX_IF_EN || serdes_tx_data_valid),
/*
* Status
@@ -690,7 +708,7 @@ if (MAC_CTRL_EN) begin : mac_ctrl
.cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
.cfg_rx_pfc_en(cfg_rx_pfc_en),
.cfg_quanta_step(10'((DATA_W*256)/512)),
.cfg_quanta_clk_en(1'b1),
.cfg_quanta_clk_en(!RX_GBX_IF_EN || serdes_rx_data_valid),
/*
* Status

18
src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv
View File

@@ -19,6 +19,8 @@ module taxi_eth_mac_phy_10g_fifo #
(
parameter DATA_W = 64,
parameter HDR_W = (DATA_W/32),
parameter logic TX_GBX_IF_EN = 1'b0,
parameter logic RX_GBX_IF_EN = TX_GBX_IF_EN,
parameter logic PADDING_EN = 1'b1,
parameter logic DIC_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
@@ -78,9 +80,16 @@ module taxi_eth_mac_phy_10g_fifo #
* SERDES interface
*/
output wire logic [DATA_W-1:0] serdes_tx_data,
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
input wire logic [DATA_W-1:0] serdes_rx_data,
input wire logic serdes_rx_data_valid = 1'b1,
input wire logic [HDR_W-1:0] serdes_rx_hdr,
input wire logic serdes_rx_hdr_valid = 1'b1,
output wire logic serdes_rx_bitslip,
output wire logic serdes_rx_reset_req,
@@ -275,6 +284,8 @@ wire stat_rx_fifo_drop;
taxi_eth_mac_phy_10g #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.TX_GBX_IF_EN(TX_GBX_IF_EN),
.RX_GBX_IF_EN(RX_GBX_IF_EN),
.PADDING_EN(PADDING_EN),
.DIC_EN(DIC_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
@@ -318,9 +329,16 @@ eth_mac_phy_10g_inst (
* Serdes interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),

13
src/eth/rtl/taxi_eth_mac_phy_10g_rx.sv
View File

@@ -19,6 +19,7 @@ module taxi_eth_mac_phy_10g_rx #
(
parameter DATA_W = 64,
parameter HDR_W = (DATA_W/32),
parameter logic GBX_IF_EN = 1'b0,
parameter logic PTP_TS_EN = 1'b0,
parameter logic PTP_TS_FMT_TOD = 1'b1,
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
@@ -43,7 +44,9 @@ module taxi_eth_mac_phy_10g_rx #
* SERDES interface
*/
input wire logic [DATA_W-1:0] serdes_rx_data,
input wire logic serdes_rx_data_valid = 1'b1,
input wire logic [HDR_W-1:0] serdes_rx_hdr,
input wire logic serdes_rx_hdr_valid = 1'b1,
output wire logic serdes_rx_bitslip,
output wire logic serdes_rx_reset_req,
@@ -85,11 +88,14 @@ module taxi_eth_mac_phy_10g_rx #
);
wire [DATA_W-1:0] encoded_rx_data;
wire encoded_rx_data_valid;
wire [HDR_W-1:0] encoded_rx_hdr;
wire encoded_rx_hdr_valid;
taxi_eth_phy_10g_rx_if #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_EN(PRBS31_EN),
@@ -106,13 +112,17 @@ eth_phy_10g_rx_if_inst (
* 10GBASE-R encoded interface
*/
.encoded_rx_data(encoded_rx_data),
.encoded_rx_data_valid(encoded_rx_data_valid),
.encoded_rx_hdr(encoded_rx_hdr),
.encoded_rx_hdr_valid(encoded_rx_hdr_valid),
/*
* SERDES interface
*/
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
@@ -135,6 +145,7 @@ eth_phy_10g_rx_if_inst (
taxi_axis_baser_rx_64 #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN),
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
.PTP_TS_W(PTP_TS_W)
@@ -147,7 +158,9 @@ axis_baser_rx_inst (
* 10GBASE-R encoded input
*/
.encoded_rx_data(encoded_rx_data),
.encoded_rx_data_valid(encoded_rx_data_valid),
.encoded_rx_hdr(encoded_rx_hdr),
.encoded_rx_hdr_valid(encoded_rx_hdr_valid),
/*
* Receive interface (AXI stream)

30
src/eth/rtl/taxi_eth_mac_phy_10g_tx.sv
View File

@@ -19,6 +19,7 @@ module taxi_eth_mac_phy_10g_tx #
(
parameter DATA_W = 64,
parameter HDR_W = (DATA_W/32),
parameter logic GBX_IF_EN = 1'b0,
parameter logic PADDING_EN = 1'b1,
parameter logic DIC_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
@@ -45,7 +46,12 @@ module taxi_eth_mac_phy_10g_tx #
* SERDES interface
*/
output wire logic [DATA_W-1:0] serdes_tx_data,
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
/*
* PTP
@@ -78,11 +84,19 @@ module taxi_eth_mac_phy_10g_tx #
);
wire [DATA_W-1:0] encoded_tx_data;
wire encoded_tx_data_valid;
wire [HDR_W-1:0] encoded_tx_hdr;
wire encoded_tx_hdr_valid;
wire tx_gbx_req_start;
wire tx_gbx_req_stall;
wire tx_gbx_start;
taxi_axis_baser_tx_64 #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN),
.GBX_CNT(1),
.PADDING_EN(PADDING_EN),
.DIC_EN(DIC_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
@@ -105,7 +119,12 @@ axis_baser_tx_inst (
* 10GBASE-R encoded interface
*/
.encoded_tx_data(encoded_tx_data),
.encoded_tx_data_valid(encoded_tx_data_valid),
.encoded_tx_hdr(encoded_tx_hdr),
.encoded_tx_hdr_valid(encoded_tx_hdr_valid),
.tx_gbx_req_start(tx_gbx_req_start),
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_start(tx_gbx_start),
/*
* PTP
@@ -139,6 +158,7 @@ axis_baser_tx_inst (
taxi_eth_phy_10g_tx_if #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_EN(PRBS31_EN),
@@ -152,13 +172,23 @@ eth_phy_10g_tx_if_inst (
* 10GBASE-R encoded interface
*/
.encoded_tx_data(encoded_tx_data),
.encoded_tx_data_valid(encoded_tx_data_valid),
.encoded_tx_hdr(encoded_tx_hdr),
.encoded_tx_hdr_valid(encoded_tx_hdr_valid),
.tx_gbx_req_start(tx_gbx_req_start),
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_start(tx_gbx_start),
/*
* SERDES interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
/*
* Configuration

28
src/eth/rtl/taxi_eth_phy_10g.sv
View File

@@ -20,6 +20,8 @@ module taxi_eth_phy_10g #
parameter DATA_W = 64,
parameter CTRL_W = (DATA_W/8),
parameter HDR_W = 2,
parameter logic TX_GBX_IF_EN = 1'b0,
parameter logic RX_GBX_IF_EN = TX_GBX_IF_EN,
parameter logic BIT_REVERSE = 1'b0,
parameter logic SCRAMBLER_DISABLE = 1'b0,
parameter logic PRBS31_EN = 1'b0,
@@ -40,16 +42,28 @@ module taxi_eth_phy_10g #
*/
input wire logic [DATA_W-1:0] xgmii_txd,
input wire logic [CTRL_W-1:0] xgmii_txc,
input wire logic xgmii_tx_valid = 1'b1,
output wire logic [DATA_W-1:0] xgmii_rxd,
output wire logic [CTRL_W-1:0] xgmii_rxc,
output wire logic xgmii_rx_valid = 1'b1,
output wire logic tx_gbx_req_start,
output wire logic tx_gbx_req_stall,
input wire logic tx_gbx_start = 1'b0,
/*
* SERDES interface
*/
output wire logic [DATA_W-1:0] serdes_tx_data,
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
input wire logic [DATA_W-1:0] serdes_rx_data,
input wire logic serdes_rx_data_valid = 1'b1,
input wire logic [HDR_W-1:0] serdes_rx_hdr,
input wire logic serdes_rx_hdr_valid = 1'b1,
output wire logic serdes_rx_bitslip,
output wire logic serdes_rx_reset_req,
@@ -75,6 +89,7 @@ taxi_eth_phy_10g_rx #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.HDR_W(HDR_W),
.GBX_IF_EN(RX_GBX_IF_EN),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_EN(PRBS31_EN),
@@ -92,12 +107,15 @@ eth_phy_10g_rx_inst (
*/
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_rx_valid(xgmii_rx_valid),
/*
* SERDES interface
*/
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
@@ -121,6 +139,7 @@ taxi_eth_phy_10g_tx #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.HDR_W(HDR_W),
.GBX_IF_EN(TX_GBX_IF_EN),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_EN(PRBS31_EN),
@@ -135,12 +154,21 @@ eth_phy_10g_tx_inst (
*/
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.xgmii_tx_valid(xgmii_tx_valid),
.tx_gbx_req_start(tx_gbx_req_start),
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_start(tx_gbx_start),
/*
* SERDES interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
/*
* Status

19
src/eth/rtl/taxi_eth_phy_10g_rx.sv
View File

@@ -20,6 +20,7 @@ module taxi_eth_phy_10g_rx #
parameter DATA_W = 64,
parameter CTRL_W = (DATA_W/8),
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter logic BIT_REVERSE = 1'b0,
parameter logic SCRAMBLER_DISABLE = 1'b0,
parameter logic PRBS31_EN = 1'b0,
@@ -37,12 +38,15 @@ module taxi_eth_phy_10g_rx #
*/
output wire logic [DATA_W-1:0] xgmii_rxd,
output wire logic [CTRL_W-1:0] xgmii_rxc,
output wire logic xgmii_rx_valid,
/*
* SERDES interface
*/
input wire logic [DATA_W-1:0] serdes_rx_data,
input wire logic serdes_rx_data_valid = 1'b1,
input wire logic [HDR_W-1:0] serdes_rx_hdr,
input wire logic serdes_rx_hdr_valid = 1'b1,
output wire logic serdes_rx_bitslip,
output wire logic serdes_rx_reset_req,
@@ -73,11 +77,14 @@ if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
wire [DATA_W-1:0] encoded_rx_data;
wire [HDR_W-1:0] encoded_rx_hdr;
wire encoded_rx_data_valid;
wire [HDR_W-1:0] encoded_rx_hdr;
wire encoded_rx_hdr_valid;
taxi_eth_phy_10g_rx_if #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_EN(PRBS31_EN),
@@ -94,13 +101,17 @@ eth_phy_10g_rx_if_inst (
* 10GBASE-R encoded interface
*/
.encoded_rx_data(encoded_rx_data),
.encoded_rx_data_valid(encoded_rx_data_valid),
.encoded_rx_hdr(encoded_rx_hdr),
.encoded_rx_hdr_valid(encoded_rx_hdr_valid),
/*
* SERDES interface
*/
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(serdes_rx_reset_req),
@@ -123,7 +134,8 @@ eth_phy_10g_rx_if_inst (
taxi_xgmii_baser_dec_64 #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.HDR_W(HDR_W)
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN)
)
xgmii_baser_dec_inst (
.clk(clk),
@@ -133,13 +145,16 @@ xgmii_baser_dec_inst (
* 10GBASE-R encoded input
*/
.encoded_rx_data(encoded_rx_data),
.encoded_rx_data_valid(encoded_rx_data_valid),
.encoded_rx_hdr(encoded_rx_hdr),
.encoded_rx_hdr_valid(encoded_rx_hdr_valid),
/*
* XGMII interface
*/
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_rx_valid(xgmii_rx_valid),
/*
* Status

6
src/eth/rtl/taxi_eth_phy_10g_rx_ber_mon.sv
View File

@@ -18,6 +18,7 @@ Authors:
module taxi_eth_phy_10g_rx_ber_mon #
(
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter COUNT_125US = 125000/6.4
)
(
@@ -28,6 +29,7 @@ module taxi_eth_phy_10g_rx_ber_mon #
* SERDES interface
*/
input wire logic [HDR_W-1:0] serdes_rx_hdr,
input wire logic serdes_rx_hdr_valid,
/*
* Status
@@ -63,7 +65,9 @@ always_comb begin
rx_high_ber_next = rx_high_ber_reg;
if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
if (GBX_IF_EN && !serdes_rx_hdr_valid) begin
// wait for header
end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
if (ber_count_reg != 4'd15) begin
if (time_count_reg == 0) begin

4
src/eth/rtl/taxi_eth_phy_10g_rx_frame_sync.sv
View File

@@ -18,6 +18,7 @@ Authors:
module taxi_eth_phy_10g_rx_frame_sync #
(
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 7
)
@@ -29,6 +30,7 @@ module taxi_eth_phy_10g_rx_frame_sync #
* SERDES interface
*/
input wire logic [HDR_W-1:0] serdes_rx_hdr,
input wire logic serdes_rx_hdr_valid,
output wire logic serdes_rx_bitslip,
/*
@@ -73,6 +75,8 @@ always_comb begin
end else if (serdes_rx_bitslip_reg) begin
serdes_rx_bitslip_next = 1'b0;
bitslip_count_next = BITSLIP_COUNT_W'(BITSLIP_LOW_CYCLES);
end else if (GBX_IF_EN && !serdes_rx_hdr_valid) begin
// wait for header
end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
sh_count_next = sh_count_reg + 1;

48
src/eth/rtl/taxi_eth_phy_10g_rx_if.sv
View File

@@ -19,6 +19,7 @@ module taxi_eth_phy_10g_rx_if #
(
parameter DATA_W = 64,
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter logic BIT_REVERSE = 1'b0,
parameter logic SCRAMBLER_DISABLE = 1'b0,
parameter logic PRBS31_EN = 1'b0,
@@ -35,13 +36,17 @@ module taxi_eth_phy_10g_rx_if #
* 10GBASE-R encoded interface
*/
output wire logic [DATA_W-1:0] encoded_rx_data,
output wire logic encoded_rx_data_valid,
output wire logic [HDR_W-1:0] encoded_rx_hdr,
output wire logic encoded_rx_hdr_valid,
/*
* SERDES interface
*/
input wire logic [DATA_W-1:0] serdes_rx_data,
input wire logic serdes_rx_data_valid,
input wire logic [HDR_W-1:0] serdes_rx_hdr,
input wire logic serdes_rx_hdr_valid,
output wire logic serdes_rx_bitslip,
output wire logic serdes_rx_reset_req,
@@ -69,7 +74,9 @@ if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
wire [DATA_W-1:0] serdes_rx_data_rev, serdes_rx_data_int;
wire [HDR_W-1:0] serdes_rx_hdr_rev, serdes_rx_hdr_int;
wire serdes_rx_data_valid_int;
wire [HDR_W-1:0] serdes_rx_hdr_rev, serdes_rx_hdr_int;
wire serdes_rx_hdr_valid_int;
if (BIT_REVERSE) begin
for (genvar n = 0; n < DATA_W; n = n + 1) begin
@@ -88,36 +95,50 @@ if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
logic [DATA_W-1:0] serdes_rx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
logic [HDR_W-1:0] serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
logic serdes_rx_data_valid_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
logic [HDR_W-1:0] serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
logic serdes_rx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0];
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_rx_data_pipe_reg[n] = '0;
serdes_rx_data_valid_pipe_reg[n] = '0;
serdes_rx_hdr_pipe_reg[n] = '0;
serdes_rx_hdr_valid_pipe_reg[n] = '0;
end
always @(posedge clk) begin
serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1];
serdes_rx_data_valid_pipe_reg[n] <= n == 0 ? serdes_rx_data_valid : serdes_rx_data_valid_pipe_reg[n-1];
serdes_rx_hdr_pipe_reg[n] <= n == 0 ? serdes_rx_hdr_rev : serdes_rx_hdr_pipe_reg[n-1];
serdes_rx_hdr_valid_pipe_reg[n] <= n == 0 ? serdes_rx_hdr_valid : serdes_rx_hdr_valid_pipe_reg[n-1];
end
end
assign serdes_rx_data_int = serdes_rx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_rx_data_valid_int = serdes_rx_data_valid_pipe_reg[SERDES_PIPELINE-1];
assign serdes_rx_hdr_int = serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1];
assign serdes_rx_hdr_valid_int = serdes_rx_hdr_valid_pipe_reg[SERDES_PIPELINE-1];
end else begin
assign serdes_rx_data_int = serdes_rx_data_rev;
assign serdes_rx_data_valid_int = serdes_rx_data_valid;
assign serdes_rx_hdr_int = serdes_rx_hdr_rev;
assign serdes_rx_hdr_valid_int = serdes_rx_hdr_valid;
end
wire [DATA_W-1:0] descrambled_rx_data;
logic [DATA_W-1:0] encoded_rx_data_reg = '0;
logic encoded_rx_data_valid_reg = 1'b0;
logic [HDR_W-1:0] encoded_rx_hdr_reg = '0;
logic encoded_rx_hdr_valid_reg = 1'b0;
logic [57:0] scrambler_state_reg = {58{1'b1}};
logic [57:0] scrambler_state_reg = '1;
wire [57:0] scrambler_state;
logic [30:0] prbs31_state_reg = 31'h7fffffff;
logic [30:0] prbs31_state_reg = '1;
wire [30:0] prbs31_state;
wire [DATA_W+HDR_W-1:0] prbs31_data;
logic [DATA_W+HDR_W-1:0] prbs31_data_reg = '0;
@@ -143,6 +164,12 @@ descrambler_inst (
.state_out(scrambler_state)
);
always_ff @(posedge clk) begin
if (!GBX_IF_EN || serdes_rx_data_valid_int) begin
scrambler_state_reg <= scrambler_state;
end
end
taxi_lfsr #(
.LFSR_W(31),
.LFSR_POLY(31'h10000001),
@@ -171,13 +198,13 @@ always_comb begin
end
always_ff @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data;
encoded_rx_data_valid_reg <= serdes_rx_data_valid_int;
encoded_rx_hdr_reg <= serdes_rx_hdr_int;
encoded_rx_hdr_valid_reg <= serdes_rx_hdr_valid_int;
if (PRBS31_EN) begin
if (cfg_rx_prbs31_enable) begin
if (cfg_rx_prbs31_enable && (!GBX_IF_EN || serdes_rx_data_valid_int)) begin
prbs31_state_reg <= prbs31_state;
prbs31_data_reg <= prbs31_data;
end else begin
@@ -193,7 +220,9 @@ always_ff @(posedge clk) begin
end
assign encoded_rx_data = encoded_rx_data_reg;
assign encoded_rx_data_valid = GBX_IF_EN ? encoded_rx_data_valid_reg : 1'b1;
assign encoded_rx_hdr = encoded_rx_hdr_reg;
assign encoded_rx_hdr_valid = GBX_IF_EN ? encoded_rx_hdr_valid_reg : 1'b1;
assign rx_error_count = rx_error_count_reg;
@@ -204,6 +233,7 @@ assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_EN && cfg_rx_pr
taxi_eth_phy_10g_rx_frame_sync #(
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES)
)
@@ -211,6 +241,7 @@ eth_phy_10g_rx_frame_sync_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid_int),
.serdes_rx_bitslip(serdes_rx_bitslip_int),
.rx_block_lock(rx_block_lock)
);
@@ -223,17 +254,20 @@ eth_phy_10g_rx_ber_mon_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid_int),
.rx_high_ber(rx_high_ber)
);
taxi_eth_phy_10g_rx_watchdog #(
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_watchdog_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid_int),
.serdes_rx_reset_req(serdes_rx_reset_req_int),
.rx_bad_block(rx_bad_block),
.rx_sequence_error(rx_sequence_error),

4
src/eth/rtl/taxi_eth_phy_10g_rx_watchdog.sv
View File

@@ -18,6 +18,7 @@ Authors:
module taxi_eth_phy_10g_rx_watchdog #
(
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter COUNT_125US = 125000/6.4
)
(
@@ -28,6 +29,7 @@ module taxi_eth_phy_10g_rx_watchdog #
* SERDES interface
*/
input wire logic [HDR_W-1:0] serdes_rx_hdr,
input wire logic serdes_rx_hdr_valid,
output wire logic serdes_rx_reset_req,
/*
@@ -82,7 +84,7 @@ always_comb begin
rx_status_next = rx_status_reg;
if (rx_block_lock) begin
if (serdes_rx_hdr == SYNC_CTRL) begin
if (serdes_rx_hdr == SYNC_CTRL && (!GBX_IF_EN || serdes_rx_hdr_valid)) begin
saw_ctrl_sh_next = 1'b1;
end
if ((rx_bad_block || rx_sequence_error) && !(&block_error_count_reg)) begin

34
src/eth/rtl/taxi_eth_phy_10g_tx.sv
View File

@@ -20,6 +20,7 @@ module taxi_eth_phy_10g_tx #
parameter DATA_W = 64,
parameter CTRL_W = (DATA_W/8),
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter logic BIT_REVERSE = 1'b0,
parameter logic SCRAMBLER_DISABLE = 1'b0,
parameter logic PRBS31_EN = 1'b0,
@@ -34,12 +35,21 @@ module taxi_eth_phy_10g_tx #
*/
input wire logic [DATA_W-1:0] xgmii_txd,
input wire logic [CTRL_W-1:0] xgmii_txc,
input wire logic xgmii_tx_valid = 1'b1,
output wire logic tx_gbx_req_start,
output wire logic tx_gbx_req_stall,
input wire logic tx_gbx_start = 1'b0,
/*
* SERDES interface
*/
output wire logic [DATA_W-1:0] serdes_tx_data,
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
/*
* Status
@@ -63,12 +73,18 @@ if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
wire [DATA_W-1:0] encoded_tx_data;
wire encoded_tx_data_valid;
wire [HDR_W-1:0] encoded_tx_hdr;
wire encoded_tx_hdr_valid;
wire tx_gbx_start_int;
taxi_xgmii_baser_enc_64 #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.HDR_W(HDR_W)
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN),
.GBX_CNT(1)
)
xgmii_baser_enc_inst (
.clk(clk),
@@ -79,12 +95,17 @@ xgmii_baser_enc_inst (
*/
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.xgmii_tx_valid(xgmii_tx_valid),
.tx_gbx_start_in(tx_gbx_start),
/*
* 10GBASE-R encoded interface
*/
.encoded_tx_data(encoded_tx_data),
.encoded_tx_data_valid(encoded_tx_data_valid),
.encoded_tx_hdr(encoded_tx_hdr),
.encoded_tx_hdr_valid(encoded_tx_hdr_valid),
.tx_gbx_start_out(tx_gbx_start_int),
/*
* Status
@@ -95,6 +116,7 @@ xgmii_baser_enc_inst (
taxi_eth_phy_10g_tx_if #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.GBX_IF_EN(GBX_IF_EN),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_EN(PRBS31_EN),
@@ -108,13 +130,23 @@ eth_phy_10g_tx_if_inst (
* 10GBASE-R encoded interface
*/
.encoded_tx_data(encoded_tx_data),
.encoded_tx_data_valid(encoded_tx_data_valid),
.encoded_tx_hdr(encoded_tx_hdr),
.encoded_tx_hdr_valid(encoded_tx_hdr_valid),
.tx_gbx_req_start(tx_gbx_req_start),
.tx_gbx_req_stall(tx_gbx_req_stall),
.tx_gbx_start(tx_gbx_start_int),
/*
* SERDES interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
/*
* Configuration

58
src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
View File

@@ -19,6 +19,7 @@ module taxi_eth_phy_10g_tx_if #
(
parameter DATA_W = 64,
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter logic BIT_REVERSE = 1'b0,
parameter logic SCRAMBLER_DISABLE = 1'b0,
parameter logic PRBS31_EN = 1'b0,
@@ -32,13 +33,22 @@ module taxi_eth_phy_10g_tx_if #
* 10GBASE-R encoded interface
*/
input wire logic [DATA_W-1:0] encoded_tx_data,
input wire logic encoded_tx_data_valid = 1'b1,
input wire logic [HDR_W-1:0] encoded_tx_hdr,
input wire logic encoded_tx_hdr_valid = 1'b1,
output wire logic tx_gbx_req_start,
output wire logic tx_gbx_req_stall,
input wire logic tx_gbx_start = 1'b0,
/*
* SERDES interface
*/
output wire logic [DATA_W-1:0] serdes_tx_data,
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
/*
* Configuration
@@ -53,19 +63,25 @@ if (DATA_W != 64)
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
assign tx_gbx_req_start = GBX_IF_EN ? serdes_tx_gbx_req_start : '0;
assign tx_gbx_req_stall = GBX_IF_EN ? serdes_tx_gbx_req_stall : '0;
logic [57:0] scrambler_state_reg = '1;
wire [57:0] scrambler_state;
wire [DATA_W-1:0] scrambled_data;
logic [30:0] prbs31_state_reg = 31'h7fffffff;
logic [30:0] prbs31_state_reg = '1;
wire [30:0] prbs31_state;
wire [DATA_W+HDR_W-1:0] prbs31_data;
logic [DATA_W-1:0] serdes_tx_data_reg = '0;
logic serdes_tx_data_valid_reg = 1'b0;
logic [HDR_W-1:0] serdes_tx_hdr_reg = '0;
logic serdes_tx_hdr_valid_reg = 1'b0;
logic serdes_tx_gbx_start_reg = 1'b0;
wire [DATA_W-1:0] serdes_tx_data_int;
wire [HDR_W-1:0] serdes_tx_hdr_int;
wire [HDR_W-1:0] serdes_tx_hdr_int;
if (BIT_REVERSE) begin
for (genvar n = 0; n < DATA_W; n = n + 1) begin
@@ -84,25 +100,43 @@ if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
reg [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
reg serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg serdes_tx_gbx_start_pipe_reg[SERDES_PIPELINE-1:0];
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_tx_data_pipe_reg[n] = '0;
serdes_tx_data_valid_pipe_reg[n] = '0;
serdes_tx_hdr_pipe_reg[n] = '0;
serdes_tx_hdr_valid_pipe_reg[n] = '0;
serdes_tx_gbx_start_pipe_reg[n] = '0;
end
always @(posedge clk) begin
serdes_tx_data_pipe_reg[n] <= n == 0 ? serdes_tx_data_int : serdes_tx_data_pipe_reg[n-1];
serdes_tx_data_valid_pipe_reg[n] <= n == 0 ? serdes_tx_data_valid_reg : serdes_tx_data_valid_pipe_reg[n-1];
serdes_tx_hdr_pipe_reg[n] <= n == 0 ? serdes_tx_hdr_int : serdes_tx_hdr_pipe_reg[n-1];
serdes_tx_hdr_valid_pipe_reg[n] <= n == 0 ? serdes_tx_hdr_valid_reg : serdes_tx_hdr_valid_pipe_reg[n-1];
serdes_tx_gbx_start_pipe_reg[n] <= n == 0 ? serdes_tx_gbx_start_reg : serdes_tx_gbx_start_pipe_reg[n-1];
end
end
assign serdes_tx_data = serdes_tx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_tx_data_valid = GBX_IF_EN ? serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
assign serdes_tx_hdr = serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1];
assign serdes_tx_hdr_valid = GBX_IF_EN ? serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
assign serdes_tx_gbx_start = GBX_IF_EN ? serdes_tx_gbx_start_pipe_reg[SERDES_PIPELINE-1] : 1'b0;
end else begin
assign serdes_tx_data = serdes_tx_data_int;
assign serdes_tx_data_valid = GBX_IF_EN ? serdes_tx_data_valid_reg : 1'b1;
assign serdes_tx_hdr = serdes_tx_hdr_int;
assign serdes_tx_hdr_valid = GBX_IF_EN ? serdes_tx_hdr_valid_reg : 1'b1;
assign serdes_tx_gbx_start = GBX_IF_EN ? serdes_tx_gbx_start_reg : 1'b0;
end
taxi_lfsr #(
@@ -120,6 +154,12 @@ scrambler_inst (
.state_out(scrambler_state)
);
always_ff @(posedge clk) begin
if (!GBX_IF_EN || encoded_tx_data_valid) begin
scrambler_state_reg <= scrambler_state;
end
end
taxi_lfsr #(
.LFSR_W(31),
.LFSR_POLY(31'h10000001),
@@ -136,10 +176,10 @@ prbs31_gen_inst (
);
always_ff @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
if (PRBS31_EN && cfg_tx_prbs31_enable) begin
prbs31_state_reg <= prbs31_state;
if (!GBX_IF_EN || encoded_tx_data_valid) begin
prbs31_state_reg <= prbs31_state;
end
serdes_tx_data_reg <= ~prbs31_data[DATA_W+HDR_W-1:HDR_W];
serdes_tx_hdr_reg <= ~prbs31_data[HDR_W-1:0];
@@ -147,6 +187,10 @@ always_ff @(posedge clk) begin
serdes_tx_data_reg <= SCRAMBLER_DISABLE ? encoded_tx_data : scrambled_data;
serdes_tx_hdr_reg <= encoded_tx_hdr;
end
serdes_tx_data_valid_reg <= encoded_tx_data_valid;
serdes_tx_hdr_valid_reg <= encoded_tx_hdr_valid;
serdes_tx_gbx_start_reg <= tx_gbx_start;
end
endmodule

23
src/eth/rtl/taxi_xgmii_baser_dec_64.sv
View File

@@ -19,7 +19,8 @@ module taxi_xgmii_baser_dec_64 #
(
parameter DATA_W = 64,
parameter CTRL_W = (DATA_W/8),
parameter HDR_W = 2
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0
)
(
input wire logic clk,
@@ -29,13 +30,16 @@ module taxi_xgmii_baser_dec_64 #
* 10GBASE-R encoded input
*/
input wire logic [DATA_W-1:0] encoded_rx_data,
input wire logic encoded_rx_data_valid = 1'b1,
input wire logic [HDR_W-1:0] encoded_rx_hdr,
input wire logic encoded_rx_hdr_valid = 1'b1,
/*
* XGMII interface
*/
output wire logic [DATA_W-1:0] xgmii_rxd,
output wire logic [CTRL_W-1:0] xgmii_rxc,
output wire logic xgmii_rx_valid,
/*
* Status
@@ -110,6 +114,7 @@ logic [CTRL_W-1:0] decode_err;
logic [DATA_W-1:0] xgmii_rxd_reg = '0, xgmii_rxd_next;
logic [CTRL_W-1:0] xgmii_rxc_reg = '0, xgmii_rxc_next;
logic xgmii_rx_valid_reg = 1'b0, xgmii_rx_valid_next;
logic rx_bad_block_reg = 1'b0, rx_bad_block_next;
logic rx_sequence_error_reg = 1'b0, rx_sequence_error_next;
@@ -117,6 +122,7 @@ logic frame_reg = 1'b0, frame_next;
assign xgmii_rxd = xgmii_rxd_reg;
assign xgmii_rxc = xgmii_rxc_reg;
assign xgmii_rx_valid = xgmii_rx_valid_reg;
assign rx_bad_block = rx_bad_block_reg;
assign rx_sequence_error = rx_sequence_error_reg;
@@ -124,6 +130,7 @@ assign rx_sequence_error = rx_sequence_error_reg;
always_comb begin
xgmii_rxd_next = {8{XGMII_ERROR}};
xgmii_rxc_next = 8'hff;
xgmii_rx_valid_next = 1'b0;
rx_bad_block_next = 1'b0;
rx_sequence_error_next = 1'b0;
frame_next = frame_reg;
@@ -173,12 +180,16 @@ always_comb begin
endcase
end
// use only four bits of block type for reduced fanin
if (encoded_rx_hdr[0] == 0) begin
if (GBX_IF_EN && !encoded_rx_data_valid) begin
// wait for data
end else if (encoded_rx_hdr[0] == 0) begin
// data block
xgmii_rxd_next = encoded_rx_data;
xgmii_rxc_next = 8'h00;
rx_bad_block_next = 1'b0;
end else begin
// control block
// use only four bits of block type for reduced fanin
case (encoded_rx_data[7:4])
BLOCK_TYPE_CTRL[7:4]: begin
// C7 C6 C5 C4 C3 C2 C1 C0 BT
@@ -340,7 +351,9 @@ always_comb begin
end
// check all block type bits to detect bad encodings
if (encoded_rx_hdr == SYNC_DATA) begin
if (GBX_IF_EN && !encoded_rx_hdr_valid) begin
// wait for header
end else if (encoded_rx_hdr == SYNC_DATA) begin
// data - nothing encoded
end else if (encoded_rx_hdr == SYNC_CTRL) begin
// control - check for bad block types
@@ -378,12 +391,14 @@ end
always_ff @(posedge clk) begin
xgmii_rxd_reg <= xgmii_rxd_next;
xgmii_rxc_reg <= xgmii_rxc_next;
xgmii_rx_valid_reg <= xgmii_rx_valid_next;
rx_bad_block_reg <= rx_bad_block_next;
rx_sequence_error_reg <= rx_sequence_error_next;
frame_reg <= frame_next;
if (rst) begin
xgmii_rx_valid_reg <= 1'b0;
frame_reg <= 1'b0;
end
end

40
src/eth/rtl/taxi_xgmii_baser_enc_64.sv
View File

@@ -19,28 +19,35 @@ module taxi_xgmii_baser_enc_64 #
(
parameter DATA_W = 64,
parameter CTRL_W = (DATA_W/8),
parameter HDR_W = 2
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter GBX_CNT = 1
)
(
input wire logic clk,
input wire logic rst,
input wire logic clk,
input wire logic rst,
/*
* XGMII interface
*/
input wire logic [DATA_W-1:0] xgmii_txd,
input wire logic [CTRL_W-1:0] xgmii_txc,
input wire logic [DATA_W-1:0] xgmii_txd,
input wire logic [CTRL_W-1:0] xgmii_txc,
input wire logic xgmii_tx_valid = 1'b1,
input wire logic [GBX_CNT-1:0] tx_gbx_start_in = '0,
/*
* 10GBASE-R encoded interface
*/
output wire logic [DATA_W-1:0] encoded_tx_data,
output wire logic [HDR_W-1:0] encoded_tx_hdr,
output wire logic [DATA_W-1:0] encoded_tx_data,
output wire logic encoded_tx_data_valid,
output wire logic [HDR_W-1:0] encoded_tx_hdr,
output wire logic encoded_tx_hdr_valid,
output wire logic [GBX_CNT-1:0] tx_gbx_start_out,
/*
* Status
*/
output wire logic tx_bad_block
output wire logic tx_bad_block
);
// check configuration
@@ -108,12 +115,18 @@ logic [DATA_W*7/8-1:0] encoded_ctrl;
logic [CTRL_W-1:0] encode_err;
logic [DATA_W-1:0] encoded_tx_data_reg = '0, encoded_tx_data_next;
logic encoded_tx_data_valid_reg = 1'b0, encoded_tx_data_valid_next;
logic [HDR_W-1:0] encoded_tx_hdr_reg = '0, encoded_tx_hdr_next;
logic encoded_tx_hdr_valid_reg = 1'b0, encoded_tx_hdr_valid_next;
logic [GBX_CNT-1:0] tx_gbx_start_reg = '0, tx_gbx_start_next;
logic tx_bad_block_reg = 1'b0, tx_bad_block_next;
assign encoded_tx_data = encoded_tx_data_reg;
assign encoded_tx_data_valid = GBX_IF_EN ? encoded_tx_data_valid_reg : 1'b1;
assign encoded_tx_hdr = encoded_tx_hdr_reg;
assign encoded_tx_hdr_valid = GBX_IF_EN ? encoded_tx_hdr_valid_reg : 1'b1;
assign tx_gbx_start_out = GBX_IF_EN ? tx_gbx_start_reg : '0;
assign tx_bad_block = tx_bad_block_reg;
@@ -244,11 +257,22 @@ always_comb begin
end
encoded_tx_hdr_next = SYNC_CTRL;
end
if (GBX_IF_EN && !xgmii_tx_valid) begin
tx_bad_block_next = 1'b0;
end
encoded_tx_data_valid_next = xgmii_tx_valid;
encoded_tx_hdr_valid_next = xgmii_tx_valid;
tx_gbx_start_next = tx_gbx_start_in;
end
always_ff @(posedge clk) begin
encoded_tx_data_reg <= encoded_tx_data_next;
encoded_tx_data_valid_reg <= encoded_tx_data_valid_next;
encoded_tx_hdr_reg <= encoded_tx_hdr_next;
encoded_tx_hdr_valid_reg <= encoded_tx_hdr_valid_next;
tx_gbx_start_reg <= tx_gbx_start_next;
tx_bad_block_reg <= tx_bad_block_next;
end

1
src/eth/rtl/us/taxi_eth_mac_25g_us.f
View File

@@ -1,4 +1,5 @@
taxi_eth_mac_25g_us.sv
taxi_eth_mac_25g_us_ch.sv
taxi_eth_phy_25g_us_gt.f
taxi_eth_phy_25g_us_gt_ll.f
../taxi_eth_mac_phy_10g.f

6
src/eth/rtl/us/taxi_eth_mac_25g_us.sv
View File

@@ -23,6 +23,9 @@ module taxi_eth_mac_25g_us #
parameter CNT = 4,
// GT config
parameter logic CFG_LOW_LATENCY = 0,
// GT type
parameter string GT_TYPE = "GTY",
@@ -333,6 +336,9 @@ for (genvar n = 0; n < CNT; n = n + 1) begin : ch
.HAS_COMMON(HAS_COMMON),
// GT config
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
// GT type
.GT_TYPE(GT_TYPE),

334
src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv
View File

@@ -23,6 +23,9 @@ module taxi_eth_mac_25g_us_ch #
parameter logic HAS_COMMON = 1'b1,
// GT config
parameter logic CFG_LOW_LATENCY = 0,
// GT type
parameter string GT_TYPE = "GTY",
@@ -278,130 +281,244 @@ localparam HDR_W = 2;
wire rx_reset_req;
wire [5:0] gt_txheader;
wire [63:0] gt_txdata;
wire gt_rxgearboxslip;
wire [5:0] gt_rxheader;
wire [1:0] gt_rxheadervalid;
wire [63:0] gt_rxdata;
wire [1:0] gt_rxdatavalid;
wire [DATA_W-1:0] serdes_tx_data;
wire serdes_tx_data_valid;
wire [HDR_W-1:0] serdes_tx_hdr;
wire serdes_tx_hdr_valid;
wire serdes_tx_gbx_req_start;
wire serdes_tx_gbx_req_stall;
wire serdes_tx_gbx_start;
wire [DATA_W-1:0] serdes_rx_data;
wire serdes_rx_data_valid;
wire [HDR_W-1:0] serdes_rx_hdr;
wire serdes_rx_hdr_valid;
wire serdes_rx_bitslip;
taxi_eth_phy_25g_us_gt #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY),
if (CFG_LOW_LATENCY) begin : gt
.HAS_COMMON(HAS_COMMON),
taxi_eth_phy_25g_us_gt_ll #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY),
// GT type
.GT_TYPE(GT_TYPE),
.HAS_COMMON(HAS_COMMON),
// PLL parameters
.QPLL0_PD(QPLL0_PD),
.QPLL1_PD(QPLL1_PD),
.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
// GT type
.GT_TYPE(GT_TYPE),
// GT parameters
.GT_TX_PD(GT_TX_PD),
.GT_TX_QPLL_SEL(GT_TX_QPLL_SEL),
.GT_TX_POLARITY(GT_TX_POLARITY),
.GT_TX_ELECIDLE(GT_TX_ELECIDLE),
.GT_TX_INHIBIT(GT_TX_INHIBIT),
.GT_TX_DIFFCTRL(GT_TX_DIFFCTRL),
.GT_TX_MAINCURSOR(GT_TX_MAINCURSOR),
.GT_TX_POSTCURSOR(GT_TX_POSTCURSOR),
.GT_TX_PRECURSOR(GT_TX_PRECURSOR),
.GT_RX_PD(GT_RX_PD),
.GT_RX_QPLL_SEL(GT_RX_QPLL_SEL),
.GT_RX_LPM_EN(GT_RX_LPM_EN),
.GT_RX_POLARITY(GT_RX_POLARITY)
)
gt_inst (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
// PLL parameters
.QPLL0_PD(QPLL0_PD),
.QPLL1_PD(QPLL1_PD),
.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
/*
* Common
*/
.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
// GT parameters
.GT_TX_PD(GT_TX_PD),
.GT_TX_QPLL_SEL(GT_TX_QPLL_SEL),
.GT_TX_POLARITY(GT_TX_POLARITY),
.GT_TX_ELECIDLE(GT_TX_ELECIDLE),
.GT_TX_INHIBIT(GT_TX_INHIBIT),
.GT_TX_DIFFCTRL(GT_TX_DIFFCTRL),
.GT_TX_MAINCURSOR(GT_TX_MAINCURSOR),
.GT_TX_POSTCURSOR(GT_TX_POSTCURSOR),
.GT_TX_PRECURSOR(GT_TX_PRECURSOR),
.GT_RX_PD(GT_RX_PD),
.GT_RX_QPLL_SEL(GT_RX_QPLL_SEL),
.GT_RX_LPM_EN(GT_RX_LPM_EN),
.GT_RX_POLARITY(GT_RX_POLARITY),
/*
* PLL out
*/
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
.xcvr_qpll0lock_out(xcvr_qpll0lock_out),
.xcvr_qpll0clk_out(xcvr_qpll0clk_out),
.xcvr_qpll0refclk_out(xcvr_qpll0refclk_out),
.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
.xcvr_qpll1lock_out(xcvr_qpll1lock_out),
.xcvr_qpll1clk_out(xcvr_qpll1clk_out),
.xcvr_qpll1refclk_out(xcvr_qpll1refclk_out),
// MAC/PHY parameters
.DATA_W(DATA_W),
.HDR_W(HDR_W)
)
gt_inst (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
/*
* PLL in
*/
.xcvr_qpll0lock_in(xcvr_qpll0lock_in),
.xcvr_qpll0clk_in(xcvr_qpll0clk_in),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk_in),
.xcvr_qpll1lock_in(xcvr_qpll1lock_in),
.xcvr_qpll1clk_in(xcvr_qpll1clk_in),
.xcvr_qpll1refclk_in(xcvr_qpll1refclk_in),
/*
* Common
*/
.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
/*
* Serial data
*/
.xcvr_txp(xcvr_txp),
.xcvr_txn(xcvr_txn),
.xcvr_rxp(xcvr_rxp),
.xcvr_rxn(xcvr_rxn),
/*
* PLL out
*/
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
.xcvr_qpll0lock_out(xcvr_qpll0lock_out),
.xcvr_qpll0clk_out(xcvr_qpll0clk_out),
.xcvr_qpll0refclk_out(xcvr_qpll0refclk_out),
.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
.xcvr_qpll1lock_out(xcvr_qpll1lock_out),
.xcvr_qpll1clk_out(xcvr_qpll1clk_out),
.xcvr_qpll1refclk_out(xcvr_qpll1refclk_out),
/*
* GT user clocks
*/
.rx_clk(rx_clk),
.rx_rst_in(rx_rst_in || rx_reset_req),
.rx_rst_out(rx_rst_out),
.tx_clk(tx_clk),
.tx_rst_in(tx_rst_in),
.tx_rst_out(tx_rst_out),
/*
* PLL in
*/
.xcvr_qpll0lock_in(xcvr_qpll0lock_in),
.xcvr_qpll0clk_in(xcvr_qpll0clk_in),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk_in),
.xcvr_qpll1lock_in(xcvr_qpll1lock_in),
.xcvr_qpll1clk_in(xcvr_qpll1clk_in),
.xcvr_qpll1refclk_in(xcvr_qpll1refclk_in),
/*
* Serdes interface
*/
.gt_txheader(gt_txheader),
.gt_txdata(gt_txdata),
.gt_rxgearboxslip(gt_rxgearboxslip),
.gt_rxheader(gt_rxheader),
.gt_rxheadervalid(gt_rxheadervalid),
.gt_rxdata(gt_rxdata),
.gt_rxdatavalid(gt_rxdatavalid)
);
/*
* Serial data
*/
.xcvr_txp(xcvr_txp),
.xcvr_txn(xcvr_txn),
.xcvr_rxp(xcvr_rxp),
.xcvr_rxn(xcvr_rxn),
wire [DATA_W-1:0] serdes_tx_data;
wire [HDR_W-1:0] serdes_tx_hdr;
wire [DATA_W-1:0] serdes_rx_data;
wire [HDR_W-1:0] serdes_rx_hdr;
wire serdes_rx_bitslip;
/*
* GT user clocks
*/
.rx_clk(rx_clk),
.rx_rst_in(rx_rst_in || rx_reset_req),
.rx_rst_out(rx_rst_out),
.tx_clk(tx_clk),
.tx_rst_in(tx_rst_in),
.tx_rst_out(tx_rst_out),
assign gt_txdata = serdes_tx_data;
assign gt_txheader = {4'd0, serdes_tx_hdr};
assign gt_rxgearboxslip = serdes_rx_bitslip;
/*
* Serdes interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
.serdes_rx_bitslip(serdes_rx_bitslip)
);
end else begin : gt
taxi_eth_phy_25g_us_gt #(
.SIM(SIM),
.VENDOR(VENDOR),
.FAMILY(FAMILY),
.HAS_COMMON(HAS_COMMON),
// GT type
.GT_TYPE(GT_TYPE),
// PLL parameters
.QPLL0_PD(QPLL0_PD),
.QPLL1_PD(QPLL1_PD),
.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
// GT parameters
.GT_TX_PD(GT_TX_PD),
.GT_TX_QPLL_SEL(GT_TX_QPLL_SEL),
.GT_TX_POLARITY(GT_TX_POLARITY),
.GT_TX_ELECIDLE(GT_TX_ELECIDLE),
.GT_TX_INHIBIT(GT_TX_INHIBIT),
.GT_TX_DIFFCTRL(GT_TX_DIFFCTRL),
.GT_TX_MAINCURSOR(GT_TX_MAINCURSOR),
.GT_TX_POSTCURSOR(GT_TX_POSTCURSOR),
.GT_TX_PRECURSOR(GT_TX_PRECURSOR),
.GT_RX_PD(GT_RX_PD),
.GT_RX_QPLL_SEL(GT_RX_QPLL_SEL),
.GT_RX_LPM_EN(GT_RX_LPM_EN),
.GT_RX_POLARITY(GT_RX_POLARITY),
// MAC/PHY parameters
.DATA_W(DATA_W),
.HDR_W(HDR_W)
)
gt_inst (
.xcvr_ctrl_clk(xcvr_ctrl_clk),
.xcvr_ctrl_rst(xcvr_ctrl_rst),
/*
* Common
*/
.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
/*
* PLL out
*/
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
.xcvr_qpll0lock_out(xcvr_qpll0lock_out),
.xcvr_qpll0clk_out(xcvr_qpll0clk_out),
.xcvr_qpll0refclk_out(xcvr_qpll0refclk_out),
.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
.xcvr_qpll1lock_out(xcvr_qpll1lock_out),
.xcvr_qpll1clk_out(xcvr_qpll1clk_out),
.xcvr_qpll1refclk_out(xcvr_qpll1refclk_out),
/*
* PLL in
*/
.xcvr_qpll0lock_in(xcvr_qpll0lock_in),
.xcvr_qpll0clk_in(xcvr_qpll0clk_in),
.xcvr_qpll0refclk_in(xcvr_qpll0refclk_in),
.xcvr_qpll1lock_in(xcvr_qpll1lock_in),
.xcvr_qpll1clk_in(xcvr_qpll1clk_in),
.xcvr_qpll1refclk_in(xcvr_qpll1refclk_in),
/*
* Serial data
*/
.xcvr_txp(xcvr_txp),
.xcvr_txn(xcvr_txn),
.xcvr_rxp(xcvr_rxp),
.xcvr_rxn(xcvr_rxn),
/*
* GT user clocks
*/
.rx_clk(rx_clk),
.rx_rst_in(rx_rst_in || rx_reset_req),
.rx_rst_out(rx_rst_out),
.tx_clk(tx_clk),
.tx_rst_in(tx_rst_in),
.tx_rst_out(tx_rst_out),
/*
* Serdes interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
.serdes_rx_bitslip(serdes_rx_bitslip)
);
if (!SIM) begin
assign serdes_rx_data = gt_rxdata;
assign serdes_rx_hdr = gt_rxheader[1:0];
end
taxi_eth_mac_phy_10g #(
.DATA_W(DATA_W),
.HDR_W(HDR_W),
.TX_GBX_IF_EN(CFG_LOW_LATENCY),
.RX_GBX_IF_EN(CFG_LOW_LATENCY),
.PADDING_EN(PADDING_EN),
.DIC_EN(DIC_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),
@@ -445,9 +562,16 @@ eth_mac_phy_10g_inst (
* Serdes interface
*/
.serdes_tx_data(serdes_tx_data),
.serdes_tx_data_valid(serdes_tx_data_valid),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
.serdes_tx_gbx_req_start(serdes_tx_gbx_req_start),
.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
.serdes_tx_gbx_start(serdes_tx_gbx_start),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_data_valid(serdes_rx_data_valid),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
.serdes_rx_bitslip(serdes_rx_bitslip),
.serdes_rx_reset_req(rx_reset_req),

57
src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv
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@@ -45,7 +45,11 @@ module taxi_eth_phy_25g_us_gt #
parameter logic GT_RX_PD = 1'b0,
parameter logic GT_RX_QPLL_SEL = 1'b0,
parameter logic GT_RX_LPM_EN = 1'b0,
parameter logic GT_RX_POLARITY = 1'b0
parameter logic GT_RX_POLARITY = 1'b0,
// MAC/PHY parameters
parameter DATA_W = 64,
parameter HDR_W = 2
)
(
input wire logic xcvr_ctrl_clk,
@@ -105,13 +109,18 @@ module taxi_eth_phy_25g_us_gt #
/*
* Serdes interface
*/
input wire logic [5:0] gt_txheader,
input wire logic [63:0] gt_txdata,
input wire logic gt_rxgearboxslip,
output wire logic [5:0] gt_rxheader,
output wire logic [1:0] gt_rxheadervalid,
output wire logic [63:0] gt_rxdata,
output wire logic [1:0] gt_rxdatavalid
input wire logic [DATA_W-1:0] serdes_tx_data,
input wire logic serdes_tx_data_valid,
input wire logic [HDR_W-1:0] serdes_tx_hdr,
input wire logic serdes_tx_hdr_valid,
output wire logic serdes_tx_gbx_req_start,
output wire logic serdes_tx_gbx_req_stall,
input wire logic serdes_tx_gbx_start,
output wire logic [DATA_W-1:0] serdes_rx_data,
output wire logic serdes_rx_data_valid,
output wire logic [HDR_W-1:0] serdes_rx_hdr,
output wire logic serdes_rx_hdr_valid,
input wire logic serdes_rx_bitslip
);
localparam GT_USP = FAMILY == "kintexuplus" || FAMILY == "virtexuplus" || FAMILY == "virtexuplusHBM"
@@ -340,6 +349,30 @@ gt_rx_reset_inst (
.rx_lpm_en_in(GT_RX_LPM_EN)
);
wire [6:0] gt_txsequence;
wire [5:0] gt_txheader;
wire [63:0] gt_txdata;
wire gt_rxgearboxslip;
wire [1:0] gt_rxstartofseq;
wire [5:0] gt_rxheader;
wire [1:0] gt_rxheadervalid;
wire [63:0] gt_rxdata;
wire [1:0] gt_rxdatavalid;
assign gt_txdata = serdes_tx_data;
assign gt_txheader = {4'd0, serdes_tx_hdr};
assign gt_rxgearboxslip = serdes_rx_bitslip;
if (!SIM) begin
assign serdes_rx_data = gt_rxdata;
assign serdes_rx_data_valid = gt_rxdatavalid;
assign serdes_rx_hdr = gt_rxheader[1:0];
assign serdes_rx_hdr_valid = gt_rxheadervalid[0];
end
assign serdes_tx_gbx_req_start = 1'b0;
assign serdes_tx_gbx_req_stall = 1'b0;
if (SIM) begin : xcvr
// simulation (no GT core)
@@ -771,8 +804,8 @@ end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr
end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr
// UltraScale/UltraScale+ GTY (channel only)
taxi_eth_phy_25g_us_gty_channel
taxi_eth_phy_25g_us_gty_channel_inst (
taxi_eth_phy_25g_us_gty_ch
taxi_eth_phy_25g_us_gty_ch_inst (
// Common
.gtpowergood_out(xcvr_gtpowergood_out),
@@ -864,8 +897,8 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr
end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr
// UltraScale/UltraScale+ GTY (channel only)
taxi_eth_phy_25g_us_gth_channel
taxi_eth_phy_25g_us_gth_channel_inst (
taxi_eth_phy_25g_us_gth_ch
taxi_eth_phy_25g_us_gth_ch_inst (
// Common
.gtpowergood_out(xcvr_gtpowergood_out),

6
src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.f Normal file
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@@ -0,0 +1,6 @@
taxi_eth_phy_25g_us_gt_ll.sv
../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv
../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv
../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv
../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv
../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv

1127
src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv Normal file
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File diff suppressed because it is too large Load Diff

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
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@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_161.tcl
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@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_322.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_161.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_322.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_161.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config

34
src/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_322.tcl
View File

@@ -35,8 +35,8 @@ if {[string first uplus [get_property FAMILY [get_property PART [current_project
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
}
# channel reset
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
# channel power down
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
# channel clock selection
@@ -91,6 +91,14 @@ proc create_gtwizard_ip {name preset config} {
set_property -dict $config_list $ip
}
# normal latency (async gearbox)
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
dict set config TX_BUFFER_MODE {1}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B_ASYNC}
dict set config RX_BUFFER_MODE {1}
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
@@ -101,4 +109,24 @@ create_gtwizard_ip "${base_name}_full" $preset $config
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_channel" $preset $config
create_gtwizard_ip "${base_name}_ch" $preset $config
# low latency (async gearbox with buffer bypass)
dict set config TX_DATA_ENCODING {64B66B}
dict set config TX_BUFFER_MODE {0}
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
dict set config RX_DATA_DECODING {64B66B}
dict set config RX_BUFFER_MODE {0}
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
# variant with channel and common
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
dict set config LOCATE_COMMON {CORE}
create_gtwizard_ip "${base_name}_ll_full" $preset $config
# variant with channel only
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
create_gtwizard_ip "${base_name}_ll_ch" $preset $config