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eth: Add support for synchronous gearbox to PHY, MAC+PHY, and GT wrappers

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-05-30 21:14:54 -07:00
parent f31ba113d2
commit e4762b7a8c
76 changed files with 3853 additions and 1090 deletions
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58
src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
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@@ -19,6 +19,7 @@ module taxi_eth_phy_10g_tx_if #
(
parameter DATA_W = 64,
parameter HDR_W = 2,
parameter logic GBX_IF_EN = 1'b0,
parameter logic BIT_REVERSE = 1'b0,
parameter logic SCRAMBLER_DISABLE = 1'b0,
parameter logic PRBS31_EN = 1'b0,
@@ -32,13 +33,22 @@ module taxi_eth_phy_10g_tx_if #
* 10GBASE-R encoded interface
*/
input wire logic [DATA_W-1:0] encoded_tx_data,
input wire logic encoded_tx_data_valid = 1'b1,
input wire logic [HDR_W-1:0] encoded_tx_hdr,
input wire logic encoded_tx_hdr_valid = 1'b1,
output wire logic tx_gbx_req_start,
output wire logic tx_gbx_req_stall,
input wire logic tx_gbx_start = 1'b0,
/*
* SERDES interface
*/
output wire logic [DATA_W-1:0] serdes_tx_data,
output wire logic serdes_tx_data_valid,
output wire logic [HDR_W-1:0] serdes_tx_hdr,
output wire logic serdes_tx_hdr_valid,
input wire logic serdes_tx_gbx_req_start = 1'b0,
input wire logic serdes_tx_gbx_req_stall = 1'b0,
output wire logic serdes_tx_gbx_start,
/*
* Configuration
@@ -53,19 +63,25 @@ if (DATA_W != 64)
if (HDR_W != 2)
$fatal(0, "Error: HDR_W must be 2");
assign tx_gbx_req_start = GBX_IF_EN ? serdes_tx_gbx_req_start : '0;
assign tx_gbx_req_stall = GBX_IF_EN ? serdes_tx_gbx_req_stall : '0;
logic [57:0] scrambler_state_reg = '1;
wire [57:0] scrambler_state;
wire [DATA_W-1:0] scrambled_data;
logic [30:0] prbs31_state_reg = 31'h7fffffff;
logic [30:0] prbs31_state_reg = '1;
wire [30:0] prbs31_state;
wire [DATA_W+HDR_W-1:0] prbs31_data;
logic [DATA_W-1:0] serdes_tx_data_reg = '0;
logic serdes_tx_data_valid_reg = 1'b0;
logic [HDR_W-1:0] serdes_tx_hdr_reg = '0;
logic serdes_tx_hdr_valid_reg = 1'b0;
logic serdes_tx_gbx_start_reg = 1'b0;
wire [DATA_W-1:0] serdes_tx_data_int;
wire [HDR_W-1:0] serdes_tx_hdr_int;
wire [HDR_W-1:0] serdes_tx_hdr_int;
if (BIT_REVERSE) begin
for (genvar n = 0; n < DATA_W; n = n + 1) begin
@@ -84,25 +100,43 @@ if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
reg [DATA_W-1:0] serdes_tx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
reg serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_W-1:0] serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg serdes_tx_gbx_start_pipe_reg[SERDES_PIPELINE-1:0];
for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_tx_data_pipe_reg[n] = '0;
serdes_tx_data_valid_pipe_reg[n] = '0;
serdes_tx_hdr_pipe_reg[n] = '0;
serdes_tx_hdr_valid_pipe_reg[n] = '0;
serdes_tx_gbx_start_pipe_reg[n] = '0;
end
always @(posedge clk) begin
serdes_tx_data_pipe_reg[n] <= n == 0 ? serdes_tx_data_int : serdes_tx_data_pipe_reg[n-1];
serdes_tx_data_valid_pipe_reg[n] <= n == 0 ? serdes_tx_data_valid_reg : serdes_tx_data_valid_pipe_reg[n-1];
serdes_tx_hdr_pipe_reg[n] <= n == 0 ? serdes_tx_hdr_int : serdes_tx_hdr_pipe_reg[n-1];
serdes_tx_hdr_valid_pipe_reg[n] <= n == 0 ? serdes_tx_hdr_valid_reg : serdes_tx_hdr_valid_pipe_reg[n-1];
serdes_tx_gbx_start_pipe_reg[n] <= n == 0 ? serdes_tx_gbx_start_reg : serdes_tx_gbx_start_pipe_reg[n-1];
end
end
assign serdes_tx_data = serdes_tx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_tx_data_valid = GBX_IF_EN ? serdes_tx_data_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
assign serdes_tx_hdr = serdes_tx_hdr_pipe_reg[SERDES_PIPELINE-1];
assign serdes_tx_hdr_valid = GBX_IF_EN ? serdes_tx_hdr_valid_pipe_reg[SERDES_PIPELINE-1] : 1'b1;
assign serdes_tx_gbx_start = GBX_IF_EN ? serdes_tx_gbx_start_pipe_reg[SERDES_PIPELINE-1] : 1'b0;
end else begin
assign serdes_tx_data = serdes_tx_data_int;
assign serdes_tx_data_valid = GBX_IF_EN ? serdes_tx_data_valid_reg : 1'b1;
assign serdes_tx_hdr = serdes_tx_hdr_int;
assign serdes_tx_hdr_valid = GBX_IF_EN ? serdes_tx_hdr_valid_reg : 1'b1;
assign serdes_tx_gbx_start = GBX_IF_EN ? serdes_tx_gbx_start_reg : 1'b0;
end
taxi_lfsr #(
@@ -120,6 +154,12 @@ scrambler_inst (
.state_out(scrambler_state)
);
always_ff @(posedge clk) begin
if (!GBX_IF_EN || encoded_tx_data_valid) begin
scrambler_state_reg <= scrambler_state;
end
end
taxi_lfsr #(
.LFSR_W(31),
.LFSR_POLY(31'h10000001),
@@ -136,10 +176,10 @@ prbs31_gen_inst (
);
always_ff @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
if (PRBS31_EN && cfg_tx_prbs31_enable) begin
prbs31_state_reg <= prbs31_state;
if (!GBX_IF_EN || encoded_tx_data_valid) begin
prbs31_state_reg <= prbs31_state;
end
serdes_tx_data_reg <= ~prbs31_data[DATA_W+HDR_W-1:HDR_W];
serdes_tx_hdr_reg <= ~prbs31_data[HDR_W-1:0];
@@ -147,6 +187,10 @@ always_ff @(posedge clk) begin
serdes_tx_data_reg <= SCRAMBLER_DISABLE ? encoded_tx_data : scrambled_data;
serdes_tx_hdr_reg <= encoded_tx_hdr;
end
serdes_tx_data_valid_reg <= encoded_tx_data_valid;
serdes_tx_hdr_valid_reg <= encoded_tx_hdr_valid;
serdes_tx_gbx_start_reg <= tx_gbx_start;
end
endmodule