diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv index 2193317..1d9df17 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv @@ -172,7 +172,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad // PHY parameters .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_qsfp_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv b/src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv index a162fb7..1e7cafc 100644 --- a/src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv +++ b/src/eth/example/AS02MC04/fpga/rtl/fpga_core.sv @@ -173,7 +173,7 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_sfp_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv index db52c2e..dd390f5 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv @@ -343,7 +343,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(eth_gty_axis_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv index 6e3b975..4b98069 100644 --- a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv +++ b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv @@ -424,7 +424,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(eth_gty_axis_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv b/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv index 8055a95..b40dcbc 100644 --- a/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv +++ b/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv @@ -368,7 +368,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(eth_gty_axis_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv b/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv index ff4dd01..dd5061f 100644 --- a/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv +++ b/src/eth/example/KC705/fpga_10g/rtl/fpga_core.sv @@ -516,7 +516,7 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_sfp_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/KCU105/fpga/fpga_10g/config.tcl b/src/eth/example/KCU105/fpga/fpga_10g/config.tcl index fe5171b..51c34b1 100644 --- a/src/eth/example/KCU105/fpga/fpga_10g/config.tcl +++ b/src/eth/example/KCU105/fpga/fpga_10g/config.tcl @@ -12,6 +12,11 @@ set params [dict create] # 0 for 1G, 1 for 10G dict set params SFP_RATE "1" +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "32" + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/src/eth/example/KCU105/fpga/fpga_1g/config.tcl b/src/eth/example/KCU105/fpga/fpga_1g/config.tcl index 168762b..a95092e 100644 --- a/src/eth/example/KCU105/fpga/fpga_1g/config.tcl +++ b/src/eth/example/KCU105/fpga/fpga_1g/config.tcl @@ -12,6 +12,11 @@ set params [dict create] # 0 for 1G, 1 for 10G dict set params SFP_RATE "0" +# 10G MAC configuration +dict set params CFG_LOW_LATENCY "1" +dict set params COMBINED_MAC_PCS "1" +dict set params MAC_DATA_W "16" + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/src/eth/example/KCU105/fpga/rtl/fpga.sv b/src/eth/example/KCU105/fpga/rtl/fpga.sv index 5fbb14a..d54d97a 100644 --- a/src/eth/example/KCU105/fpga/rtl/fpga.sv +++ b/src/eth/example/KCU105/fpga/rtl/fpga.sv @@ -24,7 +24,11 @@ module fpga # // device family parameter string FAMILY = "kintexu", // SFP rate selection (0 for 1G, 1 for 10G) - parameter logic SFP_RATE = 1'b1 + parameter logic SFP_RATE = 1'b1, + // 10G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = SFP_RATE ? 32 : 16 ) ( /* @@ -379,7 +383,10 @@ fpga_core #( .SIM(SIM), .VENDOR(VENDOR), .FAMILY(FAMILY), - .SFP_RATE(SFP_RATE) + .SFP_RATE(SFP_RATE), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), + .MAC_DATA_W(MAC_DATA_W) ) core_inst ( /* diff --git a/src/eth/example/KCU105/fpga/rtl/fpga_core.sv b/src/eth/example/KCU105/fpga/rtl/fpga_core.sv index 5596cd7..95f318d 100644 --- a/src/eth/example/KCU105/fpga/rtl/fpga_core.sv +++ b/src/eth/example/KCU105/fpga/rtl/fpga_core.sv @@ -24,7 +24,11 @@ module fpga_core # // device family parameter string FAMILY = "kintexu", // SFP rate selection (0 for 1G, 1 for 10G) - parameter logic SFP_RATE = 1'b1 + parameter logic SFP_RATE = 1'b1, + // 10G MAC configuration + parameter logic CFG_LOW_LATENCY = 1'b1, + parameter logic COMBINED_MAC_PCS = 1'b1, + parameter MAC_DATA_W = SFP_RATE ? 32 : 16 ) ( /* @@ -328,11 +332,9 @@ wire sfp_mgt_refclk_0_bufg; wire sfp_rst; -localparam SFP_DATA_W = SFP_RATE ? 32 : 16; - -taxi_axis_if #(.DATA_W(SFP_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_tx[2](); +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_tx[2](); taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2](); -taxi_axis_if #(.DATA_W(SFP_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_rx[2](); +taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_sfp_rx[2](); if (SIM) begin @@ -406,12 +408,13 @@ if (SFP_RATE == 0) begin : sfp_mac .CNT(2), // GT config - .CFG_LOW_LATENCY(1), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), // GT type .GT_TYPE("GTH"), // PHY parameters + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .SGMII_EN(1'b1), .AN_EN(1'b1), .DIC_EN(1'b1), @@ -673,12 +676,13 @@ end else begin : sfp_mac .CNT(2), // GT config - .CFG_LOW_LATENCY(1), + .CFG_LOW_LATENCY(CFG_LOW_LATENCY), // GT type .GT_TYPE("GTH"), // PHY parameters + .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_sfp_tx[0].DATA_W), .USXGMII_EN(1'b1), .DIC_EN(1'b1), diff --git a/src/eth/example/KCU105/fpga/tb/fpga_core/Makefile b/src/eth/example/KCU105/fpga/tb/fpga_core/Makefile index b05df5d..4ec8223 100644 --- a/src/eth/example/KCU105/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/KCU105/fpga/tb/fpga_core/Makefile @@ -46,6 +46,9 @@ export PARAM_SIM := "1'b1" export PARAM_VENDOR := "\"XILINX\"" export PARAM_FAMILY := "\"kintexu\"" export PARAM_SFP_RATE := "1'b1" +export PARAM_CFG_LOW_LATENCY := "1'b1" +export PARAM_COMBINED_MAC_PCS := "1'b1" +export PARAM_MAC_DATA_W := "32" ifeq ($(SIM), icarus) PLUSARGS += -fst diff --git a/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py index ce2ab3b..ce18903 100644 --- a/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py @@ -245,8 +245,8 @@ def process_f_files(files): return list(lst.values()) -@pytest.mark.parametrize("sfp_rate", [0, 1]) -def test_fpga_core(request, sfp_rate): +@pytest.mark.parametrize(("sfp_rate", "mac_data_w"), [(0, 16), (1, 32), (1, 64)]) +def test_fpga_core(request, sfp_rate, mac_data_w): dut = "fpga_core" module = os.path.splitext(os.path.basename(__file__))[0] toplevel = dut @@ -274,6 +274,9 @@ def test_fpga_core(request, sfp_rate): parameters['VENDOR'] = "\"XILINX\"" parameters['FAMILY'] = "\"kintexu\"" parameters['SFP_RATE'] = f"1'b{sfp_rate}" + parameters['CFG_LOW_LATENCY'] = "1'b1" + parameters['COMBINED_MAC_PCS'] = "1'b1" + parameters['MAC_DATA_W'] = mac_data_w extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} diff --git a/src/eth/example/KR260/fpga/rtl/fpga_core.sv b/src/eth/example/KR260/fpga/rtl/fpga_core.sv index 0b8c110..e61f625 100644 --- a/src/eth/example/KR260/fpga/rtl/fpga_core.sv +++ b/src/eth/example/KR260/fpga/rtl/fpga_core.sv @@ -416,7 +416,7 @@ end else begin : sfp_mac // PHY parameters .DATA_W(axis_sfp_tx[0].DATA_W), - .USXGMII_EN(axis_sfp_tx[0].DATA_W == 32), + .USXGMII_EN(1'b1), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/NT200A02/fpga/rtl/fpga_core.sv b/src/eth/example/NT200A02/fpga/rtl/fpga_core.sv index 047de64..4bdaaa5 100644 --- a/src/eth/example/NT200A02/fpga/rtl/fpga_core.sv +++ b/src/eth/example/NT200A02/fpga/rtl/fpga_core.sv @@ -201,7 +201,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(eth_gty_axis_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/NT40E3/fpga/rtl/fpga_core.sv b/src/eth/example/NT40E3/fpga/rtl/fpga_core.sv index da93cf8..4c40838 100644 --- a/src/eth/example/NT40E3/fpga/rtl/fpga_core.sv +++ b/src/eth/example/NT40E3/fpga/rtl/fpga_core.sv @@ -158,7 +158,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_sfp_tx[0].DATA_W), - .USXGMII_EN(1'b1), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv b/src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv index e4bcac1..fe90fe2 100644 --- a/src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv +++ b/src/eth/example/NetFPGA_SUME/fpga/rtl/fpga_core.sv @@ -305,7 +305,7 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_sfp_tx[0].DATA_W), - .USXGMII_EN(1'b1), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv b/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv index 6620d15..6c434e4 100644 --- a/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Nexus_K3P_Q/fpga/rtl/fpga_core.sv @@ -191,7 +191,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_qsfp_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv b/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv index 706786c..34ed485 100644 --- a/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Nexus_K3P_S/fpga/rtl/fpga_core.sv @@ -167,7 +167,7 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_sfp_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv b/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv index 886a32d..5d349f9 100644 --- a/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv +++ b/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv @@ -371,7 +371,7 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_qsfp_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/VC709/fpga/rtl/fpga_core.sv b/src/eth/example/VC709/fpga/rtl/fpga_core.sv index e0c9ca5..9f7cd14 100644 --- a/src/eth/example/VC709/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VC709/fpga/rtl/fpga_core.sv @@ -310,7 +310,7 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(MAC_DATA_W), - .USXGMII_EN(1'b1), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/VCU108/fpga/rtl/fpga_core.sv b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv index 116c970..60b8421 100644 --- a/src/eth/example/VCU108/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv @@ -398,7 +398,7 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_qsfp_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/VCU118/fpga/rtl/fpga_core.sv b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv index f48ff21..16fe581 100644 --- a/src/eth/example/VCU118/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv @@ -595,7 +595,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_qsfp_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv index 30f8b38..e3f3678 100644 --- a/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv +++ b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv @@ -322,7 +322,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(eth_gty_axis_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && eth_gty_axis_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/ZCU102/fpga/rtl/fpga.sv b/src/eth/example/ZCU102/fpga/rtl/fpga.sv index 40a9eb2..4289b5d 100644 --- a/src/eth/example/ZCU102/fpga/rtl/fpga.sv +++ b/src/eth/example/ZCU102/fpga/rtl/fpga.sv @@ -28,7 +28,7 @@ module fpga # // 10G MAC configuration parameter logic CFG_LOW_LATENCY = 1'b1, parameter logic COMBINED_MAC_PCS = 1'b1, - parameter MAC_DATA_W = 32 + parameter MAC_DATA_W = SFP_RATE ? 32 : 16 ) ( /* diff --git a/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv index 51ab363..2a9bc33 100644 --- a/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv @@ -28,7 +28,7 @@ module fpga_core # // 10G MAC configuration parameter logic CFG_LOW_LATENCY = 1'b1, parameter logic COMBINED_MAC_PCS = 1'b1, - parameter MAC_DATA_W = 32 + parameter MAC_DATA_W = SFP_RATE ? 32 : 16 ) ( /* @@ -547,7 +547,7 @@ end else begin : sfp_mac // PHY parameters .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_sfp_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/ZCU106/fpga/rtl/fpga.sv b/src/eth/example/ZCU106/fpga/rtl/fpga.sv index c9c2af7..113b6db 100644 --- a/src/eth/example/ZCU106/fpga/rtl/fpga.sv +++ b/src/eth/example/ZCU106/fpga/rtl/fpga.sv @@ -28,7 +28,7 @@ module fpga # // 10G MAC configuration parameter logic CFG_LOW_LATENCY = 1'b1, parameter logic COMBINED_MAC_PCS = 1'b1, - parameter MAC_DATA_W = 32 + parameter MAC_DATA_W = SFP_RATE ? 32 : 16 ) ( /* diff --git a/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv index 36d63b0..c511c0b 100644 --- a/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU106/fpga/rtl/fpga_core.sv @@ -28,7 +28,7 @@ module fpga_core # // 10G MAC configuration parameter logic CFG_LOW_LATENCY = 1'b1, parameter logic COMBINED_MAC_PCS = 1'b1, - parameter MAC_DATA_W = 32 + parameter MAC_DATA_W = SFP_RATE ? 32 : 16 ) ( /* @@ -548,7 +548,7 @@ end else begin : sfp_mac // PHY parameters .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_sfp_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv index 9fbc1ca..eca7d3a 100644 --- a/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU111/fpga/rtl/fpga_core.sv @@ -379,7 +379,7 @@ taxi_eth_mac_25g_us #( // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_sfp_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && axis_sfp_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0), diff --git a/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv index 9b1a765..61cedc6 100644 --- a/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv +++ b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv @@ -219,7 +219,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad // MAC/PHY config .COMBINED_MAC_PCS(COMBINED_MAC_PCS), .DATA_W(axis_qsfp_tx[0].DATA_W), - .USXGMII_EN(COMBINED_MAC_PCS && axis_qsfp_tx[0].DATA_W == 32), + .USXGMII_EN(COMBINED_MAC_PCS), .DIC_EN(1'b1), .PTP_TS_EN(1'b0), .PTP_TD_EN(1'b0),