eth: Add gearbox support to 64-bit 10G MAC

Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-06-13 16:39:55 -07:00
parent 28195390a2
commit e846e7f0cd
18 changed files with 641 additions and 536 deletions

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@@ -35,6 +35,7 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 64
export PARAM_GBX_IF_EN := 0
export PARAM_PTP_TS_EN := 1
export PARAM_PTP_TS_FMT_TOD := 1
export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96)

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@@ -39,6 +39,8 @@ class TB:
self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk)
dut.xgmii_rx_valid.setimmediatevalue(1)
dut.cfg_rx_max_pkt_len.setimmediatevalue(0)
dut.cfg_rx_enable.setimmediatevalue(0)
@@ -306,6 +308,7 @@ def test_taxi_axis_xgmii_rx_64(request):
parameters = {}
parameters['DATA_W'] = 64
parameters['GBX_IF_EN'] = 0
parameters['PTP_TS_EN'] = 1
parameters['PTP_TS_FMT_TOD'] = 1
parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64

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@@ -19,6 +19,7 @@ module test_taxi_axis_xgmii_rx_64 #
(
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 64,
parameter logic GBX_IF_EN = 1'b0,
parameter logic PTP_TS_EN = 1'b0,
parameter logic PTP_TS_FMT_TOD = 1'b1,
parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64
@@ -34,6 +35,7 @@ logic rst;
logic [DATA_W-1:0] xgmii_rxd;
logic [CTRL_W-1:0] xgmii_rxc;
logic xgmii_rx_valid;
taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(USER_W)) m_axis_rx();
@@ -62,6 +64,7 @@ logic stat_rx_err_preamble;
taxi_axis_xgmii_rx_64 #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.GBX_IF_EN(GBX_IF_EN),
.PTP_TS_EN(PTP_TS_EN),
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
.PTP_TS_W(PTP_TS_W)
@@ -75,6 +78,7 @@ uut (
*/
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_rx_valid(xgmii_rx_valid),
/*
* AXI4-Stream output (source)

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@@ -35,6 +35,8 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 64
export PARAM_GBX_IF_EN := 0
export PARAM_GBX_CNT := 1
export PARAM_PADDING_EN := 1
export PARAM_DIC_EN := 1
export PARAM_MIN_FRAME_LEN := 64

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@@ -522,6 +522,8 @@ def test_taxi_axis_xgmii_tx_64(request, enable_dic):
parameters = {}
parameters['DATA_W'] = 64
parameters['GBX_IF_EN'] = 0
parameters['GBX_CNT'] = 1
parameters['PADDING_EN'] = 1
parameters['DIC_EN'] = enable_dic
parameters['MIN_FRAME_LEN'] = 64

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@@ -19,6 +19,7 @@ module test_taxi_axis_xgmii_tx_64 #
(
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 64,
parameter logic GBX_IF_EN = 1'b0,
parameter logic PADDING_EN = 1'b1,
parameter logic DIC_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
@@ -65,6 +66,7 @@ logic stat_tx_err_underflow;
taxi_axis_xgmii_tx_64 #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.GBX_IF_EN(GBX_IF_EN),
.PADDING_EN(PADDING_EN),
.DIC_EN(DIC_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),

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@@ -33,6 +33,9 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 64
export PARAM_TX_GBX_IF_EN := 1
export PARAM_RX_GBX_IF_EN := $(PARAM_TX_GBX_IF_EN)
export PARAM_GBX_CNT := 1
export PARAM_PADDING_EN := 1
export PARAM_DIC_EN := 1
export PARAM_MIN_FRAME_LEN := 64

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@@ -747,6 +747,9 @@ def test_taxi_eth_mac_10g(request, data_w, dic_en, pfc_en):
parameters = {}
parameters['DATA_W'] = data_w
parameters['TX_GBX_IF_EN'] = 0
parameters['RX_GBX_IF_EN'] = parameters['TX_GBX_IF_EN']
parameters['GBX_CNT'] = 1
parameters['PADDING_EN'] = 1
parameters['DIC_EN'] = dic_en
parameters['MIN_FRAME_LEN'] = 64

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@@ -19,6 +19,9 @@ module test_taxi_eth_mac_10g #
(
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 64,
parameter logic TX_GBX_IF_EN = 1'b0,
parameter logic RX_GBX_IF_EN = TX_GBX_IF_EN,
parameter GBX_CNT = 1,
parameter logic PADDING_EN = 1'b1,
parameter logic DIC_EN = 1'b1,
parameter MIN_FRAME_LEN = 64,
@@ -168,6 +171,9 @@ logic cfg_rx_pfc_en;
taxi_eth_mac_10g #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.TX_GBX_IF_EN(TX_GBX_IF_EN),
.RX_GBX_IF_EN(RX_GBX_IF_EN),
.GBX_CNT(GBX_CNT),
.PADDING_EN(PADDING_EN),
.DIC_EN(DIC_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),

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@@ -33,6 +33,9 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W := 64
export PARAM_TX_GBX_IF_EN := 1
export PARAM_RX_GBX_IF_EN := $(PARAM_TX_GBX_IF_EN)
export PARAM_GBX_CNT := 1
export PARAM_AXIS_DATA_W := $(PARAM_DATA_W)
export PARAM_PADDING_EN := 1
export PARAM_DIC_EN := 1

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@@ -347,6 +347,9 @@ def test_taxi_eth_mac_10g_fifo(request, data_w, dic_en):
parameters['DATA_W'] = data_w
parameters['AXIS_DATA_W'] = parameters['DATA_W']
parameters['TX_GBX_IF_EN'] = 0
parameters['RX_GBX_IF_EN'] = parameters['TX_GBX_IF_EN']
parameters['GBX_CNT'] = 1
parameters['PADDING_EN'] = 1
parameters['DIC_EN'] = dic_en
parameters['MIN_FRAME_LEN'] = 64

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@@ -19,6 +19,9 @@ module test_taxi_eth_mac_10g_fifo #
(
/* verilator lint_off WIDTHTRUNC */
parameter DATA_W = 8,
parameter logic TX_GBX_IF_EN = 1'b0,
parameter logic RX_GBX_IF_EN = TX_GBX_IF_EN,
parameter GBX_CNT = 1,
parameter AXIS_DATA_W = 8,
parameter logic PADDING_EN = 1'b1,
parameter logic DIC_EN = 1'b1,
@@ -98,6 +101,9 @@ logic cfg_rx_enable;
taxi_eth_mac_10g_fifo #(
.DATA_W(DATA_W),
.CTRL_W(CTRL_W),
.TX_GBX_IF_EN(TX_GBX_IF_EN),
.RX_GBX_IF_EN(RX_GBX_IF_EN),
.GBX_CNT(GBX_CNT),
.PADDING_EN(PADDING_EN),
.DIC_EN(DIC_EN),
.MIN_FRAME_LEN(MIN_FRAME_LEN),

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@@ -911,7 +911,8 @@ def process_f_files(files):
@pytest.mark.parametrize(("dic_en", "pfc_en"), [(1, 1), (1, 0), (0, 0)])
@pytest.mark.parametrize(("low_latency", "combined_mac_pcs"), [(1, 1), (0, 1), (0, 0)])
@pytest.mark.parametrize("low_latency", [1, 0])
@pytest.mark.parametrize("combined_mac_pcs", [1, 0])
def test_taxi_eth_mac_25g_us(request, combined_mac_pcs, low_latency, dic_en, pfc_en):
dut = "taxi_eth_mac_25g_us"
module = os.path.splitext(os.path.basename(__file__))[0]