diff --git a/README.md b/README.md index e959ee6..2e90d4c 100644 --- a/README.md +++ b/README.md @@ -29,6 +29,7 @@ To facilitate the dual-license model, contributions to the project can only be a * AXI to AXI lite adapter * Register slice * Width converter + * Synchronous FIFO * Single-port RAM * AXI lite * SV interface for AXI lite diff --git a/src/axi/rtl/taxi_axi_fifo.f b/src/axi/rtl/taxi_axi_fifo.f new file mode 100644 index 0000000..6ebb051 --- /dev/null +++ b/src/axi/rtl/taxi_axi_fifo.f @@ -0,0 +1,4 @@ +taxi_axi_fifo.sv +taxi_axi_fifo_wr.sv +taxi_axi_fifo_rd.sv +taxi_axi_if.sv diff --git a/src/axi/rtl/taxi_axi_fifo.sv b/src/axi/rtl/taxi_axi_fifo.sv new file mode 100644 index 0000000..1119fda --- /dev/null +++ b/src/axi/rtl/taxi_axi_fifo.sv @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 FIFO + */ +module taxi_axi_fifo # +( + // Write data FIFO depth (cycles) + parameter WRITE_FIFO_DEPTH = 32, + // Read data FIFO depth (cycles) + parameter READ_FIFO_DEPTH = 32, + // Hold write address until write data in FIFO, if possible + parameter logic WRITE_FIFO_DELAY = 1'b0, + // Hold read address until space available in FIFO for data, if possible + parameter logic READ_FIFO_DELAY = 1'b0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4 slave interface + */ + taxi_axi_if.wr_slv s_axi_wr, + taxi_axi_if.rd_slv s_axi_rd, + + /* + * AXI4 master interface + */ + taxi_axi_if.wr_mst m_axi_wr, + taxi_axi_if.rd_mst m_axi_rd +); + +taxi_axi_fifo_wr #( + .FIFO_DEPTH(WRITE_FIFO_DEPTH), + .FIFO_DELAY(WRITE_FIFO_DELAY) +) +axi_fifo_wr_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4 slave interface + */ + .s_axi_wr(s_axi_wr), + + /* + * AXI4 master interface + */ + .m_axi_wr(m_axi_wr) +); + +taxi_axi_fifo_rd #( + .FIFO_DEPTH(READ_FIFO_DEPTH), + .FIFO_DELAY(READ_FIFO_DELAY) +) +axi_fifo_rd_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI4 slave interface + */ + .s_axi_rd(s_axi_rd), + + /* + * AXI4 master interface + */ + .m_axi_rd(m_axi_rd) +); + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axi_fifo_rd.sv b/src/axi/rtl/taxi_axi_fifo_rd.sv new file mode 100644 index 0000000..5e8dfcb --- /dev/null +++ b/src/axi/rtl/taxi_axi_fifo_rd.sv @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 FIFO (read) + */ +module taxi_axi_fifo_rd # +( + // Read data FIFO depth (cycles) + parameter FIFO_DEPTH = 32, + // Hold read address until space available in FIFO for data, if possible + parameter logic FIFO_DELAY = 1'b0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4 slave interface + */ + taxi_axi_if.rd_slv s_axi_rd, + + /* + * AXI4 master interface + */ + taxi_axi_if.rd_mst m_axi_rd +); + +// extract parameters +localparam DATA_W = s_axi_rd.DATA_W; +localparam ADDR_W = s_axi_rd.ADDR_W; +localparam STRB_W = s_axi_rd.STRB_W; +localparam ID_W = s_axi_rd.ID_W; +localparam logic ARUSER_EN = s_axi_rd.ARUSER_EN && m_axi_rd.ARUSER_EN; +localparam ARUSER_W = s_axi_rd.ARUSER_W; +localparam logic RUSER_EN = s_axi_rd.RUSER_EN && m_axi_rd.RUSER_EN; +localparam RUSER_W = s_axi_rd.RUSER_W; + +localparam LAST_OFFSET = DATA_W; +localparam ID_OFFSET = LAST_OFFSET + 1; +localparam RESP_OFFSET = ID_OFFSET + ID_W; +localparam RUSER_OFFSET = RESP_OFFSET + 2; +localparam RWIDTH = RUSER_OFFSET + (RUSER_EN ? RUSER_W : 0); + +localparam FIFO_AW = $clog2(FIFO_DEPTH); + +if (m_axi_rd.DATA_W != DATA_W) + $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)"); + +if (m_axi_rd.STRB_W != STRB_W) + $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)"); + +reg [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next; +reg [FIFO_AW:0] wr_addr_reg = '0; +reg [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next; +reg [FIFO_AW:0] rd_addr_reg = '0; + +(* ramstyle = "no_rw_check" *) +reg [RWIDTH-1:0] mem[2**FIFO_AW]; +reg [RWIDTH-1:0] mem_read_data_reg; +reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; + +wire [RWIDTH-1:0] m_axi_r; + +reg [RWIDTH-1:0] s_axi_r_reg; +reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next; + +// full when first MSB different but rest same +wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) && + (wr_ptr_reg[FIFO_AW-1:0] == rd_ptr_reg[FIFO_AW-1:0])); +// empty when pointers match exactly +wire empty = wr_ptr_reg == rd_ptr_reg; + +// control signals +reg write; +reg read; +reg store_output; + +assign m_axi_rd.rready = !full; + +assign m_axi_r[DATA_W-1:0] = m_axi_rd.rdata; +assign m_axi_r[LAST_OFFSET] = m_axi_rd.rlast; +assign m_axi_r[ID_OFFSET +: ID_W] = m_axi_rd.rid; +assign m_axi_r[RESP_OFFSET +: 2] = m_axi_rd.rresp; +if (RUSER_EN) assign m_axi_r[RUSER_OFFSET +: RUSER_W] = m_axi_rd.ruser; + +if (FIFO_DELAY) begin + // store AR channel value until there is enough space to store R channel burst in FIFO or FIFO is empty + + localparam COUNT_W = (FIFO_AW > 8 ? FIFO_AW : 8) + 1; + + localparam [0:0] + STATE_IDLE = 1'd0, + STATE_WAIT = 1'd1; + + reg [0:0] state_reg = STATE_IDLE, state_next; + + reg [COUNT_W-1:0] count_reg = 0, count_next; + + reg [ID_W-1:0] m_axi_arid_reg = '0, m_axi_arid_next; + reg [ADDR_W-1:0] m_axi_araddr_reg = '0, m_axi_araddr_next; + reg [7:0] m_axi_arlen_reg = '0, m_axi_arlen_next; + reg [2:0] m_axi_arsize_reg = '0, m_axi_arsize_next; + reg [1:0] m_axi_arburst_reg = '0, m_axi_arburst_next; + reg m_axi_arlock_reg = '0, m_axi_arlock_next; + reg [3:0] m_axi_arcache_reg = '0, m_axi_arcache_next; + reg [2:0] m_axi_arprot_reg = '0, m_axi_arprot_next; + reg [3:0] m_axi_arqos_reg = '0, m_axi_arqos_next; + reg [3:0] m_axi_arregion_reg = '0, m_axi_arregion_next; + reg [ARUSER_W-1:0] m_axi_aruser_reg = '0, m_axi_aruser_next; + reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next; + + reg s_axi_arready_reg = 1'b0, s_axi_arready_next; + + assign m_axi_rd.arid = m_axi_arid_reg; + assign m_axi_rd.araddr = m_axi_araddr_reg; + assign m_axi_rd.arlen = m_axi_arlen_reg; + assign m_axi_rd.arsize = m_axi_arsize_reg; + assign m_axi_rd.arburst = m_axi_arburst_reg; + assign m_axi_rd.arlock = m_axi_arlock_reg; + assign m_axi_rd.arcache = m_axi_arcache_reg; + assign m_axi_rd.arprot = m_axi_arprot_reg; + assign m_axi_rd.arqos = m_axi_arqos_reg; + assign m_axi_rd.arregion = m_axi_arregion_reg; + assign m_axi_rd.aruser = ARUSER_EN ? m_axi_aruser_reg : '0; + assign m_axi_rd.arvalid = m_axi_arvalid_reg; + + assign s_axi_rd.arready = s_axi_arready_reg; + + always_comb begin + state_next = STATE_IDLE; + + count_next = count_reg; + + m_axi_arid_next = m_axi_arid_reg; + m_axi_araddr_next = m_axi_araddr_reg; + m_axi_arlen_next = m_axi_arlen_reg; + m_axi_arsize_next = m_axi_arsize_reg; + m_axi_arburst_next = m_axi_arburst_reg; + m_axi_arlock_next = m_axi_arlock_reg; + m_axi_arcache_next = m_axi_arcache_reg; + m_axi_arprot_next = m_axi_arprot_reg; + m_axi_arqos_next = m_axi_arqos_reg; + m_axi_arregion_next = m_axi_arregion_reg; + m_axi_aruser_next = m_axi_aruser_reg; + m_axi_arvalid_next = m_axi_arvalid_reg && !m_axi_rd.arready; + s_axi_arready_next = s_axi_arready_reg; + + case (state_reg) + STATE_IDLE: begin + s_axi_arready_next = !m_axi_rd.arvalid || m_axi_rd.arready; + + if (s_axi_rd.arready && s_axi_rd.arvalid) begin + s_axi_arready_next = 1'b0; + + m_axi_arid_next = s_axi_rd.arid; + m_axi_araddr_next = s_axi_rd.araddr; + m_axi_arlen_next = s_axi_rd.arlen; + m_axi_arsize_next = s_axi_rd.arsize; + m_axi_arburst_next = s_axi_rd.arburst; + m_axi_arlock_next = s_axi_rd.arlock; + m_axi_arcache_next = s_axi_rd.arcache; + m_axi_arprot_next = s_axi_rd.arprot; + m_axi_arqos_next = s_axi_rd.arqos; + m_axi_arregion_next = s_axi_rd.arregion; + m_axi_aruser_next = s_axi_rd.aruser; + + if (count_reg == 0 || count_reg + m_axi_arlen_next + 1 <= 2**FIFO_AW) begin + count_next = count_reg + m_axi_arlen_next + 1; + m_axi_arvalid_next = 1'b1; + s_axi_arready_next = 1'b0; + state_next = STATE_IDLE; + end else begin + s_axi_arready_next = 1'b0; + state_next = STATE_WAIT; + end + end else begin + state_next = STATE_IDLE; + end + end + STATE_WAIT: begin + s_axi_arready_next = 1'b0; + + if (count_reg == 0 || count_reg + m_axi_arlen_reg + 1 <= 2**FIFO_AW) begin + count_next = count_reg + m_axi_arlen_reg + 1; + m_axi_arvalid_next = 1'b1; + state_next = STATE_IDLE; + end else begin + state_next = STATE_WAIT; + end + end + endcase + + if (s_axi_rd.rready && s_axi_rd.rvalid) begin + count_next = count_next - 1; + end + end + + always_ff @(posedge clk) begin + state_reg <= state_next; + count_reg <= count_next; + + m_axi_arid_reg <= m_axi_arid_next; + m_axi_araddr_reg <= m_axi_araddr_next; + m_axi_arlen_reg <= m_axi_arlen_next; + m_axi_arsize_reg <= m_axi_arsize_next; + m_axi_arburst_reg <= m_axi_arburst_next; + m_axi_arlock_reg <= m_axi_arlock_next; + m_axi_arcache_reg <= m_axi_arcache_next; + m_axi_arprot_reg <= m_axi_arprot_next; + m_axi_arqos_reg <= m_axi_arqos_next; + m_axi_arregion_reg <= m_axi_arregion_next; + m_axi_aruser_reg <= m_axi_aruser_next; + m_axi_arvalid_reg <= m_axi_arvalid_next; + s_axi_arready_reg <= s_axi_arready_next; + + if (rst) begin + state_reg <= STATE_IDLE; + count_reg <= '0; + m_axi_arvalid_reg <= 1'b0; + s_axi_arready_reg <= 1'b0; + end + end + +end else begin + + // bypass AR channel + assign m_axi_rd.arid = s_axi_rd.arid; + assign m_axi_rd.araddr = s_axi_rd.araddr; + assign m_axi_rd.arlen = s_axi_rd.arlen; + assign m_axi_rd.arsize = s_axi_rd.arsize; + assign m_axi_rd.arburst = s_axi_rd.arburst; + assign m_axi_rd.arlock = s_axi_rd.arlock; + assign m_axi_rd.arcache = s_axi_rd.arcache; + assign m_axi_rd.arprot = s_axi_rd.arprot; + assign m_axi_rd.arqos = s_axi_rd.arqos; + assign m_axi_rd.arregion = s_axi_rd.arregion; + assign m_axi_rd.aruser = ARUSER_EN ? s_axi_rd.aruser : '0; + assign m_axi_rd.arvalid = s_axi_rd.arvalid; + assign s_axi_rd.arready = m_axi_rd.arready; + +end + +assign s_axi_rd.rvalid = s_axi_rvalid_reg; + +assign s_axi_rd.rdata = s_axi_r_reg[DATA_W-1:0]; +assign s_axi_rd.rlast = s_axi_r_reg[LAST_OFFSET]; +assign s_axi_rd.rid = s_axi_r_reg[ID_OFFSET +: ID_W]; +assign s_axi_rd.rresp = s_axi_r_reg[RESP_OFFSET +: 2]; +if (RUSER_EN) begin + assign s_axi_rd.ruser = s_axi_r_reg[RUSER_OFFSET +: RUSER_W]; +end else begin + assign s_axi_rd.ruser = '0; +end + +// Write logic +always_comb begin + write = 1'b0; + + wr_ptr_next = wr_ptr_reg; + + if (m_axi_rd.rvalid) begin + // input data valid + if (!full) begin + // not full, perform write + write = 1'b1; + wr_ptr_next = wr_ptr_reg + 1; + end + end +end + +always_ff @(posedge clk) begin + wr_ptr_reg <= wr_ptr_next; + wr_addr_reg <= wr_ptr_next; + + if (write) begin + mem[wr_addr_reg[FIFO_AW-1:0]] <= m_axi_r; + end + + if (rst) begin + wr_ptr_reg <= '0; + end +end + +// Read logic +always_comb begin + read = 1'b0; + + rd_ptr_next = rd_ptr_reg; + + mem_read_data_valid_next = mem_read_data_valid_reg; + + if (store_output || !mem_read_data_valid_reg) begin + // output data not valid OR currently being transferred + if (!empty) begin + // not empty, perform read + read = 1'b1; + mem_read_data_valid_next = 1'b1; + rd_ptr_next = rd_ptr_reg + 1; + end else begin + // empty, invalidate + mem_read_data_valid_next = 1'b0; + end + end +end + +always_ff @(posedge clk) begin + rd_ptr_reg <= rd_ptr_next; + rd_addr_reg <= rd_ptr_next; + + mem_read_data_valid_reg <= mem_read_data_valid_next; + + if (read) begin + mem_read_data_reg <= mem[rd_addr_reg[FIFO_AW-1:0]]; + end + + if (rst) begin + rd_ptr_reg <= '0; + mem_read_data_valid_reg <= 1'b0; + end +end + +// Output register +always_comb begin + store_output = 1'b0; + + s_axi_rvalid_next = s_axi_rvalid_reg; + + if (s_axi_rd.rready || !s_axi_rd.rvalid) begin + store_output = 1'b1; + s_axi_rvalid_next = mem_read_data_valid_reg; + end +end + +always_ff @(posedge clk) begin + s_axi_rvalid_reg <= s_axi_rvalid_next; + + if (store_output) begin + s_axi_r_reg <= mem_read_data_reg; + end + + if (rst) begin + s_axi_rvalid_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/src/axi/rtl/taxi_axi_fifo_wr.sv b/src/axi/rtl/taxi_axi_fifo_wr.sv new file mode 100644 index 0000000..8bb7d1d --- /dev/null +++ b/src/axi/rtl/taxi_axi_fifo_wr.sv @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2018-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 FIFO (write) + */ +module taxi_axi_fifo_wr # +( + // Write data FIFO depth (cycles) + parameter FIFO_DEPTH = 32, + // Hold write address until write data in FIFO, if possible + parameter logic FIFO_DELAY = 1'b0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * AXI4 slave interface + */ + taxi_axi_if.wr_slv s_axi_wr, + + /* + * AXI4 master interface + */ + taxi_axi_if.wr_mst m_axi_wr +); + +// extract parameters +localparam DATA_W = s_axi_wr.DATA_W; +localparam ADDR_W = s_axi_wr.ADDR_W; +localparam STRB_W = s_axi_wr.STRB_W; +localparam ID_W = s_axi_wr.ID_W; +localparam logic AWUSER_EN = s_axi_wr.AWUSER_EN && m_axi_wr.AWUSER_EN; +localparam AWUSER_W = s_axi_wr.AWUSER_W; +localparam logic WUSER_EN = s_axi_wr.WUSER_EN && m_axi_wr.WUSER_EN; +localparam WUSER_W = s_axi_wr.WUSER_W; +localparam logic BUSER_EN = s_axi_wr.BUSER_EN && m_axi_wr.BUSER_EN; +localparam BUSER_W = s_axi_wr.BUSER_W; + +localparam STRB_OFFSET = DATA_W; +localparam LAST_OFFSET = STRB_OFFSET + STRB_W; +localparam WUSER_OFFSET = LAST_OFFSET + 1; +localparam WWIDTH = WUSER_OFFSET + (WUSER_EN ? WUSER_W : 0); + +localparam FIFO_AW = $clog2(FIFO_DEPTH); + +if (m_axi_wr.DATA_W != DATA_W) + $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)"); + +if (m_axi_wr.STRB_W != STRB_W) + $fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)"); + +reg [FIFO_AW:0] wr_ptr_reg = '0, wr_ptr_next; +reg [FIFO_AW:0] wr_addr_reg = '0; +reg [FIFO_AW:0] rd_ptr_reg = '0, rd_ptr_next; +reg [FIFO_AW:0] rd_addr_reg = '0; + +(* ramstyle = "no_rw_check" *) +reg [WWIDTH-1:0] mem[2**FIFO_AW]; +reg [WWIDTH-1:0] mem_read_data_reg; +reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; + +wire [WWIDTH-1:0] s_axi_w; + +reg [WWIDTH-1:0] m_axi_w_reg; +reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next; + +// full when first MSB different but rest same +wire full = ((wr_ptr_reg[FIFO_AW] != rd_ptr_reg[FIFO_AW]) && + (wr_ptr_reg[FIFO_AW-1:0] == rd_ptr_reg[FIFO_AW-1:0])); +// empty when pointers match exactly +wire empty = wr_ptr_reg == rd_ptr_reg; + +wire hold; + +// control signals +reg write; +reg read; +reg store_output; + +assign s_axi_wr.wready = !full && !hold; +assign s_axi_w[DATA_W-1:0] = s_axi_wr.wdata; +assign s_axi_w[STRB_OFFSET +: STRB_W] = s_axi_wr.wstrb; +assign s_axi_w[LAST_OFFSET] = s_axi_wr.wlast; +if (WUSER_EN) assign s_axi_w[WUSER_OFFSET +: WUSER_W] = s_axi_wr.wuser; + +if (FIFO_DELAY) begin + // store AW channel value until W channel burst is stored in FIFO or FIFO is full + + localparam [1:0] + STATE_IDLE = 2'd0, + STATE_TRANSFER_IN = 2'd1, + STATE_TRANSFER_OUT = 2'd2; + + reg [1:0] state_reg = STATE_IDLE, state_next; + + reg hold_reg = 1'b1, hold_next; + reg [8:0] count_reg = 9'd0, count_next; + + reg [ID_W-1:0] m_axi_awid_reg = '0, m_axi_awid_next; + reg [ADDR_W-1:0] m_axi_awaddr_reg = '0, m_axi_awaddr_next; + reg [7:0] m_axi_awlen_reg = '0, m_axi_awlen_next; + reg [2:0] m_axi_awsize_reg = '0, m_axi_awsize_next; + reg [1:0] m_axi_awburst_reg = '0, m_axi_awburst_next; + reg m_axi_awlock_reg = '0, m_axi_awlock_next; + reg [3:0] m_axi_awcache_reg = '0, m_axi_awcache_next; + reg [2:0] m_axi_awprot_reg = '0, m_axi_awprot_next; + reg [3:0] m_axi_awqos_reg = '0, m_axi_awqos_next; + reg [3:0] m_axi_awregion_reg = '0, m_axi_awregion_next; + reg [AWUSER_W-1:0] m_axi_awuser_reg = '0, m_axi_awuser_next; + reg m_axi_awvalid_reg = 1'b0, m_axi_awvalid_next; + + reg s_axi_awready_reg = 1'b0, s_axi_awready_next; + + assign m_axi_wr.awid = m_axi_awid_reg; + assign m_axi_wr.awaddr = m_axi_awaddr_reg; + assign m_axi_wr.awlen = m_axi_awlen_reg; + assign m_axi_wr.awsize = m_axi_awsize_reg; + assign m_axi_wr.awburst = m_axi_awburst_reg; + assign m_axi_wr.awlock = m_axi_awlock_reg; + assign m_axi_wr.awcache = m_axi_awcache_reg; + assign m_axi_wr.awprot = m_axi_awprot_reg; + assign m_axi_wr.awqos = m_axi_awqos_reg; + assign m_axi_wr.awregion = m_axi_awregion_reg; + assign m_axi_wr.awuser = AWUSER_EN ? m_axi_awuser_reg : '0; + assign m_axi_wr.awvalid = m_axi_awvalid_reg; + + assign s_axi_wr.awready = s_axi_awready_reg; + + assign hold = hold_reg; + + always_comb begin + state_next = STATE_IDLE; + + hold_next = hold_reg; + count_next = count_reg; + + m_axi_awid_next = m_axi_awid_reg; + m_axi_awaddr_next = m_axi_awaddr_reg; + m_axi_awlen_next = m_axi_awlen_reg; + m_axi_awsize_next = m_axi_awsize_reg; + m_axi_awburst_next = m_axi_awburst_reg; + m_axi_awlock_next = m_axi_awlock_reg; + m_axi_awcache_next = m_axi_awcache_reg; + m_axi_awprot_next = m_axi_awprot_reg; + m_axi_awqos_next = m_axi_awqos_reg; + m_axi_awregion_next = m_axi_awregion_reg; + m_axi_awuser_next = m_axi_awuser_reg; + m_axi_awvalid_next = m_axi_awvalid_reg && !m_axi_wr.awready; + s_axi_awready_next = s_axi_awready_reg; + + case (state_reg) + STATE_IDLE: begin + s_axi_awready_next = !m_axi_wr.awvalid || m_axi_wr.awready; + hold_next = 1'b1; + + if (s_axi_wr.awready && s_axi_wr.awvalid) begin + s_axi_awready_next = 1'b0; + + m_axi_awid_next = s_axi_wr.awid; + m_axi_awaddr_next = s_axi_wr.awaddr; + m_axi_awlen_next = s_axi_wr.awlen; + m_axi_awsize_next = s_axi_wr.awsize; + m_axi_awburst_next = s_axi_wr.awburst; + m_axi_awlock_next = s_axi_wr.awlock; + m_axi_awcache_next = s_axi_wr.awcache; + m_axi_awprot_next = s_axi_wr.awprot; + m_axi_awqos_next = s_axi_wr.awqos; + m_axi_awregion_next = s_axi_wr.awregion; + m_axi_awuser_next = s_axi_wr.awuser; + + hold_next = 1'b0; + count_next = 0; + state_next = STATE_TRANSFER_IN; + end else begin + state_next = STATE_IDLE; + end + end + STATE_TRANSFER_IN: begin + s_axi_awready_next = 1'b0; + hold_next = 1'b0; + + if (s_axi_wr.wready && s_axi_wr.wvalid) begin + count_next = count_reg + 1; + if (s_axi_wr.wlast) begin + m_axi_awvalid_next = 1'b1; + hold_next = 1'b1; + state_next = STATE_IDLE; + end else if (FIFO_AW < 8 && count_next == 2**FIFO_AW) begin + m_axi_awvalid_next = 1'b1; + state_next = STATE_TRANSFER_OUT; + end else begin + state_next = STATE_TRANSFER_IN; + end + end else begin + state_next = STATE_TRANSFER_IN; + end + end + STATE_TRANSFER_OUT: begin + s_axi_awready_next = 1'b0; + hold_next = 1'b0; + + if (s_axi.wready && s_axi.wvalid) begin + if (s_axi.wlast) begin + hold_next = 1'b1; + state_next = STATE_IDLE; + end else begin + state_next = STATE_TRANSFER_OUT; + end + end else begin + state_next = STATE_TRANSFER_OUT; + end + end + default: begin + state_next = STATE_IDLE; + end + endcase + end + + always_ff @(posedge clk) begin + state_reg <= state_next; + + hold_reg <= hold_next; + count_reg <= count_next; + + m_axi_awid_reg <= m_axi_awid_next; + m_axi_awaddr_reg <= m_axi_awaddr_next; + m_axi_awlen_reg <= m_axi_awlen_next; + m_axi_awsize_reg <= m_axi_awsize_next; + m_axi_awburst_reg <= m_axi_awburst_next; + m_axi_awlock_reg <= m_axi_awlock_next; + m_axi_awcache_reg <= m_axi_awcache_next; + m_axi_awprot_reg <= m_axi_awprot_next; + m_axi_awqos_reg <= m_axi_awqos_next; + m_axi_awregion_reg <= m_axi_awregion_next; + m_axi_awuser_reg <= m_axi_awuser_next; + m_axi_awvalid_reg <= m_axi_awvalid_next; + s_axi_awready_reg <= s_axi_awready_next; + + if (rst) begin + state_reg <= STATE_IDLE; + hold_reg <= 1'b1; + m_axi_awvalid_reg <= 1'b0; + s_axi_awready_reg <= 1'b0; + end + end + +end else begin + + // bypass AW channel + assign m_axi_wr.awid = s_axi_wr.awid; + assign m_axi_wr.awaddr = s_axi_wr.awaddr; + assign m_axi_wr.awlen = s_axi_wr.awlen; + assign m_axi_wr.awsize = s_axi_wr.awsize; + assign m_axi_wr.awburst = s_axi_wr.awburst; + assign m_axi_wr.awlock = s_axi_wr.awlock; + assign m_axi_wr.awcache = s_axi_wr.awcache; + assign m_axi_wr.awprot = s_axi_wr.awprot; + assign m_axi_wr.awqos = s_axi_wr.awqos; + assign m_axi_wr.awregion = s_axi_wr.awregion; + assign m_axi_wr.awuser = AWUSER_EN ? s_axi_wr.awuser : '0; + assign m_axi_wr.awvalid = s_axi_wr.awvalid; + assign s_axi_wr.awready = m_axi_wr.awready; + + assign hold = 1'b0; + +end + +// bypass B channel +assign s_axi_wr.bid = m_axi_wr.bid; +assign s_axi_wr.bresp = m_axi_wr.bresp; +if (BUSER_EN) begin + assign s_axi_wr.buser = m_axi_wr.buser; +end else begin + assign s_axi_wr.buser = '0; +end +assign s_axi_wr.bvalid = m_axi_wr.bvalid; +assign m_axi_wr.bready = s_axi_wr.bready; + +assign m_axi_wr.wvalid = m_axi_wvalid_reg; + +assign m_axi_wr.wdata = m_axi_w_reg[DATA_W-1:0]; +assign m_axi_wr.wstrb = m_axi_w_reg[STRB_OFFSET +: STRB_W]; +assign m_axi_wr.wlast = m_axi_w_reg[LAST_OFFSET]; +if (WUSER_EN) begin + assign m_axi_wr.wuser = m_axi_w_reg[WUSER_OFFSET +: WUSER_W]; +end else begin + assign m_axi_wr.wuser = '0; +end + +// Write logic +always_comb begin + write = 1'b0; + + wr_ptr_next = wr_ptr_reg; + + if (s_axi_wr.wvalid) begin + // input data valid + if (!full && !hold) begin + // not full, perform write + write = 1'b1; + wr_ptr_next = wr_ptr_reg + 1; + end + end +end + +always_ff @(posedge clk) begin + wr_ptr_reg <= wr_ptr_next; + wr_addr_reg <= wr_ptr_next; + + if (write) begin + mem[wr_addr_reg[FIFO_AW-1:0]] <= s_axi_w; + end + + if (rst) begin + wr_ptr_reg <= '0; + end +end + +// Read logic +always_comb begin + read = 1'b0; + + rd_ptr_next = rd_ptr_reg; + + mem_read_data_valid_next = mem_read_data_valid_reg; + + if (store_output || !mem_read_data_valid_reg) begin + // output data not valid OR currently being transferred + if (!empty) begin + // not empty, perform read + read = 1'b1; + mem_read_data_valid_next = 1'b1; + rd_ptr_next = rd_ptr_reg + 1; + end else begin + // empty, invalidate + mem_read_data_valid_next = 1'b0; + end + end +end + +always_ff @(posedge clk) begin + rd_ptr_reg <= rd_ptr_next; + rd_addr_reg <= rd_ptr_next; + + mem_read_data_valid_reg <= mem_read_data_valid_next; + + if (read) begin + mem_read_data_reg <= mem[rd_addr_reg[FIFO_AW-1:0]]; + end + + if (rst) begin + rd_ptr_reg <= '0; + mem_read_data_valid_reg <= 1'b0; + end +end + +// Output register +always_comb begin + store_output = 1'b0; + + m_axi_wvalid_next = m_axi_wvalid_reg; + + if (m_axi_wr.wready || !m_axi_wr.wvalid) begin + store_output = 1'b1; + m_axi_wvalid_next = mem_read_data_valid_reg; + end +end + +always_ff @(posedge clk) begin + m_axi_wvalid_reg <= m_axi_wvalid_next; + + if (store_output) begin + m_axi_w_reg <= mem_read_data_reg; + end + + if (rst) begin + m_axi_wvalid_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/src/axi/tb/taxi_axi_fifo/Makefile b/src/axi/tb/taxi_axi_fifo/Makefile new file mode 100644 index 0000000..2a85b98 --- /dev/null +++ b/src/axi/tb/taxi_axi_fifo/Makefile @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = taxi_axi_fifo +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_ADDR_W := 32 +export PARAM_DATA_W := 32 +export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 ) +export PARAM_ID_W := 8 +export PARAM_AWUSER_EN := 0 +export PARAM_AWUSER_W := 1 +export PARAM_WUSER_EN := 0 +export PARAM_WUSER_W := 1 +export PARAM_BUSER_EN := 0 +export PARAM_BUSER_W := 1 +export PARAM_ARUSER_EN := 0 +export PARAM_ARUSER_W := 1 +export PARAM_RUSER_EN := 0 +export PARAM_RUSER_W := 1 +export PARAM_WRITE_FIFO_DEPTH := 32 +export PARAM_READ_FIFO_DEPTH := 32 +export PARAM_WRITE_FIFO_DELAY := 0 +export PARAM_READ_FIFO_DELAY := 0 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += -Wno-WIDTH + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/axi/tb/taxi_axi_fifo/test_taxi_axi_fifo.py b/src/axi/tb/taxi_axi_fifo/test_taxi_axi_fifo.py new file mode 100644 index 0000000..719eb3b --- /dev/null +++ b/src/axi/tb/taxi_axi_fifo/test_taxi_axi_fifo.py @@ -0,0 +1,263 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import random + +import cocotb_test.simulator +import pytest + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import AxiBus, AxiMaster, AxiRam + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) + + self.axi_master = AxiMaster(AxiBus.from_entity(dut.s_axi), dut.clk, dut.rst) + self.axi_ram = AxiRam(AxiBus.from_entity(dut.m_axi), dut.clk, dut.rst, size=2**16) + + def set_idle_generator(self, generator=None): + if generator: + self.axi_master.write_if.aw_channel.set_pause_generator(generator()) + self.axi_master.write_if.w_channel.set_pause_generator(generator()) + self.axi_master.read_if.ar_channel.set_pause_generator(generator()) + self.axi_ram.write_if.b_channel.set_pause_generator(generator()) + self.axi_ram.read_if.r_channel.set_pause_generator(generator()) + + def set_backpressure_generator(self, generator=None): + if generator: + self.axi_master.write_if.b_channel.set_pause_generator(generator()) + self.axi_master.read_if.r_channel.set_pause_generator(generator()) + self.axi_ram.write_if.aw_channel.set_pause_generator(generator()) + self.axi_ram.write_if.w_channel.set_pause_generator(generator()) + self.axi_ram.read_if.ar_channel.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None): + + tb = TB(dut) + + byte_lanes = tb.axi_master.write_if.byte_lanes + max_burst_size = tb.axi_master.write_if.max_burst_size + + if size is None: + size = max_burst_size + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in list(range(1, byte_lanes*2))+[1024]: + for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)): + tb.log.info("length %d, offset %d", length, offset) + addr = offset+0x1000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.axi_ram.write(addr-128, b'\xaa'*(length+256)) + + await tb.axi_master.write(addr, test_data, size=size) + + tb.log.debug("%s", tb.axi_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48)) + + assert tb.axi_ram.read(addr, length) == test_data + assert tb.axi_ram.read(addr-1, 1) == b'\xaa' + assert tb.axi_ram.read(addr+length, 1) == b'\xaa' + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None): + + tb = TB(dut) + + byte_lanes = tb.axi_master.write_if.byte_lanes + max_burst_size = tb.axi_master.write_if.max_burst_size + + if size is None: + size = max_burst_size + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + for length in list(range(1, byte_lanes*2))+[1024]: + for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)): + tb.log.info("length %d, offset %d", length, offset) + addr = offset+0x1000 + test_data = bytearray([x % 256 for x in range(length)]) + + tb.axi_ram.write(addr, test_data) + + data = await tb.axi_master.read(addr, length, size=size) + + assert data.data == test_data + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + tb.set_backpressure_generator(backpressure_inserter) + + async def worker(master, offset, aperture, count=16): + for k in range(count): + + length = random.randint(1, min(512, aperture)) + addr = offset+random.randint(0, aperture-length) + test_data = bytearray([x % 256 for x in range(length)]) + + await Timer(random.randint(1, 100), 'ns') + + await master.write(addr, test_data) + + await Timer(random.randint(1, 100), 'ns') + + data = await master.read(addr, length) + assert data.data == test_data + + workers = [] + + for k in range(16): + workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16))) + + while workers: + await workers.pop(0).join() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if cocotb.SIM_NAME: + + data_width = len(cocotb.top.s_axi.wdata) + byte_lanes = data_width // 8 + max_burst_size = (byte_lanes-1).bit_length() + + for test in [run_test_write, run_test_read]: + + factory = TestFactory(test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.add_option("backpressure_inserter", [None, cycle_pause]) + factory.add_option("size", [None]+list(range(max_burst_size))) + factory.generate_tests() + + factory = TestFactory(run_stress_test) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize("delay", [0, 1]) +@pytest.mark.parametrize("data_w", [8, 16, 32]) +def test_taxi_axi_fifo(request, data_w, delay): + dut = "taxi_axi_fifo" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.f"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['DATA_W'] = data_w + parameters['ADDR_W'] = 32 + parameters['STRB_W'] = parameters['DATA_W'] // 8 + parameters['ID_W'] = 8 + parameters['AWUSER_EN'] = 0 + parameters['AWUSER_W'] = 1 + parameters['WUSER_EN'] = 0 + parameters['WUSER_W'] = 1 + parameters['BUSER_EN'] = 0 + parameters['BUSER_W'] = 1 + parameters['ARUSER_EN'] = 0 + parameters['ARUSER_W'] = 1 + parameters['RUSER_EN'] = 0 + parameters['RUSER_W'] = 1 + parameters['WRITE_FIFO_DEPTH'] = 32 + parameters['READ_FIFO_DEPTH'] = 32 + parameters['WRITE_FIFO_DELAY'] = delay + parameters['READ_FIFO_DELAY'] = delay + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/axi/tb/taxi_axi_fifo/test_taxi_axi_fifo.sv b/src/axi/tb/taxi_axi_fifo/test_taxi_axi_fifo.sv new file mode 100644 index 0000000..f65728e --- /dev/null +++ b/src/axi/tb/taxi_axi_fifo/test_taxi_axi_fifo.sv @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4 FIFO testbench + */ +module test_taxi_axi_fifo # +( + /* verilator lint_off WIDTHTRUNC */ + parameter ADDR_W = 32, + parameter DATA_W = 32, + parameter STRB_W = (DATA_W/8), + parameter ID_W = 8, + parameter logic AWUSER_EN = 1'b0, + parameter AWUSER_W = 1, + parameter logic WUSER_EN = 1'b0, + parameter WUSER_W = 1, + parameter logic BUSER_EN = 1'b0, + parameter BUSER_W = 1, + parameter logic ARUSER_EN = 1'b0, + parameter ARUSER_W = 1, + parameter logic RUSER_EN = 1'b0, + parameter RUSER_W = 1, + parameter WRITE_FIFO_DEPTH = 32, + parameter READ_FIFO_DEPTH = 32, + parameter logic WRITE_FIFO_DELAY = 1'b0, + parameter logic READ_FIFO_DELAY = 1'b0 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +logic clk; +logic rst; + +taxi_axi_if #( + .DATA_W(DATA_W), + .ADDR_W(ADDR_W), + .STRB_W(STRB_W), + .ID_W(ID_W), + .AWUSER_EN(AWUSER_EN), + .AWUSER_W(AWUSER_W), + .WUSER_EN(WUSER_EN), + .WUSER_W(WUSER_W), + .BUSER_EN(BUSER_EN), + .BUSER_W(BUSER_W), + .ARUSER_EN(ARUSER_EN), + .ARUSER_W(ARUSER_W), + .RUSER_EN(RUSER_EN), + .RUSER_W(RUSER_W) +) s_axi(), m_axi(); + +taxi_axi_fifo #( + .WRITE_FIFO_DEPTH(WRITE_FIFO_DEPTH), + .READ_FIFO_DEPTH(READ_FIFO_DEPTH), + .WRITE_FIFO_DELAY(WRITE_FIFO_DELAY), + .READ_FIFO_DELAY(READ_FIFO_DELAY) +) +uut ( + .clk(clk), + .rst(rst), + + /* + * AXI4 slave interface + */ + .s_axi_wr(s_axi), + .s_axi_rd(s_axi), + + /* + * AXI4 master interface + */ + .m_axi_wr(m_axi), + .m_axi_rd(m_axi) +); + +endmodule + +`resetall