axis: Normalize unpacked dimension

Signed-off-by: Alex Forencich <alex@alexforencich.com>

rtl/axis/taxi_axis_async_fifo.sv

@@ -200,7 +200,7 @@ wire s_rst_sync;
 wire m_rst_sync;
 
 (* ramstyle = "no_rw_check" *)
-logic [WIDTH-1:0] mem[(2**FIFO_AW)-1:0];
+logic [WIDTH-1:0] mem[2**FIFO_AW];
 logic mem_read_data_valid_reg = 1'b0;
 
 (* shreg_extract = "no" *)
@@ -732,19 +732,19 @@ end else begin : output_fifo
     wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
 
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [DATA_W-1:0] out_fifo_tdata[2**OUTPUT_FIFO_AW-1:0];
+    logic [DATA_W-1:0] out_fifo_tdata[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [KEEP_W-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_AW-1:0];
+    logic [KEEP_W-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [KEEP_W-1:0] out_fifo_tstrb[2**OUTPUT_FIFO_AW-1:0];
+    logic [KEEP_W-1:0] out_fifo_tstrb[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic              out_fifo_tlast[2**OUTPUT_FIFO_AW-1:0];
+    logic              out_fifo_tlast[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [ID_W-1:0]   out_fifo_tid[2**OUTPUT_FIFO_AW-1:0];
+    logic [ID_W-1:0]   out_fifo_tid[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [DEST_W-1:0] out_fifo_tdest[2**OUTPUT_FIFO_AW-1:0];
+    logic [DEST_W-1:0] out_fifo_tdest[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [USER_W-1:0] out_fifo_tuser[2**OUTPUT_FIFO_AW-1:0];
+    logic [USER_W-1:0] out_fifo_tuser[2**OUTPUT_FIFO_AW];
 
     assign pipe_ready = !out_fifo_half_full_reg;
 

rtl/axis/taxi_axis_broadcast.sv

@@ -32,7 +32,7 @@ module taxi_axis_broadcast #
     /*
      * AXI4-Stream outputs (sources)
      */
-    taxi_axis_if.src   m_axis[M_COUNT-1:0]
+    taxi_axis_if.src   m_axis[M_COUNT]
 );
 
 // extract parameters

rtl/axis/taxi_axis_fifo.sv

@@ -143,7 +143,7 @@ logic [FIFO_AW:0] wr_ptr_commit_reg = '0;
 logic [FIFO_AW:0] rd_ptr_reg = '0;
 
 (* ramstyle = "no_rw_check" *)
-logic [WIDTH-1:0] mem[(2**FIFO_AW)-1:0];
+logic [WIDTH-1:0] mem[2**FIFO_AW];
 
 (* shreg_extract = "no" *)
 logic [WIDTH-1:0] mem_rd_data_pipe_reg[RAM_PIPELINE+1-1:0];
@@ -428,19 +428,19 @@ end else begin : output_fifo
     wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
 
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [DATA_W-1:0] out_fifo_tdata[2**OUTPUT_FIFO_AW-1:0];
+    logic [DATA_W-1:0] out_fifo_tdata[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [KEEP_W-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_AW-1:0];
+    logic [KEEP_W-1:0] out_fifo_tkeep[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [KEEP_W-1:0] out_fifo_tstrb[2**OUTPUT_FIFO_AW-1:0];
+    logic [KEEP_W-1:0] out_fifo_tstrb[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic              out_fifo_tlast[2**OUTPUT_FIFO_AW-1:0];
+    logic              out_fifo_tlast[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [ID_W-1:0]   out_fifo_tid[2**OUTPUT_FIFO_AW-1:0];
+    logic [ID_W-1:0]   out_fifo_tid[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [DEST_W-1:0] out_fifo_tdest[2**OUTPUT_FIFO_AW-1:0];
+    logic [DEST_W-1:0] out_fifo_tdest[2**OUTPUT_FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [USER_W-1:0] out_fifo_tuser[2**OUTPUT_FIFO_AW-1:0];
+    logic [USER_W-1:0] out_fifo_tuser[2**OUTPUT_FIFO_AW];
 
     assign pipe_ready = !out_fifo_half_full_reg;
 

rtl/axis/taxi_axis_pipeline_fifo.sv

@@ -147,17 +147,17 @@ if (LENGTH > 0) begin : fifo
     wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
 
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [DATA_W-1:0] out_fifo_tdata[2**FIFO_AW-1:0];
+    logic [DATA_W-1:0] out_fifo_tdata[2**FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [KEEP_W-1:0] out_fifo_tkeep[2**FIFO_AW-1:0];
+    logic [KEEP_W-1:0] out_fifo_tkeep[2**FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic              out_fifo_tlast[2**FIFO_AW-1:0];
+    logic              out_fifo_tlast[2**FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [ID_W-1:0]   out_fifo_tid[2**FIFO_AW-1:0];
+    logic [ID_W-1:0]   out_fifo_tid[2**FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [DEST_W-1:0] out_fifo_tdest[2**FIFO_AW-1:0];
+    logic [DEST_W-1:0] out_fifo_tdest[2**FIFO_AW];
     (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
-    logic [USER_W-1:0] out_fifo_tuser[2**FIFO_AW-1:0];
+    logic [USER_W-1:0] out_fifo_tuser[2**FIFO_AW];
 
     assign m_axis_tready_int = !out_fifo_half_full_reg;