bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-09 17:08:38 -08:00
Code Issues Packages Projects Releases Wiki Activity

lss: Implement fractional baud rate generation for UART

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-11 23:49:39 -07:00
parent 1c686391ab
commit ebeadee172
19 changed files with 86 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
example/Arty/fpga/rtl/fpga_core.sv
View File

@@ -81,7 +81,7 @@ assign phy_reset_n = !rst;
taxi_axis_if #(.DATA_W(8)) axis_uart();
taxi_uart
uut (
uart_inst (
.clk(clk),
.rst(rst),
@@ -112,7 +112,7 @@ uut (
/*
* Configuration
*/
.prescale(16'(125000000/115200/8))
.prescale(16'(125000000/115200))
);
taxi_axis_if #(.DATA_W(8), .ID_W(8)) axis_eth();