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lss: Implement fractional baud rate generation for UART

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-11 23:49:39 -07:00
parent 1c686391ab
commit ebeadee172
19 changed files with 86 additions and 57 deletions
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30
rtl/lss/taxi_uart.sv
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@@ -15,45 +15,49 @@ Authors:
/*
* AXI4-Stream UART
*/
module taxi_uart
module taxi_uart #(
parameter PRE_W = 16
)
(
input wire logic clk,
input wire logic rst,
input wire logic clk,
input wire logic rst,
/*
* AXI4-Stream input (sink)
*/
taxi_axis_if.snk s_axis_tx,
taxi_axis_if.snk s_axis_tx,
/*
* AXI4-Stream output (source)
*/
taxi_axis_if.src m_axis_rx,
taxi_axis_if.src m_axis_rx,
/*
* UART interface
*/
input wire logic rxd,
output wire logic txd,
input wire logic rxd,
output wire logic txd,
/*
* Status
*/
output wire logic tx_busy,
output wire logic rx_busy,
output wire logic rx_overrun_error,
output wire logic rx_frame_error,
output wire logic tx_busy,
output wire logic rx_busy,
output wire logic rx_overrun_error,
output wire logic rx_frame_error,
/*
* Configuration
*/
input wire logic [15:0] prescale
input wire logic [PRE_W-1:0] prescale
);
wire baud_clk;
taxi_uart_brg
taxi_uart_brg #(
.PRE_W(PRE_W)
)
uart_brg_inst (
.clk(clk),
.rst(rst),

33
rtl/lss/taxi_uart_brg.sv
View File

@@ -15,39 +15,52 @@ Authors:
/*
* AXI4-Stream UART baud rate generator
*/
module taxi_uart_brg
module taxi_uart_brg #(
parameter PRE_W = 16
)
(
input wire logic clk,
input wire logic rst,
input wire logic clk,
input wire logic rst,
/*
* Baud rate pulse out
*/
output wire logic baud_clk,
output wire logic baud_clk,
/*
* Configuration
*/
input wire logic [15:0] prescale
input wire logic [PRE_W-1:0] prescale
);
logic [15:0] prescale_reg = 0;
localparam FRAC_W = 3;
localparam INT_W = PRE_W - FRAC_W;
logic [INT_W-1:0] prescale_int_reg = 0;
logic [FRAC_W-1:0] prescale_frac_reg = 0;
logic frac_ovf_reg = 1'b0;
logic baud_clk_reg = 1'b0;
assign baud_clk = baud_clk_reg;
always_ff @(posedge clk) begin
frac_ovf_reg <= 1'b0;
baud_clk_reg <= 1'b0;
if (prescale_reg != 0) begin
prescale_reg <= prescale_reg - 1;
if (frac_ovf_reg) begin
// delay extra cycle
frac_ovf_reg <= 1'b0;
end else if (prescale_int_reg != 0) begin
prescale_int_reg <= prescale_int_reg - 1;
end else begin
prescale_reg <= prescale - 1;
prescale_int_reg <= prescale[FRAC_W +: INT_W] - 1;
{frac_ovf_reg, prescale_frac_reg} <= prescale_frac_reg + prescale[FRAC_W-1:0];
baud_clk_reg <= 1'b1;
end
if (rst) begin
prescale_reg <= 0;
prescale_int_reg <= 0;
prescale_frac_reg <= 0;
baud_clk_reg <= 0;
end
end

19
rtl/xfcp/taxi_xfcp_if_uart.sv
View File

@@ -16,35 +16,38 @@ Authors:
* XFCP Interface (UART)
*/
module taxi_xfcp_if_uart #(
parameter PRE_W = 16,
parameter TX_FIFO_DEPTH = 512,
parameter RX_FIFO_DEPTH = 512
)
(
input wire logic clk,
input wire logic rst,
input wire logic clk,
input wire logic rst,
/*
* UART interface
*/
input wire logic uart_rxd,
output wire logic uart_txd,
input wire logic uart_rxd,
output wire logic uart_txd,
/*
* XFCP downstream port
*/
taxi_axis_if.src xfcp_dsp_ds,
taxi_axis_if.snk xfcp_dsp_us,
taxi_axis_if.src xfcp_dsp_ds,
taxi_axis_if.snk xfcp_dsp_us,
/*
* Configuration
*/
input wire logic [15:0] prescale
input wire logic [PRE_W-1:0] prescale
);
taxi_axis_if #(.DATA_W(8), .LAST_EN(0)) uart_tx(), uart_rx();
taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) fifo_tx(), fifo_rx();
taxi_uart
taxi_uart #(
.PRE_W(PRE_W)
)
uart_inst (
.clk(clk),
.rst(rst),