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lss: Implement fractional baud rate generation for UART

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-03-11 23:49:39 -07:00
parent 1c686391ab
commit ebeadee172
19 changed files with 86 additions and 57 deletions
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3
tb/lss/taxi_uart/Makefile
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@@ -28,7 +28,8 @@ uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_DATA_W ?= 8
export PARAM_PRE_W := 16
export PARAM_DATA_W := 8
ifeq ($(SIM), icarus)
PLUSARGS += -fst

3
tb/lss/taxi_uart/test_taxi_uart.py
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@@ -39,7 +39,7 @@ class TB:
self.axis_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_tx), dut.clk, dut.rst)
self.axis_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst)
dut.prescale.setimmediatevalue(int(1/8e-9/baud/8))
dut.prescale.setimmediatevalue(int(1/8e-9/baud))
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@@ -168,6 +168,7 @@ def test_taxi_uart(request):
parameters = {}
parameters['PRE_W'] = 16
parameters['DATA_W'] = 8
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

7
tb/lss/taxi_uart/test_taxi_uart.sv
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@@ -18,6 +18,7 @@ Authors:
module test_taxi_uart #
(
/* verilator lint_off WIDTHTRUNC */
parameter PRE_W = 16,
parameter DATA_W = 8
/* verilator lint_on WIDTHTRUNC */
)
@@ -37,9 +38,11 @@ logic rx_busy;
logic rx_overrun_error;
logic rx_frame_error;
logic [15:0] prescale;
logic [PRE_W-1:0] prescale;
taxi_uart
taxi_uart #(
.PRE_W(PRE_W)
)
uut (
.clk(clk),
.rst(rst),

1
tb/xfcp/taxi_xfcp_if_uart/Makefile
View File

@@ -28,6 +28,7 @@ uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_PRE_W := 16
export PARAM_TX_FIFO_DEPTH := 512
export PARAM_RX_FIFO_DEPTH := 512

3
tb/xfcp/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.py
View File

@@ -50,7 +50,7 @@ class TB(object):
self.dsp_source = AxiStreamSource(AxiStreamBus.from_entity(dut.xfcp_dsp_us), dut.clk, dut.rst)
self.dsp_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.xfcp_dsp_ds), dut.clk, dut.rst)
dut.prescale.setimmediatevalue(int(1/8e-9/baud/8))
dut.prescale.setimmediatevalue(int(1/8e-9/baud))
async def reset(self):
self.dut.rst.setimmediatevalue(0)
@@ -181,6 +181,7 @@ def test_taxi_xfcp_if_uart(request):
parameters = {}
parameters['PRE_W'] = 16
parameters['TX_FIFO_DEPTH'] = 512
parameters['RX_FIFO_DEPTH'] = 512

4
tb/xfcp/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.sv
View File

@@ -18,6 +18,7 @@ Authors:
module test_taxi_xfcp_if_uart #
(
/* verilator lint_off WIDTHTRUNC */
parameter PRE_W = 16,
parameter TX_FIFO_DEPTH = 512,
parameter RX_FIFO_DEPTH = 512
/* verilator lint_on WIDTHTRUNC */
@@ -32,9 +33,10 @@ logic uart_txd;
taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_dsp_ds(), xfcp_dsp_us();
logic [15:0] prescale;
logic [PRE_W-1:0] prescale;
taxi_xfcp_if_uart #(
.PRE_W(PRE_W),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH)
)