From ecc1558ab73ec4655a8fa2e4d4fd2315e0f88c45 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sun, 9 Aug 2026 12:34:41 -0700 Subject: [PATCH] eth: Example design cleanup Signed-off-by: Alex Forencich --- src/eth/example/ZCU102/fpga/rtl/fpga_core.sv | 2 -- src/eth/example/ZCU102/fpga/tb/fpga_core/Makefile | 1 - src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py | 1 - src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile | 1 - src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py | 1 - 5 files changed, 6 deletions(-) diff --git a/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv index ae00807..cf54e7e 100644 --- a/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ZCU102/fpga/rtl/fpga_core.sv @@ -23,8 +23,6 @@ module fpga_core # parameter string VENDOR = "XILINX", // device family parameter string FAMILY = "zynquplus", - // SFP rate selection (0 for 1G, 1 for 10G) - parameter logic SFP_RATE = 1'b1, // MAC configuration parameter logic CFG_LOW_LATENCY = 1'b1, parameter logic COMBINED_MAC_PCS = 1'b1, diff --git a/src/eth/example/ZCU102/fpga/tb/fpga_core/Makefile b/src/eth/example/ZCU102/fpga/tb/fpga_core/Makefile index 1fd5ac4..8ed7a05 100644 --- a/src/eth/example/ZCU102/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/ZCU102/fpga/tb/fpga_core/Makefile @@ -23,7 +23,6 @@ COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv -VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_1g_basex_us.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f diff --git a/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index 40602d1..a836f29 100644 --- a/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -245,7 +245,6 @@ def test_fpga_core(request, mac_data_w): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"), os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_1g_basex_us.f"), os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"), diff --git a/src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile b/src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile index 1fd5ac4..8ed7a05 100644 --- a/src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile +++ b/src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile @@ -23,7 +23,6 @@ COCOTB_TOPLEVEL = $(DUT) MODULE = $(COCOTB_TEST_MODULES) TOPLEVEL = $(COCOTB_TOPLEVEL) VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv -VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_1g_basex_us.f VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f diff --git a/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py b/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py index 40602d1..a836f29 100644 --- a/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py @@ -245,7 +245,6 @@ def test_fpga_core(request, mac_data_w): verilog_sources = [ os.path.join(rtl_dir, f"{dut}.sv"), - os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"), os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"), os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_1g_basex_us.f"), os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),