From ecfb50641d5a12eec4019d96e4347e3cd3f527cb Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Wed, 9 Apr 2025 14:24:12 -0700
Subject: [PATCH] axis: Fix async FIFO timing constraints when using
 distributed RAM

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 syn/vivado/taxi_axis_async_fifo.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/syn/vivado/taxi_axis_async_fifo.tcl b/syn/vivado/taxi_axis_async_fifo.tcl
index f6ce878..f67c50b 100644
--- a/syn/vivado/taxi_axis_async_fifo.tcl
+++ b/syn/vivado/taxi_axis_async_fifo.tcl
@@ -49,7 +49,7 @@ foreach fifo_inst [get_cells -hier -filter {(ORIG_REF_NAME == taxi_axis_async_fi
     }
 
     # output register (needed for distributed RAM sync write/async read)
-    set output_reg_ffs [get_cells -quiet "$fifo_inst/m_axis_pipe_reg_reg[0][*]"]
+    set output_reg_ffs [get_cells -quiet "$fifo_inst/mem_rd_data_pipe_reg_reg[0][*]"]
 
     if {[llength $output_reg_ffs]} {
         if {[llength $write_clk]} {