From f0f2a259436918b9c29cbe103a30cb73161fb0ba Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 7 Feb 2025 16:25:54 -0800 Subject: [PATCH] eth: Add AXI stream 64-bit XGMII Ethernet frame receiver module and testbench Signed-off-by: Alex Forencich --- rtl/eth/taxi_axis_xgmii_rx_64.sv | 439 ++++++++++++++++++ tb/eth/taxi_axis_xgmii_rx_64/Makefile | 52 +++ .../test_taxi_axis_xgmii_rx_64.py | 176 +++++++ .../test_taxi_axis_xgmii_rx_64.sv | 90 ++++ 4 files changed, 757 insertions(+) create mode 100644 rtl/eth/taxi_axis_xgmii_rx_64.sv create mode 100644 tb/eth/taxi_axis_xgmii_rx_64/Makefile create mode 100644 tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.py create mode 100644 tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv diff --git a/rtl/eth/taxi_axis_xgmii_rx_64.sv b/rtl/eth/taxi_axis_xgmii_rx_64.sv new file mode 100644 index 0000000..6a21c43 --- /dev/null +++ b/rtl/eth/taxi_axis_xgmii_rx_64.sv @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2015-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4-Stream XGMII frame receiver (XGMII in, AXI out) + */ +module taxi_axis_xgmii_rx_64 # +( + parameter DATA_W = 64, + parameter CTRL_W = (DATA_W/8), + parameter logic PTP_TS_EN = 1'b0, + parameter logic PTP_TS_FMT_TOD = 1'b1, + parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64 +) +( + input wire logic clk, + input wire logic rst, + + /* + * XGMII input + */ + input wire logic [DATA_W-1:0] xgmii_rxd, + input wire logic [CTRL_W-1:0] xgmii_rxc, + + /* + * Receive interface (AXI stream) + */ + taxi_axis_if.src m_axis_rx, + + /* + * PTP + */ + input wire logic [PTP_TS_W-1:0] ptp_ts, + + /* + * Configuration + */ + input wire logic cfg_rx_enable, + + /* + * Status + */ + output wire logic [1:0] start_packet, + output wire logic error_bad_frame, + output wire logic error_bad_fcs +); + +// extract parameters +localparam KEEP_W = DATA_W/8; +localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1; + +// check configuration +if (DATA_W != 64) + $fatal(0, "Error: Interface width must be 64 (instance %m)"); + +if (KEEP_W*8 != DATA_W || CTRL_W*8 != DATA_W) + $fatal(0, "Error: Interface requires byte (8-bit) granularity (instance %m)"); + +if (m_axis_rx.DATA_W != DATA_W) + $fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)"); + +if (m_axis_rx.USER_W != USER_W) + $fatal(0, "Error: Interface USER_W parameter mismatch (instance %m)"); + +localparam [7:0] + ETH_PRE = 8'h55, + ETH_SFD = 8'hD5; + +localparam [7:0] + XGMII_IDLE = 8'h07, + XGMII_START = 8'hfb, + XGMII_TERM = 8'hfd, + XGMII_ERROR = 8'hfe; + +localparam [1:0] + STATE_IDLE = 2'd0, + STATE_PAYLOAD = 2'd1, + STATE_LAST = 2'd2; + +logic [1:0] state_reg = STATE_IDLE, state_next; + +// datapath control signals +logic reset_crc; + +logic lanes_swapped = 1'b0; +logic [31:0] swap_rxd = 32'd0; +logic [3:0] swap_rxc = 4'd0; +logic [3:0] swap_rxc_term = 4'd0; + +logic [2:0] term_lane_reg = 0, term_lane_d0_reg = 0; +logic term_present_reg = 1'b0; +logic framing_error_reg = 1'b0, framing_error_d0_reg = 1'b0; + +logic [DATA_W-1:0] xgmii_rxd_d0 = '0; +logic [DATA_W-1:0] xgmii_rxd_d1 = '0; + +logic [CTRL_W-1:0] xgmii_rxc_d0 = '0; + +logic xgmii_start_swap = 1'b0; +logic xgmii_start_d0 = 1'b0; +logic xgmii_start_d1 = 1'b0; + +logic [DATA_W-1:0] m_axis_rx_tdata_reg = '0, m_axis_rx_tdata_next; +logic [KEEP_W-1:0] m_axis_rx_tkeep_reg = '0, m_axis_rx_tkeep_next; +logic m_axis_rx_tvalid_reg = 1'b0, m_axis_rx_tvalid_next; +logic m_axis_rx_tlast_reg = 1'b0, m_axis_rx_tlast_next; +logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next; + +logic [1:0] start_packet_reg = 2'b00; +logic error_bad_frame_reg = 1'b0, error_bad_frame_next; +logic error_bad_fcs_reg = 1'b0, error_bad_fcs_next; + +logic [PTP_TS_W-1:0] ptp_ts_reg = '0; +logic [PTP_TS_W-1:0] ptp_ts_out_reg = '0, ptp_ts_out_next; +logic [PTP_TS_W-1:0] ptp_ts_adj_reg = '0; +logic ptp_ts_borrow_reg = '0; + +logic [31:0] crc_state = '1; + +wire [31:0] crc_next; + +wire [7:0] crc_valid; +logic [7:0] crc_valid_save; + +assign crc_valid[7] = crc_next == ~32'h2144df1c; +assign crc_valid[6] = crc_next == ~32'hc622f71d; +assign crc_valid[5] = crc_next == ~32'hb1c2a1a3; +assign crc_valid[4] = crc_next == ~32'h9d6cdf7e; +assign crc_valid[3] = crc_next == ~32'h6522df69; +assign crc_valid[2] = crc_next == ~32'he60914ae; +assign crc_valid[1] = crc_next == ~32'he38a6876; +assign crc_valid[0] = crc_next == ~32'h6b87b1ec; + +logic [4+16-1:0] last_ts_reg = '0; +logic [4+16-1:0] ts_inc_reg = '0; + +assign m_axis_rx.tdata = m_axis_rx_tdata_reg; +assign m_axis_rx.tkeep = m_axis_rx_tkeep_reg; +assign m_axis_rx.tstrb = m_axis_rx.tkeep; +assign m_axis_rx.tvalid = m_axis_rx_tvalid_reg; +assign m_axis_rx.tlast = m_axis_rx_tlast_reg; +assign m_axis_rx.tid = '0; +assign m_axis_rx.tdest = '0; +assign m_axis_rx.tuser[0] = m_axis_rx_tuser_reg; +if (PTP_TS_EN) begin + assign m_axis_rx.tuser[1 +: PTP_TS_W] = ptp_ts_out_reg; +end + +assign start_packet = start_packet_reg; +assign error_bad_frame = error_bad_frame_reg; +assign error_bad_fcs = error_bad_fcs_reg; + +taxi_lfsr #( + .LFSR_W(32), + .LFSR_POLY(32'h4c11db7), + .LFSR_GALOIS(1), + .LFSR_FEED_FORWARD(0), + .REVERSE(1), + .DATA_W(64) +) +eth_crc ( + .data_in(xgmii_rxd_d0), + .state_in(crc_state), + .data_out(), + .state_out(crc_next) +); + +// Mask input data +wire [DATA_W-1:0] xgmii_rxd_masked; +wire [CTRL_W-1:0] xgmii_term; + +for (genvar n = 0; n < CTRL_W; n = n + 1) begin + assign xgmii_rxd_masked[n*8 +: 8] = xgmii_rxc[n] ? 8'd0 : xgmii_rxd[n*8 +: 8]; + assign xgmii_term[n] = xgmii_rxc[n] && (xgmii_rxd[n*8 +: 8] == XGMII_TERM); +end + +always_comb begin + state_next = STATE_IDLE; + + reset_crc = 1'b0; + + m_axis_rx_tdata_next = xgmii_rxd_d1; + m_axis_rx_tkeep_next = {KEEP_W{1'b1}}; + m_axis_rx_tvalid_next = 1'b0; + m_axis_rx_tlast_next = 1'b0; + m_axis_rx_tuser_next = 1'b0; + + ptp_ts_out_next = ptp_ts_out_reg; + + error_bad_frame_next = 1'b0; + error_bad_fcs_next = 1'b0; + + case (state_reg) + STATE_IDLE: begin + // idle state - wait for packet + reset_crc = 1'b1; + + if (xgmii_start_d1 && cfg_rx_enable) begin + // start condition + + reset_crc = 1'b0; + state_next = STATE_PAYLOAD; + end else begin + state_next = STATE_IDLE; + end + end + STATE_PAYLOAD: begin + // read payload + m_axis_rx_tdata_next = xgmii_rxd_d1; + m_axis_rx_tkeep_next = {KEEP_W{1'b1}}; + m_axis_rx_tvalid_next = 1'b1; + m_axis_rx_tlast_next = 1'b0; + m_axis_rx_tuser_next = 1'b0; + + if (PTP_TS_EN) begin + ptp_ts_out_next = (!PTP_TS_FMT_TOD || ptp_ts_borrow_reg) ? ptp_ts_reg : ptp_ts_adj_reg; + end + + if (framing_error_reg || framing_error_d0_reg) begin + // control or error characters in packet + m_axis_rx_tlast_next = 1'b1; + m_axis_rx_tuser_next = 1'b1; + error_bad_frame_next = 1'b1; + reset_crc = 1'b1; + state_next = STATE_IDLE; + end else if (term_present_reg) begin + reset_crc = 1'b1; + if (term_lane_reg <= 4) begin + // end this cycle + m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W-4-term_lane_reg); + m_axis_rx_tlast_next = 1'b1; + if ((term_lane_reg == 0 && crc_valid_save[7]) || + (term_lane_reg == 1 && crc_valid[0]) || + (term_lane_reg == 2 && crc_valid[1]) || + (term_lane_reg == 3 && crc_valid[2]) || + (term_lane_reg == 4 && crc_valid[3])) begin + // CRC valid + end else begin + m_axis_rx_tuser_next = 1'b1; + error_bad_frame_next = 1'b1; + error_bad_fcs_next = 1'b1; + end + state_next = STATE_IDLE; + end else begin + // need extra cycle + state_next = STATE_LAST; + end + end else begin + state_next = STATE_PAYLOAD; + end + end + STATE_LAST: begin + // last cycle of packet + m_axis_rx_tdata_next = xgmii_rxd_d1; + m_axis_rx_tkeep_next = {KEEP_W{1'b1}} >> 3'(CTRL_W+4-term_lane_d0_reg); + m_axis_rx_tvalid_next = 1'b1; + m_axis_rx_tlast_next = 1'b1; + m_axis_rx_tuser_next = 1'b0; + + reset_crc = 1'b1; + + if ((term_lane_d0_reg == 5 && crc_valid_save[4]) || + (term_lane_d0_reg == 6 && crc_valid_save[5]) || + (term_lane_d0_reg == 7 && crc_valid_save[6])) begin + // CRC valid + end else begin + m_axis_rx_tuser_next = 1'b1; + error_bad_frame_next = 1'b1; + error_bad_fcs_next = 1'b1; + end + + if (xgmii_start_d1 && cfg_rx_enable) begin + // start condition + + reset_crc = 1'b0; + state_next = STATE_PAYLOAD; + end else begin + state_next = STATE_IDLE; + end + end + default: begin + // invalid state, return to idle + state_next = STATE_IDLE; + end + endcase +end + +always_ff @(posedge clk) begin + state_reg <= state_next; + + m_axis_rx_tdata_reg <= m_axis_rx_tdata_next; + m_axis_rx_tkeep_reg <= m_axis_rx_tkeep_next; + m_axis_rx_tvalid_reg <= m_axis_rx_tvalid_next; + m_axis_rx_tlast_reg <= m_axis_rx_tlast_next; + m_axis_rx_tuser_reg <= m_axis_rx_tuser_next; + + ptp_ts_out_reg <= ptp_ts_out_next; + + start_packet_reg <= 2'b00; + error_bad_frame_reg <= error_bad_frame_next; + error_bad_fcs_reg <= error_bad_fcs_next; + + swap_rxd <= xgmii_rxd_masked[63:32]; + swap_rxc <= xgmii_rxc[7:4]; + swap_rxc_term <= xgmii_term[7:4]; + + xgmii_start_swap <= 1'b0; + xgmii_start_d0 <= xgmii_start_swap; + + if (PTP_TS_EN && PTP_TS_FMT_TOD) begin + // ns field rollover + ptp_ts_adj_reg[15:0] <= ptp_ts_reg[15:0]; + {ptp_ts_borrow_reg, ptp_ts_adj_reg[45:16]} <= $signed({1'b0, ptp_ts_reg[45:16]}) - $signed(31'd1000000000); + ptp_ts_adj_reg[47:46] <= 0; + ptp_ts_adj_reg[95:48] <= ptp_ts_reg[95:48] + 1; + end + + // lane swapping and termination character detection + if (lanes_swapped) begin + xgmii_rxd_d0 <= {xgmii_rxd_masked[31:0], swap_rxd}; + xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc}; + + term_lane_reg <= 0; + term_present_reg <= 1'b0; + framing_error_reg <= {xgmii_rxc[3:0], swap_rxc} != 0; + + for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin + if ({xgmii_term[3:0], swap_rxc_term}[i]) begin + term_lane_reg <= 3'(i); + term_present_reg <= 1'b1; + framing_error_reg <= ({xgmii_rxc[3:0], swap_rxc} & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0; + lanes_swapped <= 1'b0; + end + end + end else begin + xgmii_rxd_d0 <= xgmii_rxd_masked; + xgmii_rxc_d0 <= xgmii_rxc; + + term_lane_reg <= 0; + term_present_reg <= 1'b0; + framing_error_reg <= xgmii_rxc != 0; + + for (integer i = CTRL_W-1; i >= 0; i = i - 1) begin + if (xgmii_rxc[i] && (xgmii_rxd[i*8 +: 8] == XGMII_TERM)) begin + term_lane_reg <= 3'(i); + term_present_reg <= 1'b1; + framing_error_reg <= (xgmii_rxc & ({CTRL_W{1'b1}} >> (CTRL_W-i))) != 0; + lanes_swapped <= 1'b0; + end + end + end + + // start control character detection + if (xgmii_rxc[0] && xgmii_rxd[7:0] == XGMII_START) begin + lanes_swapped <= 1'b0; + + xgmii_start_d0 <= 1'b1; + + term_lane_reg <= 0; + term_present_reg <= 1'b0; + framing_error_reg <= xgmii_rxc[7:1] != 0; + end else if (xgmii_rxc[4] && xgmii_rxd[39:32] == XGMII_START) begin + lanes_swapped <= 1'b1; + + xgmii_start_swap <= 1'b1; + + term_lane_reg <= 0; + term_present_reg <= 1'b0; + framing_error_reg <= xgmii_rxc[7:5] != 0; + end + + // capture timestamps + if (xgmii_start_swap) begin + start_packet_reg <= 2'b10; + if (PTP_TS_FMT_TOD) begin + ptp_ts_reg[45:0] <= ptp_ts[45:0] + 46'(ts_inc_reg >> 1); + ptp_ts_reg[95:48] <= ptp_ts[95:48]; + end else begin + ptp_ts_reg <= ptp_ts + PTP_TS_W'(ts_inc_reg >> 1); + end + end + + if (xgmii_start_d0) begin + if (!lanes_swapped) begin + start_packet_reg <= 2'b01; + ptp_ts_reg <= ptp_ts; + end + end + + term_lane_d0_reg <= term_lane_reg; + framing_error_d0_reg <= framing_error_reg; + + if (reset_crc) begin + crc_state <= '1; + end else begin + crc_state <= crc_next; + end + + crc_valid_save <= crc_valid; + + xgmii_rxd_d1 <= xgmii_rxd_d0; + xgmii_start_d1 <= xgmii_start_d0; + + last_ts_reg <= (4+16)'(ptp_ts); + ts_inc_reg <= (4+16)'(ptp_ts) - last_ts_reg; + + if (rst) begin + state_reg <= STATE_IDLE; + + m_axis_rx_tvalid_reg <= 1'b0; + + start_packet_reg <= 2'b00; + error_bad_frame_reg <= 1'b0; + error_bad_fcs_reg <= 1'b0; + + xgmii_rxc_d0 <= '0; + + xgmii_start_swap <= 1'b0; + xgmii_start_d0 <= 1'b0; + xgmii_start_d1 <= 1'b0; + + lanes_swapped <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/tb/eth/taxi_axis_xgmii_rx_64/Makefile b/tb/eth/taxi_axis_xgmii_rx_64/Makefile new file mode 100644 index 0000000..666d663 --- /dev/null +++ b/tb/eth/taxi_axis_xgmii_rx_64/Makefile @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +DUT = taxi_axis_xgmii_rx_64 +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += ../../../rtl/eth/$(DUT).sv +VERILOG_SOURCES += ../../../rtl/lfsr/taxi_lfsr.sv +VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_DATA_W := 64 +export PARAM_CTRL_W := $(shell expr $(PARAM_DATA_W) / 8 ) +export PARAM_PTP_TS_EN := 1 +export PARAM_PTP_TS_FMT_TOD := 1 +export PARAM_PTP_TS_W := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),64,96) + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.py b/tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.py new file mode 100644 index 0000000..9ad7483 --- /dev/null +++ b/tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.py @@ -0,0 +1,176 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2020-2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os + +import cocotb_test.simulator + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge +from cocotb.utils import get_time_from_sim_steps +from cocotb.regression import TestFactory + +from cocotbext.eth import XgmiiFrame, XgmiiSource, PtpClockSimTime +from cocotbext.axi import AxiStreamBus, AxiStreamSink + + +class TB: + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) + + self.source = XgmiiSource(dut.xgmii_rxd, dut.xgmii_rxc, dut.clk, dut.rst) + self.sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_rx), dut.clk, dut.rst) + + self.ptp_clock = PtpClockSimTime(ts_tod=dut.ptp_ts, clock=dut.clk) + + dut.cfg_rx_enable.setimmediatevalue(0) + + async def reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12): + + tb = TB(dut) + + tb.source.ifg = ifg + tb.dut.cfg_rx_enable.value = 1 + + await tb.reset() + + test_frames = [payload_data(x) for x in payload_lengths()] + tx_frames = [] + + for test_data in test_frames: + test_frame = XgmiiFrame.from_payload(test_data, tx_complete=tx_frames.append) + await tb.source.send(test_frame) + + for test_data in test_frames: + rx_frame = await tb.sink.recv() + tx_frame = tx_frames.pop(0) + + frame_error = rx_frame.tuser & 1 + ptp_ts = rx_frame.tuser >> 1 + ptp_ts_ns = ptp_ts / 2**16 + + tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns") + + if tx_frame.start_lane == 4: + # start in lane 4 reports 1 full cycle delay, so subtract half clock period + tx_frame_sfd_ns -= 3.2 + + tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) + tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) + tb.log.info("Difference: %f ns", abs(ptp_ts_ns - tx_frame_sfd_ns)) + + assert rx_frame.tdata == test_data + assert frame_error == 0 + assert abs(ptp_ts_ns - tx_frame_sfd_ns - 6.4) < 0.01 + + assert tb.sink.empty() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def size_list(): + return list(range(60, 128)) + [512, 1514, 9214] + [60]*10 + + +def incrementing_payload(length): + return bytearray(itertools.islice(itertools.cycle(range(256)), length)) + + +def cycle_en(): + return itertools.cycle([0, 0, 0, 1]) + + +if cocotb.SIM_NAME: + + factory = TestFactory(run_test) + factory.add_option("payload_lengths", [size_list]) + factory.add_option("payload_data", [incrementing_payload]) + factory.add_option("ifg", [12, 0]) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +def test_taxi_axis_xgmii_rx_64(request): + dut = "taxi_axis_xgmii_rx_64" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, "eth", f"{dut}.sv"), + os.path.join(rtl_dir, "lfsr", "taxi_lfsr.sv"), + os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['DATA_W'] = 64 + parameters['CTRL_W'] = parameters['DATA_W'] // 8 + parameters['PTP_TS_EN'] = 1 + parameters['PTP_TS_FMT_TOD'] = 1 + parameters['PTP_TS_W'] = 96 if parameters['PTP_TS_FMT_TOD'] else 64 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv b/tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv new file mode 100644 index 0000000..58265f1 --- /dev/null +++ b/tb/eth/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * AXI4-Stream XGMII frame receiver testbench + */ +module test_taxi_axis_xgmii_rx_64 # +( + /* verilator lint_off WIDTHTRUNC */ + parameter DATA_W = 64, + parameter CTRL_W = (DATA_W/8), + parameter logic PTP_TS_EN = 1'b0, + parameter logic PTP_TS_FMT_TOD = 1'b1, + parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +localparam USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1; + +logic clk; +logic rst; + +logic [DATA_W-1:0] xgmii_rxd; +logic [CTRL_W-1:0] xgmii_rxc; + +taxi_axis_if #(.DATA_W(DATA_W), .USER_W(USER_W)) m_axis_rx(); + +logic [PTP_TS_W-1:0] ptp_ts; + +logic cfg_rx_enable; + +logic [1:0] start_packet; +logic error_bad_frame; +logic error_bad_fcs; + +taxi_axis_xgmii_rx_64 #( + .DATA_W(DATA_W), + .CTRL_W(CTRL_W), + .PTP_TS_EN(PTP_TS_EN), + .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), + .PTP_TS_W(PTP_TS_W) +) +uut ( + .clk(clk), + .rst(rst), + + /* + * XGMII input + */ + .xgmii_rxd(xgmii_rxd), + .xgmii_rxc(xgmii_rxc), + + /* + * AXI4-Stream output (source) + */ + .m_axis_rx(m_axis_rx), + + /* + * PTP + */ + .ptp_ts(ptp_ts), + + /* + * Configuration + */ + .cfg_rx_enable(cfg_rx_enable), + + /* + * Status + */ + .start_packet(start_packet), + .error_bad_frame(error_bad_frame), + .error_bad_fcs(error_bad_fcs) +); + +endmodule + +`resetall