From f25e41de182e4a58de438997ba271fe2ad5c9f13 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 30 Sep 2025 15:24:56 -0700 Subject: [PATCH] apb: Add APB RAM module and testbench Signed-off-by: Alex Forencich --- README.md | 1 + src/apb/rtl/taxi_apb_ram.sv | 122 +++++++++++ src/apb/tb/taxi_apb_ram/Makefile | 54 +++++ src/apb/tb/taxi_apb_ram/test_taxi_apb_ram.py | 213 +++++++++++++++++++ src/apb/tb/taxi_apb_ram/test_taxi_apb_ram.sv | 54 +++++ 5 files changed, 444 insertions(+) create mode 100644 src/apb/rtl/taxi_apb_ram.sv create mode 100644 src/apb/tb/taxi_apb_ram/Makefile create mode 100644 src/apb/tb/taxi_apb_ram/test_taxi_apb_ram.py create mode 100644 src/apb/tb/taxi_apb_ram/test_taxi_apb_ram.sv diff --git a/README.md b/README.md index ab0b7b6..765744f 100644 --- a/README.md +++ b/README.md @@ -26,6 +26,7 @@ To facilitate the dual-license model, contributions to the project can only be a * APB * SV interface for APB + * Single-port RAM * AXI * SV interface for AXI * AXI to AXI lite adapter diff --git a/src/apb/rtl/taxi_apb_ram.sv b/src/apb/rtl/taxi_apb_ram.sv new file mode 100644 index 0000000..e9df635 --- /dev/null +++ b/src/apb/rtl/taxi_apb_ram.sv @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * APM RAM + */ +module taxi_apb_ram # +( + // Width of address bus in bits + parameter ADDR_W = 16, + // Extra pipeline register on output + parameter logic PIPELINE_OUTPUT = 1'b0 +) +( + input wire logic clk, + input wire logic rst, + + /* + * APB slave interface + */ + taxi_apb_if.slv s_apb +); + +// extract parameters +localparam DATA_W = s_apb.DATA_W; +localparam STRB_W = s_apb.STRB_W; + +localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W); +localparam BYTE_LANES = STRB_W; +localparam BYTE_W = DATA_W/BYTE_LANES; + +// check configuration +if (BYTE_W * STRB_W != DATA_W) + $fatal(0, "Error: APB data width not evenly divisible (instance %m)"); + +if (2**$clog2(BYTE_LANES) != BYTE_LANES) + $fatal(0, "Error: APB byte lane count must be even power of two (instance %m)"); + +if (s_apb.ADDR_W < ADDR_W) + $fatal(0, "Error: APB address width is insufficient (instance %m)"); + +logic mem_wr_en; +logic mem_rd_en; + +logic s_apb_pready_reg = 1'b0, s_apb_pready_next; +logic s_apb_pready_pipe_reg = 1'b0; +logic [DATA_W-1:0] s_apb_prdata_reg = '0, s_apb_prdata_next; +logic [DATA_W-1:0] s_apb_prdata_pipe_reg = '0; + +// (* RAM_STYLE="BLOCK" *) +logic [DATA_W-1:0] mem[2**VALID_ADDR_W]; + +wire [VALID_ADDR_W-1:0] s_apb_paddr_valid = VALID_ADDR_W'(s_apb.paddr >> (ADDR_W - VALID_ADDR_W)); + +assign s_apb.prdata = PIPELINE_OUTPUT ? s_apb_prdata_pipe_reg : s_apb_prdata_reg; +assign s_apb.pready = PIPELINE_OUTPUT ? s_apb_pready_pipe_reg : s_apb_pready_reg; +assign s_apb.pslverr = 1'b0; +assign s_apb.pruser = '0; +assign s_apb.pbuser = '0; + +initial begin + // two nested loops for smaller number of iterations per loop + // workaround for synthesizer complaints about large loop counts + for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin + for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin + mem[j] = '0; + end + end +end + +always_comb begin + mem_wr_en = 1'b0; + mem_rd_en = 1'b0; + + s_apb_pready_next = 1'b0; + + if (s_apb.psel && s_apb.penable && (!s_apb_pready_reg && (PIPELINE_OUTPUT || !s_apb_pready_pipe_reg))) begin + s_apb_pready_next = 1'b1; + + if (s_apb.pwrite) begin + mem_wr_en = 1'b1; + end else begin + mem_rd_en = 1'b1; + end + end +end + +always_ff @(posedge clk) begin + s_apb_pready_reg <= s_apb_pready_next; + + for (integer i = 0; i < BYTE_LANES; i = i + 1) begin + if (mem_wr_en && s_apb.pstrb[i]) begin + mem[s_apb_paddr_valid][BYTE_W*i +: BYTE_W] <= s_apb.pwdata[BYTE_W*i +: BYTE_W]; + end + end + + if (mem_rd_en) begin + s_apb_prdata_reg <= mem[s_apb_paddr_valid]; + end + + s_apb_prdata_pipe_reg <= s_apb_prdata_reg; + s_apb_pready_pipe_reg <= s_apb_pready_reg; + + if (rst) begin + s_apb_pready_reg <= 1'b0; + end +end + +endmodule + +`resetall diff --git a/src/apb/tb/taxi_apb_ram/Makefile b/src/apb/tb/taxi_apb_ram/Makefile new file mode 100644 index 0000000..c180867 --- /dev/null +++ b/src/apb/tb/taxi_apb_ram/Makefile @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: CERN-OHL-S-2.0 +# +# Copyright (c) 2020-2025 FPGA Ninja, LLC +# +# Authors: +# - Alex Forencich + +TOPLEVEL_LANG = verilog + +SIM ?= verilator +WAVES ?= 0 + +COCOTB_HDL_TIMEUNIT = 1ns +COCOTB_HDL_TIMEPRECISION = 1ps + +RTL_DIR = ../../rtl +LIB_DIR = ../../lib +TAXI_SRC_DIR = $(LIB_DIR)/taxi/src + +DUT = taxi_apb_ram +COCOTB_TEST_MODULES = test_$(DUT) +COCOTB_TOPLEVEL = test_$(DUT) +MODULE = $(COCOTB_TEST_MODULES) +TOPLEVEL = $(COCOTB_TOPLEVEL) +VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv +VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv +VERILOG_SOURCES += $(RTL_DIR)/taxi_apb_if.sv + +# handle file list files +process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1))) +process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f)) +uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1)) +VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES))) + +# module parameters +export PARAM_DATA_W := 32 +export PARAM_ADDR_W := 16 +export PARAM_STRB_W := $(shell expr $(PARAM_DATA_W) / 8 ) +export PARAM_PIPELINE_OUTPUT := 0 + +ifeq ($(SIM), icarus) + PLUSARGS += -fst + + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v))) +else ifeq ($(SIM), verilator) + COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v))) + + ifeq ($(WAVES), 1) + COMPILE_ARGS += --trace-fst + VERILATOR_TRACE = 1 + endif +endif + +include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/src/apb/tb/taxi_apb_ram/test_taxi_apb_ram.py b/src/apb/tb/taxi_apb_ram/test_taxi_apb_ram.py new file mode 100644 index 0000000..186c7b2 --- /dev/null +++ b/src/apb/tb/taxi_apb_ram/test_taxi_apb_ram.py @@ -0,0 +1,213 @@ +#!/usr/bin/env python +# SPDX-License-Identifier: CERN-OHL-S-2.0 +""" + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +""" + +import itertools +import logging +import os +import random + +import cocotb_test.simulator +import pytest + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import RisingEdge, Timer +from cocotb.regression import TestFactory + +from cocotbext.axi import ApbBus, ApbMaster + + +class TB(object): + def __init__(self, dut): + self.dut = dut + + self.log = logging.getLogger("cocotb.tb") + self.log.setLevel(logging.DEBUG) + + cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) + + self.apb_master = ApbMaster(ApbBus.from_entity(dut.s_apb), dut.clk, dut.rst) + + def set_idle_generator(self, generator=None): + if generator: + self.apb_master.set_pause_generator(generator()) + + async def cycle_reset(self): + self.dut.rst.setimmediatevalue(0) + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 1 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + self.dut.rst.value = 0 + await RisingEdge(self.dut.clk) + await RisingEdge(self.dut.clk) + + +async def run_test_write(dut, data_in=None, idle_inserter=None): + + tb = TB(dut) + + byte_lanes = tb.apb_master.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): + tb.log.info("length %d, offset %d", length, offset) + addr = offset+0x1000 + test_data = bytearray([x % 256 for x in range(length)]) + + await tb.apb_master.write(addr-4, b'\xaa'*(length+8)) + + await tb.apb_master.write(addr, test_data) + + data = await tb.apb_master.read(addr-1, length+2) + + assert data.data == b'\xaa'+test_data+b'\xaa' + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_test_read(dut, data_in=None, idle_inserter=None): + + tb = TB(dut) + + byte_lanes = tb.apb_master.byte_lanes + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + + for length in range(1, byte_lanes*2): + for offset in range(byte_lanes): + tb.log.info("length %d, offset %d", length, offset) + addr = offset+0x1000 + test_data = bytearray([x % 256 for x in range(length)]) + + await tb.apb_master.write(addr, test_data) + + data = await tb.apb_master.read(addr, length) + + assert data.data == test_data + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +async def run_stress_test(dut, idle_inserter=None): + + tb = TB(dut) + + await tb.cycle_reset() + + tb.set_idle_generator(idle_inserter) + + async def worker(master, offset, aperture, count=16): + for k in range(count): + length = random.randint(1, min(32, aperture)) + addr = offset+random.randint(0, aperture-length) + test_data = bytearray([x % 256 for x in range(length)]) + + await Timer(random.randint(1, 100), 'ns') + + await master.write(addr, test_data) + + await Timer(random.randint(1, 100), 'ns') + + data = await master.read(addr, length) + assert data.data == test_data + + workers = [] + + for k in range(16): + workers.append(cocotb.start_soon(worker(tb.apb_master, k*0x1000, 0x1000, count=16))) + + while workers: + await workers.pop(0).join() + + await RisingEdge(dut.clk) + await RisingEdge(dut.clk) + + +def cycle_pause(): + return itertools.cycle([1, 1, 1, 0]) + + +if getattr(cocotb, 'top', None) is not None: + + for test in [run_test_write, run_test_read, run_stress_test]: + + factory = TestFactory(test) + factory.add_option("idle_inserter", [None, cycle_pause]) + factory.generate_tests() + + +# cocotb-test + +tests_dir = os.path.abspath(os.path.dirname(__file__)) +rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) +lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib')) +taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src')) + + +def process_f_files(files): + lst = {} + for f in files: + if f[-2:].lower() == '.f': + with open(f, 'r') as fp: + l = fp.read().split() + for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]): + lst[os.path.basename(f)] = f + else: + lst[os.path.basename(f)] = f + return list(lst.values()) + + +@pytest.mark.parametrize("data_w", [8, 16, 32]) +def test_taxi_apb_ram(request, data_w): + dut = "taxi_apb_ram" + module = os.path.splitext(os.path.basename(__file__))[0] + toplevel = module + + verilog_sources = [ + os.path.join(tests_dir, f"{toplevel}.sv"), + os.path.join(rtl_dir, f"{dut}.sv"), + os.path.join(rtl_dir, "taxi_apb_if.sv"), + ] + + verilog_sources = process_f_files(verilog_sources) + + parameters = {} + + parameters['DATA_W'] = data_w + parameters['ADDR_W'] = 16 + parameters['STRB_W'] = parameters['DATA_W'] // 8 + parameters['PIPELINE_OUTPUT'] = 0 + + extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} + + sim_build = os.path.join(tests_dir, "sim_build", + request.node.name.replace('[', '-').replace(']', '')) + + cocotb_test.simulator.run( + simulator="verilator", + python_search=[tests_dir], + verilog_sources=verilog_sources, + toplevel=toplevel, + module=module, + parameters=parameters, + sim_build=sim_build, + extra_env=extra_env, + ) diff --git a/src/apb/tb/taxi_apb_ram/test_taxi_apb_ram.sv b/src/apb/tb/taxi_apb_ram/test_taxi_apb_ram.sv new file mode 100644 index 0000000..2d2d13d --- /dev/null +++ b/src/apb/tb/taxi_apb_ram/test_taxi_apb_ram.sv @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: CERN-OHL-S-2.0 +/* + +Copyright (c) 2025 FPGA Ninja, LLC + +Authors: +- Alex Forencich + +*/ + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * APB RAM testbench + */ +module test_taxi_apb_ram # +( + /* verilator lint_off WIDTHTRUNC */ + parameter DATA_W = 32, + parameter ADDR_W = 16, + parameter STRB_W = (DATA_W/8), + parameter PIPELINE_OUTPUT = 0 + /* verilator lint_on WIDTHTRUNC */ +) +(); + +logic clk; +logic rst; + +taxi_apb_if #( + .DATA_W(DATA_W), + .ADDR_W(ADDR_W+16), + .STRB_W(STRB_W) +) s_apb(); + +taxi_apb_ram #( + .ADDR_W(ADDR_W), + .PIPELINE_OUTPUT(PIPELINE_OUTPUT) +) +uut ( + .clk(clk), + .rst(rst), + + /* + * AXI4-Lite slave interface + */ + .s_apb(s_apb) +); + +endmodule + +`resetall