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https://github.com/fpganinja/taxi.git
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eth: Fix offset start in BASE-R model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -223,6 +223,7 @@ class BaseRSerdesSource():
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frame_offset = 0
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sof = False
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in_pre = False
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in_term = False
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ifg_cnt = 0
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deficit_idle_cnt = 0
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scrambler_state = 0
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@@ -299,106 +300,92 @@ class BaseRSerdesSource():
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continue
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if rep_cnt != 0:
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# scale IFG
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pass
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elif ifg_cnt + deficit_idle_cnt > 8-1 or (not self.enable_dic and ifg_cnt > 4):
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# in IFG
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ifg_cnt = ifg_cnt - 8
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if ifg_cnt < 0:
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if self.enable_dic:
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deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
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ifg_cnt = 0
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elif frame is None:
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# idle
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if not self.queue.empty():
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# send frame
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frame = self.queue.get_nowait()
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self.dequeue_event.set()
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self.queue_occupancy_bytes -= len(frame)
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self.queue_occupancy_frames -= 1
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self.current_frame = frame
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frame.sim_time_start = sim_time - gbx_delay
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frame.sim_time_sfd = None
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frame.sim_time_end = None
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self.log.info("TX frame: %s", frame)
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frame.normalize()
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frame.start_lane = 0
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assert frame.data[0] == EthPre.PRE
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assert frame.ctrl[0] == 0
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frame.data[0] = XgmiiCtrl.START
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frame.ctrl[0] = 1
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frame.data.append(XgmiiCtrl.TERM)
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frame.ctrl.append(1)
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# offset start
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if self.enable_dic:
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min_ifg = 3 - deficit_idle_cnt
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else:
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min_ifg = 0
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if ifg_cnt > min_ifg or self.force_offset_start:
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ifg_cnt = ifg_cnt-4
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frame.start_lane = 4
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frame.sim_time_start = sim_time + (clk_period // self.byte_lanes * 4) - gbx_delay
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frame.data = bytearray([XgmiiCtrl.IDLE]*4)+frame.data
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frame.ctrl = [1]*4+frame.ctrl
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if self.enable_dic:
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deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
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ifg_cnt = 0
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self.active = True
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frame_offset = -1
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sof = True
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in_pre = True
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else:
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# clear counters
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deficit_idle_cnt = 0
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ifg_cnt = 0
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self.active = False
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self.idle_event.set()
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dl = bytearray()
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cl = []
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for k in range(8):
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if frame is not None:
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frame_offset += 1
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if rep_cnt == 0:
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pass
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elif k == 0 or k == 4:
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frame_offset = max(0, frame_offset-4)
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d = frame.data[frame_offset]
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c = frame.ctrl[frame_offset]
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if frame.sim_time_sfd is None and not in_pre:
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frame.sim_time_sfd = sim_time + (clk_period // self.byte_lanes * k) - gbx_delay
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if d == EthPre.SFD and (not self.xgmii_rep_count or rep_cnt == 1):
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in_pre = False
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if c and d == XgmiiCtrl.START:
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if sof:
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sof = False
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else:
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d = 0xAA
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c = 0
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dl.append(d)
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cl.append(c)
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if k % 4 != 0 or rep_cnt != 0 or (self.force_offset_start and k == 0):
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pass
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elif ifg_cnt + deficit_idle_cnt > 4-1 or (not self.enable_dic and ifg_cnt > 4) or in_term:
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# in IFG
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ifg_cnt = ifg_cnt - 4
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if ifg_cnt < 0:
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if self.enable_dic:
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deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
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ifg_cnt = 0
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elif frame is None:
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# idle
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if not self.queue.empty():
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# send frame
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frame = self.queue.get_nowait()
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self.dequeue_event.set()
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self.queue_occupancy_bytes -= len(frame)
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self.queue_occupancy_frames -= 1
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self.current_frame = frame
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frame.sim_time_start = None
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frame.sim_time_sfd = None
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frame.sim_time_end = None
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self.log.info("TX frame: %s", frame)
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frame.normalize()
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frame.start_lane = 0
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assert frame.data[0] == EthPre.PRE
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assert frame.ctrl[0] == 0
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if frame_offset >= len(frame.data)-1:
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if self.enable_dic:
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deficit_idle_cnt = max(deficit_idle_cnt+ifg_cnt, 0)
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ifg_cnt = 0
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self.active = True
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frame_offset = 0
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sof = True
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in_pre = True
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else:
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# clear counters
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deficit_idle_cnt = 0
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ifg_cnt = 0
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self.active = False
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self.idle_event.set()
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d = XgmiiCtrl.IDLE
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c = 1
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if frame is not None:
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if sof:
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sof = False
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d = XgmiiCtrl.START
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c = 1
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frame.start_lane = k
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frame.sim_time_start = sim_time + (clk_period // self.byte_lanes * k) - gbx_delay
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elif frame_offset >= len(frame.data):
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d = XgmiiCtrl.TERM
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c = 1
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in_term = True
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ifg_cnt = max(self.ifg - (8-k), 0)
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frame.sim_time_end = sim_time + (clk_period // self.byte_lanes * k) - gbx_delay
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frame.handle_tx_complete()
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frame = None
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self.current_frame = None
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else:
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dl.append(XgmiiCtrl.IDLE)
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cl.append(1)
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else:
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d = frame.data[frame_offset]
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c = frame.ctrl[frame_offset]
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if frame.sim_time_sfd is None and not in_pre:
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frame.sim_time_sfd = sim_time + (clk_period // self.byte_lanes * k) - gbx_delay
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if d == EthPre.SFD and (not self.xgmii_rep_count or rep_cnt == 1):
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in_pre = False
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if frame_offset == 0:
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d = 0xAA
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c = 0
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if k == 3 or k == 7:
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dl.append(d)
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cl.append(c)
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frame_offset += 1
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if k % 4 == 3:
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if rep_cnt > 0:
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rep_cnt -= 1
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elif self.xgmii_rep_count:
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rep_cnt = self.xgmii_rep_count
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if self.xgmii_rep_count % 2 == 0 or (k != 3 if self.force_offset_start else k == 3):
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rep_cnt = self.xgmii_rep_count
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if rep_cnt > 0:
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frame_offset -= 4
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# replace idles with ordered sets
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if self.os is not None:
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@@ -413,6 +400,8 @@ class BaseRSerdesSource():
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dl[k+1:k+4] = self.os.to_bytes(3, 'big')
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cl[k+1:k+4] = [0, 0, 0]
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in_term = False
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# remap control characters
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ctrl = sum(xgmii_ctrl_to_baser_mapping.get(d, BaseRCtrl.ERROR) << i*7 for i, d in enumerate(dl))
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