From f31ba113d26b62af80d04e929626f2bd0cbc7306 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 30 May 2025 18:54:45 -0700 Subject: [PATCH] example: Fix KCU105 TX disable pin constraints Signed-off-by: Alex Forencich --- src/eth/example/KCU105/fpga/fpga.xdc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/eth/example/KCU105/fpga/fpga.xdc b/src/eth/example/KCU105/fpga/fpga.xdc index 61688ad..2dc9e05 100644 --- a/src/eth/example/KCU105/fpga/fpga.xdc +++ b/src/eth/example/KCU105/fpga/fpga.xdc @@ -177,8 +177,8 @@ set_property -dict {LOC D28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports { create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p] #create_clock -period 6.400 -name sfp_mgt_refclk_1 [get_ports sfp_mgt_refclk_1_p] -set_false_path -to [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b}] -set_output_delay 0 [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b}] +set_false_path -to [get_ports {sfp_tx_disable_b[*]}] +set_output_delay 0 [get_ports {sfp_tx_disable_b[*]}] # PCIe Interface #set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1