From f5b7eb272d335b76c5ba6956892f90b3c425f76c Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 12 Mar 2026 15:35:03 -0700 Subject: [PATCH] apb: Remove extra idle cycles Signed-off-by: Alex Forencich --- src/apb/rtl/taxi_apb_adapter.sv | 4 ++-- src/apb/rtl/taxi_apb_axil_adapter.sv | 6 +++--- src/apb/rtl/taxi_apb_dp_ram.sv | 4 ++-- src/apb/rtl/taxi_apb_interconnect.sv | 2 +- src/apb/rtl/taxi_apb_ram.sv | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/apb/rtl/taxi_apb_adapter.sv b/src/apb/rtl/taxi_apb_adapter.sv index a3ad3f4..147f6ff 100644 --- a/src/apb/rtl/taxi_apb_adapter.sv +++ b/src/apb/rtl/taxi_apb_adapter.sv @@ -162,7 +162,7 @@ end else if (M_BYTE_LANES > S_BYTE_LANES) begin : upsize m_apb_pauser_next = s_apb.pauser; m_apb_pwuser_next = s_apb.pwuser; - if (s_apb.psel && s_apb.penable && !s_apb.pready) begin + if (s_apb.psel && !s_apb.pready) begin m_apb_psel_next = 1'b1; state_next = STATE_DATA; end else begin @@ -317,7 +317,7 @@ end else begin : downsize s_apb_pslverr_next = 1'b0; - if (s_apb.psel && s_apb.penable && !s_apb.pready) begin + if (s_apb.psel && !s_apb.pready) begin m_apb_psel_next = 1'b1; state_next = STATE_DATA; end else begin diff --git a/src/apb/rtl/taxi_apb_axil_adapter.sv b/src/apb/rtl/taxi_apb_axil_adapter.sv index 32463eb..2de45c7 100644 --- a/src/apb/rtl/taxi_apb_axil_adapter.sv +++ b/src/apb/rtl/taxi_apb_axil_adapter.sv @@ -168,7 +168,7 @@ if (AXIL_BYTE_LANES == APB_BYTE_LANES) begin : bypass m_axil_auser_next = s_apb.pauser; m_axil_wuser_next = s_apb.pwuser; - if (s_apb.psel && s_apb.penable && !s_apb.pready) begin + if (s_apb.psel && !s_apb.pready) begin if (s_apb.pwrite) begin m_axil_awvalid_next = 1'b1; m_axil_wvalid_next = 1'b1; @@ -322,7 +322,7 @@ end else if (AXIL_BYTE_LANES > APB_BYTE_LANES) begin : upsize m_axil_auser_next = s_apb.pauser; m_axil_wuser_next = s_apb.pwuser; - if (s_apb.psel && s_apb.penable && !s_apb.pready) begin + if (s_apb.psel && !s_apb.pready) begin if (s_apb.pwrite) begin m_axil_awvalid_next = 1'b1; m_axil_wvalid_next = 1'b1; @@ -501,7 +501,7 @@ end else begin : downsize s_apb_pslverr_next = 1'b0; - if (s_apb.psel && s_apb.penable && !s_apb.pready) begin + if (s_apb.psel && !s_apb.pready) begin if (s_apb.pwrite) begin m_axil_awvalid_next = 1'b1; m_axil_wvalid_next = 1'b1; diff --git a/src/apb/rtl/taxi_apb_dp_ram.sv b/src/apb/rtl/taxi_apb_dp_ram.sv index 2eece03..12a8848 100644 --- a/src/apb/rtl/taxi_apb_dp_ram.sv +++ b/src/apb/rtl/taxi_apb_dp_ram.sv @@ -101,7 +101,7 @@ always_comb begin s_apb_a_pready_next = 1'b0; - if (s_apb_a.psel && s_apb_a.penable && (!s_apb_a_pready_reg && (PIPELINE_OUTPUT || !s_apb_a_pready_pipe_reg))) begin + if (s_apb_a.psel && (!s_apb_a_pready_reg && (PIPELINE_OUTPUT || !s_apb_a_pready_pipe_reg))) begin s_apb_a_pready_next = 1'b1; if (s_apb_a.pwrite) begin @@ -139,7 +139,7 @@ always_comb begin s_apb_b_pready_next = 1'b0; - if (s_apb_b.psel && s_apb_b.penable && (!s_apb_b_pready_reg && (PIPELINE_OUTPUT || !s_apb_b_pready_pipe_reg))) begin + if (s_apb_b.psel && (!s_apb_b_pready_reg && (PIPELINE_OUTPUT || !s_apb_b_pready_pipe_reg))) begin s_apb_b_pready_next = 1'b1; if (s_apb_b.pwrite) begin diff --git a/src/apb/rtl/taxi_apb_interconnect.sv b/src/apb/rtl/taxi_apb_interconnect.sv index 34b754b..560e49c 100644 --- a/src/apb/rtl/taxi_apb_interconnect.sv +++ b/src/apb/rtl/taxi_apb_interconnect.sv @@ -249,7 +249,7 @@ always_ff @(posedge clk) begin m_apb_psel_reg <= '0; m_apb_penable_reg <= 1'b0; - if (s_apb.psel && s_apb.penable && !s_apb_pready_reg) begin + if (s_apb.psel && !s_apb_pready_reg) begin act_reg <= 1'b1; for (integer i = 0; i < M_CNT; i = i + 1) begin for (integer j = 0; j < M_REGIONS; j = j + 1) begin diff --git a/src/apb/rtl/taxi_apb_ram.sv b/src/apb/rtl/taxi_apb_ram.sv index b0b21f4..6e3a4b6 100644 --- a/src/apb/rtl/taxi_apb_ram.sv +++ b/src/apb/rtl/taxi_apb_ram.sv @@ -75,7 +75,7 @@ always_comb begin s_apb_pready_next = 1'b0; - if (s_apb.psel && s_apb.penable && (!s_apb_pready_reg && (PIPELINE_OUTPUT || !s_apb_pready_pipe_reg))) begin + if (s_apb.psel && (!s_apb_pready_reg && (PIPELINE_OUTPUT || !s_apb_pready_pipe_reg))) begin s_apb_pready_next = 1'b1; if (s_apb.pwrite) begin