diff --git a/example/KC705/fpga/fpga_gmii_1g/Makefile b/example/KC705/fpga/fpga_gmii_1g/Makefile index 3146f23..74f8920 100644 --- a/example/KC705/fpga/fpga_gmii_1g/Makefile +++ b/example/KC705/fpga/fpga_gmii_1g/Makefile @@ -24,7 +24,6 @@ SYN_FILES += ../lib/taxi/rtl/io/taxi_debounce_switch.sv # XDC files XDC_FILES = ../fpga.xdc XDC_FILES += ../eth_gmii.xdc -XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_1g_gmii.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_eth_mac_fifo.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_axis_async_fifo.tcl XDC_FILES += ../lib/taxi/syn/vivado/taxi_sync_reset.tcl diff --git a/rtl/eth/taxi_eth_mac_1g_gmii.sv b/rtl/eth/taxi_eth_mac_1g_gmii.sv index bb0a4c0..71c0f72 100644 --- a/rtl/eth/taxi_eth_mac_1g_gmii.sv +++ b/rtl/eth/taxi_eth_mac_1g_gmii.sv @@ -160,19 +160,29 @@ module taxi_eth_mac_1g_gmii # reg [1:0] link_speed_reg = 2'b10; reg mii_select_reg = 1'b0; -(* srl_style = "register" *) -reg [1:0] tx_mii_select_sync = 2'd0; +wire tx_mii_select_sync; -always_ff @(posedge tx_clk) begin - tx_mii_select_sync <= {tx_mii_select_sync[0], mii_select_reg}; -end +taxi_sync_signal #( + .WIDTH(1), + .N(2) +) +tx_mii_select_sync_inst ( + .clk(tx_clk), + .in(mii_select_reg), + .out(tx_mii_select_sync) +); -(* srl_style = "register" *) -reg [1:0] rx_mii_select_sync = 2'd0; +wire rx_mii_select_sync; -always_ff @(posedge rx_clk) begin - rx_mii_select_sync <= {rx_mii_select_sync[0], mii_select_reg}; -end +taxi_sync_signal #( + .WIDTH(1), + .N(2) +) +rx_mii_select_sync_inst ( + .clk(rx_clk), + .in(mii_select_reg), + .out(rx_mii_select_sync) +); // PHY speed detection reg [2:0] rx_prescale = 3'd0; @@ -181,51 +191,58 @@ always_ff @(posedge rx_clk) begin rx_prescale <= rx_prescale + 3'd1; end -(* srl_style = "register" *) -reg [2:0] rx_prescale_sync = 3'd0; +wire rx_prescale_sync; -always_ff @(posedge gtx_clk) begin - rx_prescale_sync <= {rx_prescale_sync[1:0], rx_prescale[2]}; -end +taxi_sync_signal #( + .WIDTH(1), + .N(2) +) +rx_prescale_sync_inst ( + .clk(gtx_clk), + .in(rx_prescale[2]), + .out(rx_prescale_sync) +); reg [6:0] rx_speed_count_1 = 0; reg [1:0] rx_speed_count_2 = 0; +reg rx_prescale_sync_last_reg = 1'b0; always_ff @(posedge gtx_clk) begin + rx_prescale_sync_last_reg <= rx_prescale_sync; + rx_speed_count_1 <= rx_speed_count_1 + 1; + + if (rx_prescale_sync ^ rx_prescale_sync_last_reg) begin + rx_speed_count_2 <= rx_speed_count_2 + 1; + end + + if (&rx_speed_count_1) begin + // reference count overflow - 10M + rx_speed_count_1 <= 0; + rx_speed_count_2 <= 0; + link_speed_reg <= 2'b00; + mii_select_reg <= 1'b1; + end + + if (&rx_speed_count_2) begin + // prescaled count overflow - 100M or 1000M + rx_speed_count_1 <= 0; + rx_speed_count_2 <= 0; + if (rx_speed_count_1[6:5] != 0) begin + // large reference count - 100M + link_speed_reg <= 2'b01; + mii_select_reg <= 1'b1; + end else begin + // small reference count - 1000M + link_speed_reg <= 2'b10; + mii_select_reg <= 1'b0; + end + end + if (gtx_rst) begin rx_speed_count_1 <= 0; rx_speed_count_2 <= 0; link_speed_reg <= 2'b10; mii_select_reg <= 1'b0; - end else begin - rx_speed_count_1 <= rx_speed_count_1 + 1; - - if (rx_prescale_sync[1] ^ rx_prescale_sync[2]) begin - rx_speed_count_2 <= rx_speed_count_2 + 1; - end - - if (&rx_speed_count_1) begin - // reference count overflow - 10M - rx_speed_count_1 <= 0; - rx_speed_count_2 <= 0; - link_speed_reg <= 2'b00; - mii_select_reg <= 1'b1; - end - - if (&rx_speed_count_2) begin - // prescaled count overflow - 100M or 1000M - rx_speed_count_1 <= 0; - rx_speed_count_2 <= 0; - if (rx_speed_count_1[6:5] != 0) begin - // large reference count - 100M - link_speed_reg <= 2'b01; - mii_select_reg <= 1'b1; - end else begin - // small reference count - 1000M - link_speed_reg <= 2'b10; - mii_select_reg <= 1'b0; - end - end end end @@ -349,8 +366,8 @@ eth_mac_1g_inst ( */ .rx_clk_enable(1'b1), .tx_clk_enable(1'b1), - .rx_mii_select(rx_mii_select_sync[1]), - .tx_mii_select(tx_mii_select_sync[1]), + .rx_mii_select(rx_mii_select_sync), + .tx_mii_select(tx_mii_select_sync), /* * Status diff --git a/syn/vivado/taxi_eth_mac_1g_gmii.tcl b/syn/vivado/taxi_eth_mac_1g_gmii.tcl deleted file mode 100644 index ed18659..0000000 --- a/syn/vivado/taxi_eth_mac_1g_gmii.tcl +++ /dev/null @@ -1,50 +0,0 @@ -# SPDX-License-Identifier: CERN-OHL-S-2.0 -# -# Copyright (c) 2019-2025 FPGA Ninja, LLC -# -# Authors: -# - Alex Forencich -# - -# GMII Gigabit Ethernet MAC timing constraints - -foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "taxi_eth_mac_1g_gmii(__\w+__\d+)?" || - REF_NAME =~ "taxi_eth_mac_1g_gmii(__\w+__\d+)?")}] { - puts "Inserting timing constraints for taxi_eth_mac_1g_gmii instance $inst" - - set select_ffs [get_cells -hier -regexp ".*/tx_mii_select_sync_reg\\\[\\d\\\]" -filter "PARENT == $inst"] - - if {[llength $select_ffs]} { - set_property ASYNC_REG TRUE $select_ffs - - set src_clk [get_clocks -of_objects [get_pins $inst/mii_select_reg_reg/C]] - - set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] - - set_max_delay -from [get_cells $inst/mii_select_reg_reg] -to [get_cells $inst/tx_mii_select_sync_reg[0]] -datapath_only $src_clk_period - } - - set select_ffs [get_cells -hier -regexp ".*/rx_mii_select_sync_reg\\\[\\d\\\]" -filter "PARENT == $inst"] - - if {[llength $select_ffs]} { - set_property ASYNC_REG TRUE $select_ffs - - set src_clk [get_clocks -of_objects [get_pins $inst/mii_select_reg_reg/C]] - - set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] - - set_max_delay -from [get_cells $inst/mii_select_reg_reg] -to [get_cells $inst/rx_mii_select_sync_reg[0]] -datapath_only $src_clk_period - } - - set prescale_ffs [get_cells -hier -regexp ".*/rx_prescale_sync_reg\\\[\\d\\\]" -filter "PARENT == $inst"] - - if {[llength $prescale_ffs]} { - set_property ASYNC_REG TRUE $prescale_ffs - - set src_clk [get_clocks -of_objects [get_pins $inst/rx_prescale_reg[2]/C]] - - set src_clk_period [if {[llength $src_clk]} {get_property -min PERIOD $src_clk} {expr 8.0}] - - set_max_delay -from [get_cells $inst/rx_prescale_reg[2]] -to [get_cells $inst/rx_prescale_sync_reg[0]] -datapath_only $src_clk_period - } -}