diff --git a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv index 1de8580..7ab3623 100644 --- a/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv +++ b/src/eth/example/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv @@ -197,15 +197,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad */ .xcvr_gtpowergood_out(qsfp_gtpowergood[n]), .xcvr_gtrefclk00_in(qsfp_0_mgt_refclk), - .xcvr_qpll0pd_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(qsfp_0_mgt_refclk), - .xcvr_qpll1pd_in(1'b0), - .xcvr_qpll1lock_out(), - .xcvr_qpll1clk_out(), - .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv index 2f6e227..4810a42 100644 --- a/src/eth/example/Alveo/fpga/rtl/fpga_core.sv +++ b/src/eth/example/Alveo/fpga/rtl/fpga_core.sv @@ -377,15 +377,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad */ .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]), .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]), - .xcvr_qpll0pd_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[CLK]), - .xcvr_qpll1pd_in(1'b0), - .xcvr_qpll1lock_out(), - .xcvr_qpll1clk_out(), - .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv index f5213e7..e1c363e 100644 --- a/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv +++ b/src/eth/example/HTG9200/fpga/rtl/fpga_core.sv @@ -465,15 +465,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad */ .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]), .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]), - .xcvr_qpll0pd_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[CLK]), - .xcvr_qpll1pd_in(1'b0), - .xcvr_qpll1lock_out(), - .xcvr_qpll1clk_out(), - .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv b/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv index 7d7c9a4..2da85b1 100644 --- a/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv +++ b/src/eth/example/HTG_ZRF8/fpga/rtl/fpga_core.sv @@ -402,15 +402,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad */ .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]), .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]), - .xcvr_qpll0pd_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[CLK]), - .xcvr_qpll1pd_in(1'b0), - .xcvr_qpll1lock_out(), - .xcvr_qpll1clk_out(), - .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/NT200A02/fpga/rtl/fpga_core.sv b/src/eth/example/NT200A02/fpga/rtl/fpga_core.sv index 0a86bad..fe3ef4f 100644 --- a/src/eth/example/NT200A02/fpga/rtl/fpga_core.sv +++ b/src/eth/example/NT200A02/fpga/rtl/fpga_core.sv @@ -243,15 +243,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad */ .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]), .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]), - .xcvr_qpll0pd_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[CLK]), - .xcvr_qpll1pd_in(1'b0), - .xcvr_qpll1lock_out(), - .xcvr_qpll1clk_out(), - .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv b/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv index 42bb1a1..314dff7 100644 --- a/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv +++ b/src/eth/example/RK_XCKU5P_F/fpga/rtl/fpga_core.sv @@ -400,15 +400,7 @@ if (MAC_DATA_W == 512) begin: mac */ .xcvr_gtpowergood_out(qsfp_gtpowergood), .xcvr_gtrefclk00_in(qsfp_mgt_refclk), - .xcvr_qpll0pd_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(qsfp_mgt_refclk), - .xcvr_qpll1pd_in(1'b0), - .xcvr_qpll1lock_out(), - .xcvr_qpll1clk_out(), - .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/VCU108/fpga/rtl/fpga_core.sv b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv index 6ef9ae8..e52ae45 100644 --- a/src/eth/example/VCU108/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VCU108/fpga/rtl/fpga_core.sv @@ -423,15 +423,7 @@ if (MAC_DATA_W == 512) begin: mac */ .xcvr_gtpowergood_out(qsfp_gtpowergood), .xcvr_gtrefclk00_in(qsfp_mgt_refclk_0), - .xcvr_qpll0pd_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(qsfp_mgt_refclk_0), - .xcvr_qpll1pd_in(1'b0), - .xcvr_qpll1lock_out(), - .xcvr_qpll1clk_out(), - .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/VCU118/fpga/rtl/fpga_core.sv b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv index cc03cfa..368d36e 100644 --- a/src/eth/example/VCU118/fpga/rtl/fpga_core.sv +++ b/src/eth/example/VCU118/fpga/rtl/fpga_core.sv @@ -628,15 +628,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad */ .xcvr_gtpowergood_out(qsfp_gtpowergood[n]), .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0), - .xcvr_qpll0pd_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(qsfp1_mgt_refclk_0), - .xcvr_qpll1pd_in(1'b0), - .xcvr_qpll1lock_out(), - .xcvr_qpll1clk_out(), - .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv index 0f2e060..a951753 100644 --- a/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv +++ b/src/eth/example/XUPP3R/fpga/rtl/fpga_core.sv @@ -358,15 +358,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad */ .xcvr_gtpowergood_out(eth_gty_gtpowergood[n]), .xcvr_gtrefclk00_in(eth_gty_mgt_refclk[CLK]), - .xcvr_qpll0pd_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(eth_gty_mgt_refclk[CLK]), - .xcvr_qpll1pd_in(1'b0), - .xcvr_qpll1lock_out(), - .xcvr_qpll1clk_out(), - .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv index 1a4d987..05cd059 100644 --- a/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv +++ b/src/eth/example/fb2CG/fpga/rtl/fpga_core.sv @@ -255,15 +255,7 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad */ .xcvr_gtpowergood_out(qsfp_gtpowergood[n]), .xcvr_gtrefclk00_in(qsfp_mgt_refclk[CLK]), - .xcvr_qpll0pd_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0clk_out(), - .xcvr_qpll0refclk_out(), .xcvr_gtrefclk01_in(qsfp_mgt_refclk[CLK]), - .xcvr_qpll1pd_in(1'b0), - .xcvr_qpll1lock_out(), - .xcvr_qpll1clk_out(), - .xcvr_qpll1refclk_out(), /* * Serial data diff --git a/src/eth/rtl/us/taxi_eth_mac_100g_us.sv b/src/eth/rtl/us/taxi_eth_mac_100g_us.sv index 20626a6..2995429 100644 --- a/src/eth/rtl/us/taxi_eth_mac_100g_us.sv +++ b/src/eth/rtl/us/taxi_eth_mac_100g_us.sv @@ -81,15 +81,7 @@ module taxi_eth_mac_100g_us # */ output wire logic xcvr_gtpowergood_out, input wire logic xcvr_gtrefclk00_in = 1'b0, - input wire logic xcvr_qpll0pd_in = 1'b0, - output wire logic xcvr_qpll0lock_out, - output wire logic xcvr_qpll0clk_out, - output wire logic xcvr_qpll0refclk_out, input wire logic xcvr_gtrefclk01_in = 1'b0, - input wire logic xcvr_qpll1pd_in = 1'b0, - output wire logic xcvr_qpll1lock_out, - output wire logic xcvr_qpll1clk_out, - output wire logic xcvr_qpll1refclk_out, /* * Serial data @@ -329,6 +321,13 @@ ctrl_intercon_inst ( localparam STAT_TX_CNT = STAT_TX_LEVEL == 0 ? 8 : (STAT_TX_LEVEL == 1 ? 16: 32); localparam STAT_RX_CNT = STAT_RX_LEVEL == 0 ? 8 : (STAT_RX_LEVEL == 1 ? 16: 32); +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; +wire xcvr_qpll1lock; +wire xcvr_qpll1clk; +wire xcvr_qpll1refclk; + wire tx_clk_int[GT_CNT]; wire rx_clk_int[GT_CNT]; wire tx_rst_int[GT_CNT]; @@ -400,12 +399,12 @@ for (genvar n = 0; n < GT_CNT; n = n + 1) begin : ch // drive outputs from common assign xcvr_gtpowergood_out = ch_gtpowergood_out; - assign xcvr_qpll0lock_out = ch_qpll0lock_out; - assign xcvr_qpll0clk_out = ch_qpll0clk_out; - assign xcvr_qpll0refclk_out = ch_qpll0refclk_out; - assign xcvr_qpll1lock_out = ch_qpll1lock_out; - assign xcvr_qpll1clk_out = ch_qpll1clk_out; - assign xcvr_qpll1refclk_out = ch_qpll1refclk_out; + assign xcvr_qpll0lock = ch_qpll0lock_out; + assign xcvr_qpll0clk = ch_qpll0clk_out; + assign xcvr_qpll0refclk = ch_qpll0refclk_out; + assign xcvr_qpll1lock = ch_qpll1lock_out; + assign xcvr_qpll1clk = ch_qpll1clk_out; + assign xcvr_qpll1refclk = ch_qpll1refclk_out; end taxi_eth_mac_100g_us_ch #( @@ -458,12 +457,10 @@ for (genvar n = 0; n < GT_CNT; n = n + 1) begin : ch * PLL out */ .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), - .xcvr_qpll0pd_in(xcvr_qpll0pd_in), .xcvr_qpll0lock_out(ch_qpll0lock_out), .xcvr_qpll0clk_out(ch_qpll0clk_out), .xcvr_qpll0refclk_out(ch_qpll0refclk_out), .xcvr_gtrefclk01_in(xcvr_gtrefclk01_in), - .xcvr_qpll1pd_in(xcvr_qpll1pd_in), .xcvr_qpll1lock_out(ch_qpll1lock_out), .xcvr_qpll1clk_out(ch_qpll1clk_out), .xcvr_qpll1refclk_out(ch_qpll1refclk_out), @@ -471,12 +468,12 @@ for (genvar n = 0; n < GT_CNT; n = n + 1) begin : ch /* * PLL in */ - .xcvr_qpll0lock_in(xcvr_qpll0lock_out), - .xcvr_qpll0clk_in(xcvr_qpll0clk_out), - .xcvr_qpll0refclk_in(xcvr_qpll0refclk_out), - .xcvr_qpll1lock_in(xcvr_qpll1lock_out), - .xcvr_qpll1clk_in(xcvr_qpll1clk_out), - .xcvr_qpll1refclk_in(xcvr_qpll1refclk_out), + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + .xcvr_qpll1lock_in(xcvr_qpll1lock), + .xcvr_qpll1clk_in(xcvr_qpll1clk), + .xcvr_qpll1refclk_in(xcvr_qpll1refclk), /* * Serial data diff --git a/src/eth/rtl/us/taxi_eth_mac_100g_us_ch.sv b/src/eth/rtl/us/taxi_eth_mac_100g_us_ch.sv index c683ab7..adbb761 100644 --- a/src/eth/rtl/us/taxi_eth_mac_100g_us_ch.sv +++ b/src/eth/rtl/us/taxi_eth_mac_100g_us_ch.sv @@ -70,12 +70,10 @@ module taxi_eth_mac_100g_us_ch # * PLL out */ input wire logic xcvr_gtrefclk00_in = 1'b0, - input wire logic xcvr_qpll0pd_in = 1'b0, output wire logic xcvr_qpll0lock_out, output wire logic xcvr_qpll0clk_out, output wire logic xcvr_qpll0refclk_out, input wire logic xcvr_gtrefclk01_in = 1'b0, - input wire logic xcvr_qpll1pd_in = 1'b0, output wire logic xcvr_qpll1lock_out, output wire logic xcvr_qpll1clk_out, output wire logic xcvr_qpll1refclk_out, @@ -245,12 +243,10 @@ if (CFG_LOW_LATENCY) begin : gt * PLL out */ .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), - .xcvr_qpll0pd_in(xcvr_qpll0pd_in), .xcvr_qpll0lock_out(xcvr_qpll0lock_out), .xcvr_qpll0clk_out(xcvr_qpll0clk_out), .xcvr_qpll0refclk_out(xcvr_qpll0refclk_out), .xcvr_gtrefclk01_in(xcvr_gtrefclk01_in), - .xcvr_qpll1pd_in(xcvr_qpll1pd_in), .xcvr_qpll1lock_out(xcvr_qpll1lock_out), .xcvr_qpll1clk_out(xcvr_qpll1clk_out), .xcvr_qpll1refclk_out(xcvr_qpll1refclk_out), @@ -345,12 +341,10 @@ end else if (!CFG_LOW_LATENCY) begin : gt * PLL out */ .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), - .xcvr_qpll0pd_in(xcvr_qpll0pd_in), .xcvr_qpll0lock_out(xcvr_qpll0lock_out), .xcvr_qpll0clk_out(xcvr_qpll0clk_out), .xcvr_qpll0refclk_out(xcvr_qpll0refclk_out), .xcvr_gtrefclk01_in(xcvr_gtrefclk01_in), - .xcvr_qpll1pd_in(xcvr_qpll1pd_in), .xcvr_qpll1lock_out(xcvr_qpll1lock_out), .xcvr_qpll1clk_out(xcvr_qpll1clk_out), .xcvr_qpll1refclk_out(xcvr_qpll1refclk_out), diff --git a/src/eth/rtl/us/taxi_eth_mac_100g_us_gt.sv b/src/eth/rtl/us/taxi_eth_mac_100g_us_gt.sv index 5650d7b..b291407 100644 --- a/src/eth/rtl/us/taxi_eth_mac_100g_us_gt.sv +++ b/src/eth/rtl/us/taxi_eth_mac_100g_us_gt.sv @@ -63,12 +63,10 @@ module taxi_eth_mac_100g_us_gt # * PLL out */ input wire logic xcvr_gtrefclk00_in = 1'b0, - input wire logic xcvr_qpll0pd_in = 1'b0, output wire logic xcvr_qpll0lock_out, output wire logic xcvr_qpll0clk_out, output wire logic xcvr_qpll0refclk_out, input wire logic xcvr_gtrefclk01_in = 1'b0, - input wire logic xcvr_qpll1pd_in = 1'b0, output wire logic xcvr_qpll1lock_out, output wire logic xcvr_qpll1clk_out, output wire logic xcvr_qpll1refclk_out, diff --git a/src/eth/rtl/us/taxi_eth_mac_100g_us_gt_ll.sv b/src/eth/rtl/us/taxi_eth_mac_100g_us_gt_ll.sv index 1df2d61..114c029 100644 --- a/src/eth/rtl/us/taxi_eth_mac_100g_us_gt_ll.sv +++ b/src/eth/rtl/us/taxi_eth_mac_100g_us_gt_ll.sv @@ -63,12 +63,10 @@ module taxi_eth_mac_100g_us_gt_ll # * PLL out */ input wire logic xcvr_gtrefclk00_in = 1'b0, - input wire logic xcvr_qpll0pd_in = 1'b0, output wire logic xcvr_qpll0lock_out, output wire logic xcvr_qpll0clk_out, output wire logic xcvr_qpll0refclk_out, input wire logic xcvr_gtrefclk01_in = 1'b0, - input wire logic xcvr_qpll1pd_in = 1'b0, output wire logic xcvr_qpll1lock_out, output wire logic xcvr_qpll1clk_out, output wire logic xcvr_qpll1refclk_out,