diff --git a/src/cndm/board/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv b/src/cndm/board/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv index dba7df3..5d91051 100644 --- a/src/cndm/board/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv +++ b/src/cndm/board/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv @@ -321,7 +321,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n; assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p; assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n; -for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad +for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad localparam CNT = 4; diff --git a/src/cndm/board/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py b/src/cndm/board/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py index da4a76c..fcab40e 100644 --- a/src/cndm/board/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/cndm/board/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py @@ -9,6 +9,7 @@ Authors: """ +import itertools import logging import os import sys @@ -282,48 +283,47 @@ class TB: self.qsfp_sources = [] self.qsfp_sinks = [] - for inst in dut.uut.gty_quad: - for ch in inst.mac_inst.ch: - gt_inst = ch.ch_inst.gt.gt_inst + for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]): + gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.DATA_W.value == 64: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) - else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) else: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 3.102 - gbx_cfg = (66, [64, 65]) - else: - clk = 3.2 - gbx_cfg = None + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None - cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) - cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource( - data=gt_inst.serdes_rx_data, - data_valid=gt_inst.serdes_rx_data_valid, - hdr=gt_inst.serdes_rx_hdr, - hdr_valid=gt_inst.serdes_rx_hdr_valid, - clock=gt_inst.rx_clk, - slip=gt_inst.serdes_rx_bitslip, - reverse=True, - gbx_cfg=gbx_cfg - )) - self.qsfp_sinks.append(BaseRSerdesSink( - data=gt_inst.serdes_tx_data, - data_valid=gt_inst.serdes_tx_data_valid, - hdr=gt_inst.serdes_tx_hdr, - hdr_valid=gt_inst.serdes_tx_hdr_valid, - gbx_sync=gt_inst.serdes_tx_gbx_sync, - clock=gt_inst.tx_clk, - reverse=True, - gbx_cfg=gbx_cfg - )) + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) dut.user_sw.setimmediatevalue(0) dut.qsfp_0_modprs_l.setimmediatevalue(0) diff --git a/src/cndm/board/Alveo/fpga/rtl/fpga_core.sv b/src/cndm/board/Alveo/fpga/rtl/fpga_core.sv index ada514d..ffc0be5 100644 --- a/src/cndm/board/Alveo/fpga/rtl/fpga_core.sv +++ b/src/cndm/board/Alveo/fpga/rtl/fpga_core.sv @@ -412,7 +412,7 @@ wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT]; wire eth_gty_rst[GTY_CLK_CNT]; -for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk +for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk wire eth_gty_mgt_refclk_int; @@ -469,7 +469,7 @@ assign led[0] = ptp_pps_str; localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"}; localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"}; -for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad +for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad localparam CLK = n; localparam CNT = 4; diff --git a/src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.py b/src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.py index 088a31b..a702841 100644 --- a/src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.py @@ -9,6 +9,7 @@ Authors: """ +import itertools import logging import os import sys @@ -293,48 +294,47 @@ class TB: self.qsfp_sources = [] self.qsfp_sinks = [] - for inst in dut.uut.gty_quad: - for ch in inst.mac_inst.ch: - gt_inst = ch.ch_inst.gt.gt_inst + for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]): + gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.DATA_W.value == 64: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) - else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) else: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 3.102 - gbx_cfg = (66, [64, 65]) - else: - clk = 3.2 - gbx_cfg = None + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None - cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) - cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource( - data=gt_inst.serdes_rx_data, - data_valid=gt_inst.serdes_rx_data_valid, - hdr=gt_inst.serdes_rx_hdr, - hdr_valid=gt_inst.serdes_rx_hdr_valid, - clock=gt_inst.rx_clk, - slip=gt_inst.serdes_rx_bitslip, - reverse=True, - gbx_cfg=gbx_cfg - )) - self.qsfp_sinks.append(BaseRSerdesSink( - data=gt_inst.serdes_tx_data, - data_valid=gt_inst.serdes_tx_data_valid, - hdr=gt_inst.serdes_tx_hdr, - hdr_valid=gt_inst.serdes_tx_hdr_valid, - gbx_sync=gt_inst.serdes_tx_gbx_sync, - clock=gt_inst.tx_clk, - reverse=True, - gbx_cfg=gbx_cfg - )) + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) dut.sw.setimmediatevalue(0) dut.eth_port_modprsl.setimmediatevalue(0) diff --git a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py index c153ad7..1d89109 100644 --- a/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py @@ -9,6 +9,7 @@ Authors: """ +import itertools import logging import os import sys @@ -259,48 +260,47 @@ class TB: self.qsfp_sources = [] self.qsfp_sinks = [] - for inst in dut.uut.gt_quad: - for ch in inst.mac_inst.ch: - gt_inst = ch.ch_inst.gt.gt_inst + for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]): + gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.DATA_W.value == 64: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 6.206 - gbx_cfg = (66, [64, 65]) - else: - clk = 6.4 - gbx_cfg = None + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 6.206 + gbx_cfg = (66, [64, 65]) else: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 3.102 - gbx_cfg = (66, [64, 65]) - else: - clk = 3.2 - gbx_cfg = None + clk = 6.4 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None - cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) - cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource( - data=gt_inst.serdes_rx_data, - data_valid=gt_inst.serdes_rx_data_valid, - hdr=gt_inst.serdes_rx_hdr, - hdr_valid=gt_inst.serdes_rx_hdr_valid, - clock=gt_inst.rx_clk, - slip=gt_inst.serdes_rx_bitslip, - reverse=True, - gbx_cfg=gbx_cfg - )) - self.qsfp_sinks.append(BaseRSerdesSink( - data=gt_inst.serdes_tx_data, - data_valid=gt_inst.serdes_tx_data_valid, - hdr=gt_inst.serdes_tx_hdr, - hdr_valid=gt_inst.serdes_tx_hdr_valid, - gbx_sync=gt_inst.serdes_tx_gbx_sync, - clock=gt_inst.tx_clk, - reverse=True, - gbx_cfg=gbx_cfg - )) + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) self.loopback_enable = False cocotb.start_soon(self._run_loopback()) diff --git a/src/cndm/board/VCU118/fpga/rtl/fpga_core.sv b/src/cndm/board/VCU118/fpga/rtl/fpga_core.sv index d2e65f3..31e01a7 100644 --- a/src/cndm/board/VCU118/fpga/rtl/fpga_core.sv +++ b/src/cndm/board/VCU118/fpga/rtl/fpga_core.sv @@ -720,7 +720,7 @@ wire ptp_pps_str; localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"}; localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"}; -for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad +for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad localparam CNT = 4; diff --git a/src/cndm/board/VCU118/fpga/tb/fpga_core/test_fpga_core.py b/src/cndm/board/VCU118/fpga/tb/fpga_core/test_fpga_core.py index 60142f0..e64254f 100644 --- a/src/cndm/board/VCU118/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/cndm/board/VCU118/fpga/tb/fpga_core/test_fpga_core.py @@ -9,6 +9,7 @@ Authors: """ +import itertools import logging import os import sys @@ -293,48 +294,47 @@ class TB: self.qsfp_sources = [] self.qsfp_sinks = [] - for inst in dut.uut.gty_quad: - for ch in inst.mac_inst.ch: - gt_inst = ch.ch_inst.gt.gt_inst + for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]): + gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.DATA_W.value == 64: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) - else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) else: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 3.102 - gbx_cfg = (66, [64, 65]) - else: - clk = 3.2 - gbx_cfg = None + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None - cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) - cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource( - data=gt_inst.serdes_rx_data, - data_valid=gt_inst.serdes_rx_data_valid, - hdr=gt_inst.serdes_rx_hdr, - hdr_valid=gt_inst.serdes_rx_hdr_valid, - clock=gt_inst.rx_clk, - slip=gt_inst.serdes_rx_bitslip, - reverse=True, - gbx_cfg=gbx_cfg - )) - self.qsfp_sinks.append(BaseRSerdesSink( - data=gt_inst.serdes_tx_data, - data_valid=gt_inst.serdes_tx_data_valid, - hdr=gt_inst.serdes_tx_hdr, - hdr_valid=gt_inst.serdes_tx_hdr_valid, - gbx_sync=gt_inst.serdes_tx_gbx_sync, - clock=gt_inst.tx_clk, - reverse=True, - gbx_cfg=gbx_cfg - )) + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) dut.phy_gmii_clk_en.setimmediatevalue(1) diff --git a/src/cndm/board/fb2CG/fpga/rtl/fpga_core.sv b/src/cndm/board/fb2CG/fpga/rtl/fpga_core.sv index 8041c38..921f665 100644 --- a/src/cndm/board/fb2CG/fpga/rtl/fpga_core.sv +++ b/src/cndm/board/fb2CG/fpga/rtl/fpga_core.sv @@ -293,7 +293,7 @@ wire qsfp_mgt_refclk_bufg[2]; wire qsfp_rst[2]; -for (genvar n = 0; n < 2; n = n + 1) begin : gty_clk +for (genvar n = 0; n < 2; n = n + 1) begin : gt_clk wire qsfp_mgt_refclk_int; @@ -363,7 +363,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n; assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p; assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n; -for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad +for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad localparam CLK = n; localparam CNT = 4; diff --git a/src/cndm/board/fb2CG/fpga/tb/fpga_core/test_fpga_core.py b/src/cndm/board/fb2CG/fpga/tb/fpga_core/test_fpga_core.py index 77730b7..ebd3f64 100644 --- a/src/cndm/board/fb2CG/fpga/tb/fpga_core/test_fpga_core.py +++ b/src/cndm/board/fb2CG/fpga/tb/fpga_core/test_fpga_core.py @@ -9,6 +9,7 @@ Authors: """ +import itertools import logging import os import sys @@ -283,48 +284,47 @@ class TB: self.qsfp_sources = [] self.qsfp_sinks = [] - for inst in dut.uut.gty_quad: - for ch in inst.mac_inst.ch: - gt_inst = ch.ch_inst.gt.gt_inst + for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]): + gt_inst = ch.ch_inst.gt.gt_inst - if ch.ch_inst.DATA_W.value == 64: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 2.482 - gbx_cfg = (66, [64, 65]) - else: - clk = 2.56 - gbx_cfg = None + if ch.ch_inst.DATA_W.value == 64: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 2.482 + gbx_cfg = (66, [64, 65]) else: - if ch.ch_inst.CFG_LOW_LATENCY.value: - clk = 3.102 - gbx_cfg = (66, [64, 65]) - else: - clk = 3.2 - gbx_cfg = None + clk = 2.56 + gbx_cfg = None + else: + if ch.ch_inst.CFG_LOW_LATENCY.value: + clk = 3.102 + gbx_cfg = (66, [64, 65]) + else: + clk = 3.2 + gbx_cfg = None - cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) - cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start()) + cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start()) - self.qsfp_sources.append(BaseRSerdesSource( - data=gt_inst.serdes_rx_data, - data_valid=gt_inst.serdes_rx_data_valid, - hdr=gt_inst.serdes_rx_hdr, - hdr_valid=gt_inst.serdes_rx_hdr_valid, - clock=gt_inst.rx_clk, - slip=gt_inst.serdes_rx_bitslip, - reverse=True, - gbx_cfg=gbx_cfg - )) - self.qsfp_sinks.append(BaseRSerdesSink( - data=gt_inst.serdes_tx_data, - data_valid=gt_inst.serdes_tx_data_valid, - hdr=gt_inst.serdes_tx_hdr, - hdr_valid=gt_inst.serdes_tx_hdr_valid, - gbx_sync=gt_inst.serdes_tx_gbx_sync, - clock=gt_inst.tx_clk, - reverse=True, - gbx_cfg=gbx_cfg - )) + self.qsfp_sources.append(BaseRSerdesSource( + data=gt_inst.serdes_rx_data, + data_valid=gt_inst.serdes_rx_data_valid, + hdr=gt_inst.serdes_rx_hdr, + hdr_valid=gt_inst.serdes_rx_hdr_valid, + clock=gt_inst.rx_clk, + slip=gt_inst.serdes_rx_bitslip, + reverse=True, + gbx_cfg=gbx_cfg + )) + self.qsfp_sinks.append(BaseRSerdesSink( + data=gt_inst.serdes_tx_data, + data_valid=gt_inst.serdes_tx_data_valid, + hdr=gt_inst.serdes_tx_hdr, + hdr_valid=gt_inst.serdes_tx_hdr_valid, + gbx_sync=gt_inst.serdes_tx_gbx_sync, + clock=gt_inst.tx_clk, + reverse=True, + gbx_cfg=gbx_cfg + )) dut.qsfp_0_mod_prsnt_n.setimmediatevalue(0) dut.qsfp_0_intr_n.setimmediatevalue(0)