bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2026-04-09 05:18:44 -07:00
Code Issues Packages Projects Releases Wiki Activity

cndm: Clean up multiple quad handling

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-04-05 18:36:55 -07:00
parent bbe4353c3a
commit fb9757106d
9 changed files with 196 additions and 196 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cndm/board/ADM_PCIE_9V3/fpga/rtl/fpga_core.sv
View File

@@ -321,7 +321,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
localparam CNT = 4;

4
src/cndm/board/ADM_PCIE_9V3/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -9,6 +9,7 @@ Authors:
"""
import itertools
import logging
import os
import sys
@@ -282,8 +283,7 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for inst in dut.uut.gty_quad:
for ch in inst.mac_inst.ch:
for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]):
gt_inst = ch.ch_inst.gt.gt_inst
if ch.ch_inst.DATA_W.value == 64:

4
src/cndm/board/Alveo/fpga/rtl/fpga_core.sv
View File

@@ -412,7 +412,7 @@ wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
wire eth_gty_rst[GTY_CLK_CNT];
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gt_clk
wire eth_gty_mgt_refclk_int;
@@ -469,7 +469,7 @@ assign led[0] = ptp_pps_str;
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"};
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"};
for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gt_quad
localparam CLK = n;
localparam CNT = 4;

4
src/cndm/board/Alveo/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -9,6 +9,7 @@ Authors:
"""
import itertools
import logging
import os
import sys
@@ -293,8 +294,7 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for inst in dut.uut.gty_quad:
for ch in inst.mac_inst.ch:
for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]):
gt_inst = ch.ch_inst.gt.gt_inst
if ch.ch_inst.DATA_W.value == 64:

4
src/cndm/board/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -9,6 +9,7 @@ Authors:
"""
import itertools
import logging
import os
import sys
@@ -259,8 +260,7 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for inst in dut.uut.gt_quad:
for ch in inst.mac_inst.ch:
for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]):
gt_inst = ch.ch_inst.gt.gt_inst
if ch.ch_inst.DATA_W.value == 64:

2
src/cndm/board/VCU118/fpga/rtl/fpga_core.sv
View File

@@ -720,7 +720,7 @@ wire ptp_pps_str;
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP1[4] = '{"QSFP1.1", "QSFP1.2", "QSFP1.3", "QSFP1.4"};
localparam logic [8*8-1:0] STAT_PREFIX_STR_QSFP2[4] = '{"QSFP2.1", "QSFP2.2", "QSFP2.3", "QSFP2.4"};
for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
localparam CNT = 4;

4
src/cndm/board/VCU118/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -9,6 +9,7 @@ Authors:
"""
import itertools
import logging
import os
import sys
@@ -293,8 +294,7 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for inst in dut.uut.gty_quad:
for ch in inst.mac_inst.ch:
for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]):
gt_inst = ch.ch_inst.gt.gt_inst
if ch.ch_inst.DATA_W.value == 64:

4
src/cndm/board/fb2CG/fpga/rtl/fpga_core.sv
View File

@@ -293,7 +293,7 @@ wire qsfp_mgt_refclk_bufg[2];
wire qsfp_rst[2];
for (genvar n = 0; n < 2; n = n + 1) begin : gty_clk
for (genvar n = 0; n < 2; n = n + 1) begin : gt_clk
wire qsfp_mgt_refclk_int;
@@ -363,7 +363,7 @@ assign qsfp_rx_n[4*0 +: 4] = qsfp_0_rx_n;
assign qsfp_rx_p[4*1 +: 4] = qsfp_1_rx_p;
assign qsfp_rx_n[4*1 +: 4] = qsfp_1_rx_n;
for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
for (genvar n = 0; n < 2; n = n + 1) begin : gt_quad
localparam CLK = n;
localparam CNT = 4;

4
src/cndm/board/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -9,6 +9,7 @@ Authors:
"""
import itertools
import logging
import os
import sys
@@ -283,8 +284,7 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for inst in dut.uut.gty_quad:
for ch in inst.mac_inst.ch:
for ch in itertools.chain.from_iterable([inst.mac_inst.ch for inst in dut.uut.gt_quad]):
gt_inst = ch.ch_inst.gt.gt_inst
if ch.ch_inst.DATA_W.value == 64: