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ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
303
rtl/ptp/taxi_ptp_td_rel2tod.sv
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303
rtl/ptp/taxi_ptp_td_rel2tod.sv
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2024-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1fs
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`default_nettype none
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/*
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* PTP time distribution ToD timestamp reconstruction module
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*/
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module taxi_ptp_td_rel2tod #
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(
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parameter TS_FNS_W = 16,
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parameter TS_REL_NS_W = 32,
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parameter TS_TOD_S_W = 48,
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parameter TS_REL_W = TS_REL_NS_W + TS_FNS_W,
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parameter TS_TOD_W = TS_TOD_S_W + 32 + TS_FNS_W,
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parameter TD_SDI_PIPELINE = 2
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* PTP clock interface
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*/
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input wire logic ptp_clk,
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input wire logic ptp_rst,
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input wire logic ptp_td_sdi,
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/*
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* Timestamp conversion
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*/
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taxi_axis_if.snk s_axis_ts_rel,
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taxi_axis_if.src m_axis_ts_tod
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);
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localparam TS_ID_W = s_axis_ts_rel.ID_W;
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localparam TS_DEST_W = s_axis_ts_rel.DEST_W;
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localparam TS_USER_W = s_axis_ts_rel.USER_W;
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localparam TS_TOD_NS_W = 30;
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localparam TS_NS_W = TS_TOD_NS_W+1;
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localparam [30:0] NS_PER_S = 31'd1_000_000_000;
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// pipeline to facilitate long input path
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wire ptp_td_sdi_pipe[0:TD_SDI_PIPELINE];
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assign ptp_td_sdi_pipe[0] = ptp_td_sdi;
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for (genvar n = 0; n < TD_SDI_PIPELINE; n = n + 1) begin : pipe_stage
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(* shreg_extract = "no" *)
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reg ptp_td_sdi_reg = 0;
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assign ptp_td_sdi_pipe[n+1] = ptp_td_sdi_reg;
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always_ff @(posedge ptp_clk) begin
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ptp_td_sdi_reg <= ptp_td_sdi_pipe[n];
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end
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end
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// deserialize data
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logic [15:0] td_shift_reg = '0;
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logic [4:0] bit_cnt_reg = '0;
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logic td_valid_reg = 1'b0;
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logic [3:0] td_index_reg = '0;
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logic [3:0] td_msg_reg = '0;
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logic [15:0] td_tdata_reg = '0;
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logic td_tvalid_reg = 1'b0;
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logic td_tlast_reg = 1'b0;
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logic [7:0] td_tid_reg = '0;
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logic td_sync_reg = 1'b0;
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always_ff @(posedge ptp_clk) begin
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td_shift_reg <= {ptp_td_sdi_pipe[TD_SDI_PIPELINE], td_shift_reg[15:1]};
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td_tvalid_reg <= 1'b0;
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if (bit_cnt_reg != 0) begin
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bit_cnt_reg <= bit_cnt_reg - 1;
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end else begin
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td_valid_reg <= 1'b0;
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if (td_valid_reg) begin
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td_tdata_reg <= td_shift_reg;
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td_tvalid_reg <= 1'b1;
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td_tlast_reg <= ptp_td_sdi_pipe[TD_SDI_PIPELINE];
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td_tid_reg <= {td_msg_reg, td_index_reg};
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if (td_index_reg == 0) begin
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td_msg_reg <= td_shift_reg[3:0];
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td_tid_reg[7:4] <= td_shift_reg[3:0];
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end
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td_index_reg <= td_index_reg + 1;
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td_sync_reg = !td_sync_reg;
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end
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if (ptp_td_sdi_pipe[TD_SDI_PIPELINE] == 0) begin
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bit_cnt_reg <= 16;
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td_valid_reg <= 1'b1;
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end else begin
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td_index_reg <= 0;
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end
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end
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if (ptp_rst) begin
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bit_cnt_reg <= 0;
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td_valid_reg <= 1'b0;
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td_tvalid_reg <= 1'b0;
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end
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end
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// sync TD data
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logic [15:0] dst_td_tdata_reg = '0;
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logic dst_td_tvalid_reg = 1'b0;
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logic [7:0] dst_td_tid_reg = '0;
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(* shreg_extract = "no" *)
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logic td_sync_sync1_reg = 1'b0;
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(* shreg_extract = "no" *)
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logic td_sync_sync2_reg = 1'b0;
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(* shreg_extract = "no" *)
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logic td_sync_sync3_reg = 1'b0;
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always_ff @(posedge clk) begin
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td_sync_sync1_reg <= td_sync_reg;
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td_sync_sync2_reg <= td_sync_sync1_reg;
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td_sync_sync3_reg <= td_sync_sync2_reg;
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end
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always_ff @(posedge clk) begin
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dst_td_tvalid_reg <= 1'b0;
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if (td_sync_sync3_reg ^ td_sync_sync2_reg) begin
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dst_td_tdata_reg <= td_tdata_reg;
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dst_td_tvalid_reg <= 1'b1;
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dst_td_tid_reg <= td_tid_reg;
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end
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if (rst) begin
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dst_td_tvalid_reg <= 1'b0;
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end
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end
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logic ts_sel_reg = 1'b0;
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logic [47:0] ts_tod_s_0_reg = '0;
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logic [31:0] ts_tod_offset_ns_0_reg = '0;
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logic [47:0] ts_tod_s_1_reg = '0;
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logic [31:0] ts_tod_offset_ns_1_reg = '0;
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logic [TS_TOD_S_W-1:0] output_ts_tod_s_reg = '0, output_ts_tod_s_next;
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logic [TS_TOD_NS_W-1:0] output_ts_tod_ns_reg = '0, output_ts_tod_ns_next;
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logic [TS_FNS_W-1:0] output_ts_fns_reg = '0, output_ts_fns_next;
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logic [TS_ID_W-1:0] output_ts_id_reg = '0, output_ts_id_next;
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logic [TS_DEST_W-1:0] output_ts_dest_reg = '0, output_ts_dest_next;
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logic [TS_USER_W-1:0] output_ts_user_reg = '0, output_ts_user_next;
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logic output_ts_valid_reg = 1'b0, output_ts_valid_next;
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logic [TS_NS_W-1:0] ts_tod_ns_0;
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logic [TS_NS_W-1:0] ts_tod_ns_1;
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assign s_axis_ts_rel.tready = 1'b1;
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assign m_axis_ts_tod.tdata = {output_ts_tod_s_reg, 2'b00, output_ts_tod_ns_reg, output_ts_fns_reg};
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assign m_axis_ts_tod.tkeep = '1;
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assign m_axis_ts_tod.tstrb = m_axis_ts_tod.tkeep;
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assign m_axis_ts_tod.tlast = 1'b1;
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assign m_axis_ts_tod.tid = output_ts_id_reg;
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assign m_axis_ts_tod.tdest = output_ts_dest_reg;
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assign m_axis_ts_tod.tuser = output_ts_user_reg;
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assign m_axis_ts_tod.tvalid = output_ts_valid_reg;
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always_comb begin
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// reconstruct timestamp
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// apply both offsets
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ts_tod_ns_0 = TS_NS_W'(s_axis_ts_rel.tdata[TS_FNS_W +: TS_REL_NS_W] + ts_tod_offset_ns_0_reg);
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ts_tod_ns_1 = TS_NS_W'(s_axis_ts_rel.tdata[TS_FNS_W +: TS_REL_NS_W] + ts_tod_offset_ns_1_reg);
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// pick the correct result
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// 2 MSB clear = lower half of range (0-536,870,911)
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// 1 MSB clear = upper half of range, but could also be over 1 billion (536,870,912-1,073,741,823)
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// 1 MSB set = overflow or underflow
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// prefer 2 MSB clear over 1 MSB clear if neither result was overflow or underflow
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if (ts_tod_ns_0[30:29] == 0 || (ts_tod_ns_0[30] == 0 && ts_tod_ns_1[30:29] != 0)) begin
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output_ts_tod_s_next = ts_tod_s_0_reg;
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output_ts_tod_ns_next = ts_tod_ns_0[TS_TOD_NS_W-1:0];
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end else begin
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output_ts_tod_s_next = ts_tod_s_1_reg;
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output_ts_tod_ns_next = ts_tod_ns_1[TS_TOD_NS_W-1:0];
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end
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output_ts_fns_next = s_axis_ts_rel.tdata[TS_FNS_W-1:0];
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output_ts_id_next = s_axis_ts_rel.tid;
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output_ts_dest_next = s_axis_ts_rel.tdest;
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output_ts_user_next = s_axis_ts_rel.tuser;
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output_ts_valid_next = s_axis_ts_rel.tvalid;
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end
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always_ff @(posedge clk) begin
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// extract data
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if (dst_td_tvalid_reg) begin
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if (dst_td_tid_reg[3:0] == 4'd0) begin
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ts_sel_reg <= dst_td_tdata_reg[9];
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end
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// current
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if (dst_td_tid_reg == {4'd1, 4'd1}) begin
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if (ts_sel_reg) begin
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ts_tod_offset_ns_1_reg[15:0] <= dst_td_tdata_reg;
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end else begin
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ts_tod_offset_ns_0_reg[15:0] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd1, 4'd2}) begin
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if (ts_sel_reg) begin
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ts_tod_offset_ns_1_reg[31:16] <= dst_td_tdata_reg;
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end else begin
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ts_tod_offset_ns_0_reg[31:16] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd0, 4'd3}) begin
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if (ts_sel_reg) begin
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ts_tod_s_1_reg[15:0] <= dst_td_tdata_reg;
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end else begin
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ts_tod_s_0_reg[15:0] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd0, 4'd4}) begin
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if (ts_sel_reg) begin
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ts_tod_s_1_reg[31:16] <= dst_td_tdata_reg;
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end else begin
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ts_tod_s_0_reg[31:16] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd0, 4'd5}) begin
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if (ts_sel_reg) begin
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ts_tod_s_1_reg[47:32] <= dst_td_tdata_reg;
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end else begin
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ts_tod_s_0_reg[47:32] <= dst_td_tdata_reg;
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end
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end
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// alternate
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if (dst_td_tid_reg == {4'd2, 4'd1}) begin
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if (ts_sel_reg) begin
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ts_tod_offset_ns_0_reg[15:0] <= dst_td_tdata_reg;
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end else begin
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ts_tod_offset_ns_1_reg[15:0] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd2, 4'd2}) begin
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if (ts_sel_reg) begin
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ts_tod_offset_ns_0_reg[31:16] <= dst_td_tdata_reg;
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end else begin
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ts_tod_offset_ns_1_reg[31:16] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd2, 4'd3}) begin
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if (ts_sel_reg) begin
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ts_tod_s_0_reg[15:0] <= dst_td_tdata_reg;
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end else begin
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ts_tod_s_1_reg[15:0] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd2, 4'd4}) begin
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if (ts_sel_reg) begin
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ts_tod_s_0_reg[31:16] <= dst_td_tdata_reg;
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end else begin
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ts_tod_s_1_reg[31:16] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd2, 4'd5}) begin
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if (ts_sel_reg) begin
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ts_tod_s_0_reg[47:32] <= dst_td_tdata_reg;
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end else begin
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ts_tod_s_1_reg[47:32] <= dst_td_tdata_reg;
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end
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end
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end
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output_ts_tod_s_reg <= output_ts_tod_s_next;
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output_ts_tod_ns_reg <= output_ts_tod_ns_next;
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output_ts_fns_reg <= output_ts_fns_next;
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output_ts_id_reg <= output_ts_id_next;
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output_ts_dest_reg <= output_ts_dest_next;
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output_ts_user_reg <= output_ts_user_next;
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output_ts_valid_reg <= output_ts_valid_next;
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if (rst) begin
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output_ts_valid_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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