diff --git a/rtl/stats/taxi_stats_collect.sv b/rtl/stats/taxi_stats_collect.sv
new file mode 100644
index 0000000..fc95d02
--- /dev/null
+++ b/rtl/stats/taxi_stats_collect.sv
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * Statistics collector
+ */
+module taxi_stats_collect #
+(
+    // Channel count
+    parameter CNT = 8,
+    // Increment width (bits)
+    parameter INC_W = 8,
+    // Base statistic ID
+    parameter ID_BASE = 0,
+    // Statistics counter update period (cycles)
+    parameter UPDATE_PERIOD = 1024
+)
+(
+    input  wire logic              clk,
+    input  wire logic              rst,
+
+    /*
+     * Increment inputs
+     */
+    input  wire logic [INC_W-1:0]  stat_inc[CNT],
+    input  wire logic              stat_valid[CNT],
+
+    /*
+     * Statistics increment output
+     */
+    taxi_axis_if.src               m_axis_stat,
+
+    /*
+     * Control inputs
+     */
+    input  wire logic              update
+);
+
+localparam STAT_INC_W = m_axis_stat.DATA_W;
+localparam STAT_ID_W = m_axis_stat.ID_W;
+
+localparam CNT_W = $clog2(CNT);
+localparam PERIOD_CNT_W = $clog2(UPDATE_PERIOD+1);
+localparam ACC_W = INC_W+CNT_W+1;
+
+localparam [0:0]
+    STATE_READ = 1'd0,
+    STATE_WRITE = 1'd1;
+
+logic [0:0] state_reg = STATE_READ, state_next;
+
+logic [STAT_INC_W-1:0] m_axis_stat_tdata_reg = '0, m_axis_stat_tdata_next;
+logic [STAT_ID_W-1:0] m_axis_stat_tid_reg = '0, m_axis_stat_tid_next;
+logic m_axis_stat_tvalid_reg = 0, m_axis_stat_tvalid_next;
+
+logic [CNT_W-1:0] count_reg = '0, count_next;
+logic [PERIOD_CNT_W-1:0] update_period_reg = PERIOD_CNT_W'(UPDATE_PERIOD), update_period_next;
+logic [CNT-1:0] zero_reg = '1, zero_next;
+logic [CNT-1:0] update_reg = '0, update_next;
+
+wire [ACC_W-1:0] acc_int[CNT];
+logic [CNT-1:0] acc_clear;
+
+(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
+logic [STAT_INC_W-1:0] mem_reg[CNT];
+
+logic [STAT_INC_W-1:0] mem_rd_data_reg = '0;
+
+logic mem_rd_en;
+logic mem_wr_en;
+logic [STAT_INC_W-1:0] mem_wr_data;
+
+assign m_axis_stat.tdata = m_axis_stat_tdata_reg;
+assign m_axis_stat.tkeep = 1'b1;
+assign m_axis_stat.tstrb = m_axis_stat.tkeep;
+assign m_axis_stat.tvalid = m_axis_stat_tvalid_reg;
+assign m_axis_stat.tlast = 1'b1;
+assign m_axis_stat.tid = m_axis_stat_tid_reg;
+assign m_axis_stat.tdest = '0;
+assign m_axis_stat.tuser = '0;
+
+for (genvar n = 0; n < CNT; n = n + 1) begin
+    reg [ACC_W-1:0] acc_reg = '0;
+
+    assign acc_int[n] = acc_reg;
+
+    always_ff @(posedge clk) begin
+        if (acc_clear[n]) begin
+            if (stat_valid[n]) begin
+                acc_reg <= ACC_W'(stat_inc[n]);
+            end else begin
+                acc_reg <= '0;
+            end
+        end else begin
+            if (stat_valid[n]) begin
+                acc_reg <= acc_reg + ACC_W'(stat_inc[n]);
+            end
+        end
+
+        if (rst) begin
+            acc_reg <= '0;
+        end
+    end
+end
+
+always_comb begin
+    state_next = STATE_READ;
+
+    m_axis_stat_tdata_next = m_axis_stat_tdata_reg;
+    m_axis_stat_tid_next = m_axis_stat_tid_reg;
+    m_axis_stat_tvalid_next = m_axis_stat_tvalid_reg && !m_axis_stat.tready;
+
+    count_next = count_reg;
+    update_period_next = update_period_reg;
+    zero_next = zero_reg;
+    update_next = update_reg;
+
+    acc_clear = '0;
+
+    mem_rd_en = 1'b0;
+    mem_wr_en = 1'b0;
+    mem_wr_data = '0;
+
+    case (state_reg)
+        STATE_READ: begin
+            mem_rd_en = 1'b1;
+            state_next = STATE_WRITE;
+        end
+        STATE_WRITE: begin
+            mem_wr_en = 1'b1;
+            acc_clear[count_reg] = 1'b1;
+            if (!m_axis_stat_tvalid_reg && update_reg[count_reg]) begin
+                update_next[count_reg] = 1'b0;
+                mem_wr_data = '0;
+                if (zero_reg[count_reg]) begin
+                    m_axis_stat_tdata_next = STAT_INC_W'(acc_int[count_reg]);
+                    m_axis_stat_tid_next = STAT_ID_W'(count_reg+ID_BASE);
+                    m_axis_stat_tvalid_next = acc_int[count_reg] != 0;
+                end else begin
+                    m_axis_stat_tdata_next = STAT_INC_W'(mem_rd_data_reg + acc_int[count_reg]);
+                    m_axis_stat_tid_next = STAT_ID_W'(count_reg+ID_BASE);
+                    m_axis_stat_tvalid_next = mem_rd_data_reg != 0 || acc_int[count_reg] != 0;
+                end
+            end else begin
+                if (zero_reg[count_reg]) begin
+                    mem_wr_data = STAT_INC_W'(acc_int[count_reg]);
+                end else begin
+                    mem_wr_data = mem_rd_data_reg + STAT_INC_W'(acc_int[count_reg]);
+                end
+            end
+            zero_next[count_reg] = 1'b0;
+
+            if (count_reg == CNT_W'(CNT-1)) begin
+                count_next = '0;
+            end else begin
+                count_next = count_reg + 1;
+            end
+
+            state_next = STATE_READ;
+        end
+    endcase
+
+    if (update_period_reg == 0) begin
+        update_next = '1;
+        update_period_next = PERIOD_CNT_W'(UPDATE_PERIOD);
+    end else begin
+        update_period_next = update_period_reg - 1;
+    end
+
+    if (update) begin
+        update_next = '1;
+    end
+end
+
+always_ff @(posedge clk) begin
+    state_reg <= state_next;
+
+    m_axis_stat_tdata_reg <= m_axis_stat_tdata_next;
+    m_axis_stat_tid_reg <= m_axis_stat_tid_next;
+    m_axis_stat_tvalid_reg <= m_axis_stat_tvalid_next;
+
+    count_reg <= count_next;
+    update_period_reg <= update_period_next;
+    zero_reg <= zero_next;
+    update_reg <= update_next;
+
+    if (mem_wr_en) begin
+        mem_reg[count_reg] <= mem_wr_data;
+    end else if (mem_rd_en) begin
+        mem_rd_data_reg <= mem_reg[count_reg];
+    end
+
+    if (rst) begin
+        state_reg <= STATE_READ;
+        m_axis_stat_tvalid_reg <= 1'b0;
+        count_reg <= '0;
+        update_period_reg <= PERIOD_CNT_W'(UPDATE_PERIOD);
+        zero_reg <= '1;
+        update_reg <= '0;
+    end
+end
+
+endmodule
+
+`resetall
diff --git a/tb/stats/taxi_stats_collect/Makefile b/tb/stats/taxi_stats_collect/Makefile
new file mode 100644
index 0000000..62b8624
--- /dev/null
+++ b/tb/stats/taxi_stats_collect/Makefile
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2021-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = taxi_stats_collect
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += ../../../rtl/stats/$(DUT).sv
+VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+export PARAM_CNT := 8
+export PARAM_INC_W := 8
+export PARAM_ID_BASE := 0
+export PARAM_UPDATE_PERIOD := 128
+export PARAM_STAT_INC_W := 16
+export PARAM_STAT_ID_W := $(shell python -c "print(($(PARAM_CNT)-1).bit_length())")
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/tb/stats/taxi_stats_collect/test_taxi_stats_collect.py b/tb/stats/taxi_stats_collect/test_taxi_stats_collect.py
new file mode 100644
index 0000000..5d3f112
--- /dev/null
+++ b/tb/stats/taxi_stats_collect/test_taxi_stats_collect.py
@@ -0,0 +1,249 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2021-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import itertools
+import logging
+import os
+import random
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.queue import Queue
+from cocotb.triggers import RisingEdge, Timer
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiStreamBus, AxiStreamSink
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+        self.stat_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_stat), dut.clk, dut.rst)
+
+        for k in range(len(dut.stat_inc)):
+            dut.stat_inc[k].setimmediatevalue(0)
+            dut.stat_valid[k].setimmediatevalue(0)
+        dut.update.setimmediatevalue(0)
+
+    def set_backpressure_generator(self, generator=None):
+        if generator:
+            self.stat_sink.set_pause_generator(generator())
+
+    async def cycle_reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+
+async def run_test_acc(dut, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    stat_count = len(dut.stat_valid)
+
+    await tb.cycle_reset()
+
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    for n in range(10):
+        await RisingEdge(dut.clk)
+        dut.stat_inc.value = [k for k in range(stat_count)]
+        dut.stat_valid.value = [1]*stat_count
+        await RisingEdge(dut.clk)
+        dut.stat_inc.value = [0]*stat_count
+        dut.stat_valid.value = [0]*stat_count
+
+        await Timer(1000, 'ns')
+
+    await Timer(1000, 'ns')
+
+    data = [0]*stat_count
+
+    while not tb.stat_sink.empty():
+        stat = await tb.stat_sink.recv()
+
+        assert stat.tdata[0] != 0
+
+        data[stat.tid] += stat.tdata[0]
+
+    print(data)
+
+    for n in range(stat_count):
+        assert data[n] == n*10
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+async def run_stress_test(dut, backpressure_inserter=None):
+
+    tb = TB(dut)
+
+    stat_count = len(dut.stat_valid)
+    stat_inc_width = len(dut.stat_inc) // stat_count
+
+    await tb.cycle_reset()
+
+    tb.set_backpressure_generator(backpressure_inserter)
+
+    async def worker(num, queue_ref, queue_drive, count=1024):
+        for k in range(count):
+            count = random.randrange(1, 2**stat_inc_width)
+
+            await queue_drive.put(count)
+            await queue_ref.put((num, count))
+
+            await Timer(random.randint(1, 100), 'ns')
+
+    workers = []
+    queue_ref = Queue()
+    queue_drive = [Queue() for k in range(stat_count)]
+
+    for k in range(stat_count):
+        workers.append(cocotb.start_soon(worker(k, queue_ref, queue_drive[k], count=1024)))
+
+    async def driver(dut, queues):
+        while True:
+            await RisingEdge(dut.clk)
+
+            inc = [0]*stat_count
+            valid = [0]*stat_count
+            for num, queue in enumerate(queues):
+                if not queue.empty():
+                    count = await queue.get()
+                    inc[num] += count
+                    valid[num] = 1
+
+            dut.stat_inc.value = inc
+            dut.stat_valid.value = valid
+
+    driver = cocotb.start_soon(driver(dut, queue_drive))
+
+    while workers:
+        await workers.pop(0).join()
+
+    await Timer(1000, 'ns')
+
+    driver.kill()
+
+    await Timer(1000, 'ns')
+
+    data_ref = [0]*stat_count
+
+    while not queue_ref.empty():
+        num, count = await queue_ref.get()
+        data_ref[num] += count
+
+    print(data_ref)
+
+    data = [0]*stat_count
+
+    while not tb.stat_sink.empty():
+        stat = await tb.stat_sink.recv()
+
+        assert stat.tdata[0] != 0
+
+        data[stat.tid] += stat.tdata[0]
+
+    print(data)
+
+    assert data == data_ref
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+def cycle_pause():
+    return itertools.cycle([1, 1, 1, 0])
+
+
+if cocotb.SIM_NAME:
+
+    for test in [run_test_acc]:
+
+        factory = TestFactory(test)
+        factory.add_option("backpressure_inserter", [None, cycle_pause])
+        factory.generate_tests()
+
+    factory = TestFactory(run_stress_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.dirname(__file__)
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_stats_collect(request):
+    dut = "taxi_stats_collect"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, "stats", f"{dut}.sv"),
+        os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
+    ]
+
+    verilog_sources = process_f_files(verilog_sources)
+
+    parameters = {}
+
+    parameters['CNT'] = 8
+    parameters['INC_W'] = 8
+    parameters['ID_BASE'] = 0
+    parameters['UPDATE_PERIOD'] = 128
+    parameters['STAT_INC_W'] = 16
+    parameters['STAT_ID_W'] = (parameters['CNT']-1).bit_length()
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )
diff --git a/tb/stats/taxi_stats_collect/test_taxi_stats_collect.sv b/tb/stats/taxi_stats_collect/test_taxi_stats_collect.sv
new file mode 100644
index 0000000..c3b05a7
--- /dev/null
+++ b/tb/stats/taxi_stats_collect/test_taxi_stats_collect.sv
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * Statistics collector testbench
+ */
+module test_taxi_stats_collect #
+(
+    /* verilator lint_off WIDTHTRUNC */
+    parameter CNT = 8,
+    parameter INC_W = 8,
+    parameter ID_BASE = 0,
+    parameter UPDATE_PERIOD = 128,
+    parameter STAT_INC_W = 16,
+    parameter STAT_ID_W = $clog2(CNT)
+    /* verilator lint_on WIDTHTRUNC */
+)
+();
+
+logic clk;
+logic rst;
+
+logic [INC_W-1:0] stat_inc[CNT];
+logic [0:0] stat_valid[CNT];
+
+taxi_axis_if #(
+    .DATA_W(STAT_INC_W),
+    .KEEP_EN(0),
+    .KEEP_W(1),
+    .ID_EN(1),
+    .ID_W(STAT_ID_W)
+) m_axis_stat();
+
+logic update;
+
+taxi_stats_collect #(
+    .CNT(CNT),
+    .INC_W(INC_W),
+    .ID_BASE(ID_BASE),
+    .UPDATE_PERIOD(UPDATE_PERIOD)
+)
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Increment inputs
+     */
+    .stat_inc(stat_inc),
+    .stat_valid(stat_valid),
+
+    /*
+     * Statistics increment output
+     */
+    .m_axis_stat(m_axis_stat),
+
+    /*
+     * Control inputs
+     */
+    .update(update)
+);
+
+endmodule
+
+`resetall