From fd521a1511e7344b959342d3e94d26a21b8caa6b Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 17 Jun 2025 20:15:50 -0700 Subject: [PATCH] eth: Avoid hardcoding clock period Signed-off-by: Alex Forencich --- .../tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py b/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py index 50e0a2f..c8c2c15 100644 --- a/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py +++ b/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.py @@ -144,7 +144,7 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i if tx_frame.start_lane == 4: # start in lane 4 reports 1 full cycle delay, so subtract half clock period - tx_frame_sfd_ns -= 3.2 + tx_frame_sfd_ns -= tb.clk_period/2 tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns) tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns) @@ -153,7 +153,7 @@ async def run_test(dut, gbx_cfg=None, payload_lengths=None, payload_data=None, i assert rx_frame.tdata == test_data assert frame_error == 0 if gbx_cfg is None: - assert abs(ptp_ts_ns - tx_frame_sfd_ns - 6.4) < 0.01 + assert abs(ptp_ts_ns - tx_frame_sfd_ns - tb.clk_period) < 0.01 assert tb.sink.empty()