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eth: Update timestamping point for 32-bit BASE-R TX

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-07-23 17:58:26 -07:00
parent b06321186a
commit ff1213c605
5 changed files with 25 additions and 12 deletions
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23
src/eth/rtl/taxi_axis_baser_tx_32.sv
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@@ -226,9 +226,10 @@ logic [GBX_CNT-1:0] tx_gbx_sync_reg = '0;
logic [DATA_W-1:0] output_data_reg = '0, output_data_next;
logic [DATA_W-1:0] output_data_d1_reg = '0;
out_type_t output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;
logic output_start_packet_reg = 1'b0, output_start_packet_next;
logic start_packet_int_reg = 1'b0, start_packet_int_next;
logic start_packet_reg = 1'b0, start_packet_next;
logic start_packet_reg = 1'b0;
logic [2:0] stat_tx_byte_reg = '0, stat_tx_byte_next;
logic [15:0] stat_tx_pkt_len_reg = '0, stat_tx_pkt_len_next;
@@ -387,9 +388,9 @@ always_comb begin
output_data_next = output_data_reg;
output_type_next = output_type_reg;
output_start_packet_next = output_start_packet_reg;
start_packet_int_next = start_packet_int_reg;
start_packet_next = 1'b0;
stat_tx_byte_next = '0;
stat_tx_pkt_len_next = '0;
@@ -414,6 +415,7 @@ always_comb begin
output_data_next = output_data_reg;
output_type_next = output_type_reg;
output_start_packet_next = output_start_packet_reg;
end else if (USXGMII_EN && rep_stall_reg) begin
// USXGMII stall - replicate XGMII symbol
state_next = state_reg;
@@ -421,6 +423,7 @@ always_comb begin
output_data_next = output_data_reg;
output_type_next = output_type_reg;
output_start_packet_next = 1'b0;
// SOP/EOP are not replicated
case (output_type_reg)
@@ -498,6 +501,7 @@ always_comb begin
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
output_start_packet_next = 1'b0;
s_tdata_next = s_axis_tx.tdata;
s_empty_next = keep2empty(s_axis_tx.tkeep);
@@ -529,6 +533,7 @@ always_comb begin
output_data_next = {ETH_SFD, {2{ETH_PRE}}, 8'hAA};
output_type_next = OUTPUT_TYPE_DATA;
output_start_packet_next = 1'b0;
s_axis_tx_tready_next = 1'b1;
start_packet_int_next = 1'b1;
@@ -540,13 +545,13 @@ always_comb begin
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_DATA;
output_start_packet_next = start_packet_int_reg;
start_packet_int_next = 1'b0;
s_tdata_next = s_axis_tx.tdata;
s_empty_next = keep2empty(s_axis_tx.tkeep);
stat_tx_byte_next = 3'(KEEP_W);
start_packet_next = start_packet_int_reg;
start_packet_int_next = 1'b0;
if (s_axis_tx.tvalid && s_axis_tx.tlast) begin
if (frame_len_lim_check_reg) begin
@@ -578,6 +583,7 @@ always_comb begin
output_data_next = fcs_output_data_0;
output_type_next = fcs_output_type_0;
output_start_packet_next = 1'b0;
stat_tx_byte_next = 3'(KEEP_W);
@@ -593,6 +599,7 @@ always_comb begin
output_data_next = fcs_output_data_1;
output_type_next = fcs_output_type_1;
output_start_packet_next = 1'b0;
stat_tx_byte_next = 4-s_empty_reg;
frame_len_next = frame_len_reg + 16'(4-s_empty_reg);
@@ -619,6 +626,7 @@ always_comb begin
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_TERM_0;
output_start_packet_next = 1'b0;
stat_tx_pkt_len_next = frame_len_reg;
stat_tx_pkt_good_next = !frame_error_reg;
@@ -654,6 +662,7 @@ always_comb begin
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_ERROR;
output_start_packet_next = 1'b0;
ifg_cnt_next = cfg_tx_ifg > 8'd12 ? cfg_tx_ifg : 8'd12;
@@ -674,6 +683,7 @@ always_comb begin
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
output_start_packet_next = 1'b0;
if (DIC_EN) begin
if (ifg_cnt_next > 8'd3 || frame_reg) begin
@@ -730,7 +740,6 @@ always_ff @(posedge clk) begin
tx_os_ready_reg <= 1'b0;
start_packet_int_reg <= start_packet_int_next;
start_packet_reg <= start_packet_next;
stat_tx_byte_reg <= stat_tx_byte_next;
stat_tx_pkt_len_reg <= stat_tx_pkt_len_next;
@@ -751,8 +760,11 @@ always_ff @(posedge clk) begin
end else begin
output_data_reg <= output_data_next;
output_type_reg <= output_type_next;
output_start_packet_reg <= output_start_packet_next;
output_data_d1_reg <= output_data_reg;
start_packet_reg <= output_start_packet_reg;
if (phase_reg == 0) begin
case ({output_type_reg, output_type_next})
{OUTPUT_TYPE_IDLE, OUTPUT_TYPE_IDLE}: begin
@@ -931,6 +943,7 @@ always_ff @(posedge clk) begin
tx_gbx_sync_reg <= '0;
output_type_reg <= OUTPUT_TYPE_IDLE;
output_start_packet_reg <= 1'b0;
start_packet_reg <= 1'b0;

2
src/eth/tb/taxi_axis_baser_tx_32/test_taxi_axis_baser_tx_32.py
View File

@@ -190,7 +190,7 @@ async def run_test(dut, gbx_cfg=None, usxgmii_speed=None, payload_lengths=None,
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
if gbx_cfg is None:
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*2) < 0.01
assert abs(rx_frame_sfd_ns - ptp_ts_ns - tb.clk_period*1) < 0.01
assert tb.sink.empty()

4
src/eth/tb/taxi_eth_mac_25g_us/test_taxi_eth_mac_25g_us.py
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@@ -316,7 +316,7 @@ async def run_test_tx(dut, port=0, payload_lengths=None, payload_data=None, ifg=
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 2 + 1
else:
if dut.COMBINED_MAC_PCS.value:
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 2 + 1
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 1 + 1
else:
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 4 + 1
@@ -389,7 +389,7 @@ async def run_test_tx_alignment(dut, port=0, payload_data=None, ifg=12):
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 2 + 1
else:
if dut.COMBINED_MAC_PCS.value:
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 2 + 1
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 1 + 1
else:
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 4 + 1

4
src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.py
View File

@@ -255,7 +255,7 @@ async def run_test_tx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None
if len(dut.serdes_tx_data) == 64:
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 2 + 1
else:
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 2 + 1
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 1 + 1
tb = TB(dut, gbx_cfg)
@@ -318,7 +318,7 @@ async def run_test_tx_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12):
if len(dut.serdes_tx_data) == 64:
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 2 + 1
else:
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 2 + 1
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 1 + 1
dic_en = int(cocotb.top.DIC_EN.value)

4
src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.py
View File

@@ -219,7 +219,7 @@ async def run_test_tx(dut, gbx_cfg=None, payload_lengths=None, payload_data=None
if len(dut.serdes_tx_data) == 64:
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 2 + 1
else:
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 2 + 1
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 1 + 1
tb = TB(dut, gbx_cfg)
@@ -277,7 +277,7 @@ async def run_test_tx_alignment(dut, gbx_cfg=None, payload_data=None, ifg=12):
if len(dut.serdes_tx_data) == 64:
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 2 + 1
else:
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 2 + 1
pipe_delay = int(dut.TX_SERDES_PIPELINE.value) + 1 + 1
dic_en = int(cocotb.top.DIC_EN.value)