Commit Graph

13 Commits

Author SHA1 Message Date
Alex Forencich
34dd338acf axi: Add AXI lite interconnect module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-11-11 10:20:26 -08:00
Alex Forencich
004246608e Use logic instead of reg
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-11-07 02:14:19 -08:00
Alex Forencich
5f814e7da8 Clean up always blocks
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-11-07 01:51:18 -08:00
Alex Forencich
8f5a534d35 axi: Tie off ruser/buser in AXI lite RAM modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-09-30 16:30:32 -07:00
Alex Forencich
bdfc0f120c axi: Tie off ruser/buser in AXI RAM module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-09-30 16:28:59 -07:00
Alex Forencich
88018ac9e8 axi: Add AXI lite to APB adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-09-30 16:14:17 -07:00
Alex Forencich
e87e16c299 axi: Add AXI FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-08-30 22:17:53 -07:00
Alex Forencich
0080125120 axi: Add AXI to AXI lite adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-08-30 21:11:20 -07:00
Alex Forencich
94a821192c axi: Add AXI width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-08-30 21:10:08 -07:00
Alex Forencich
5f6487964e axi: Add MAX_BURST_LEN and NARROW_BURST_EN parameters to AXI interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-08-30 13:55:33 -07:00
Alex Forencich
e43d6acbbd axi: Add AXI lite to AXI adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-08-30 13:40:43 -07:00
Alex Forencich
c22e659259 axi: Add AXI lite width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-08-30 13:02:27 -07:00
Alex Forencich
66b53d98a2 Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-05-18 12:25:59 -07:00