Alex Forencich
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59a3d5f511
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eth: Normalize signal and register names in MAC modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-05 18:11:27 -07:00 |
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Alex Forencich
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caeacadb78
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eth: Clean up masking, lane 0 never needs to be masked
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-04 20:06:58 -07:00 |
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Alex Forencich
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93ef0f970b
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eth: Re-nest if statements for termination character handling in 10G RX logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-04 19:01:47 -07:00 |
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Alex Forencich
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7e08164e8d
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eth: Add term_first_cycle_reg to reduce fanin
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-04 17:01:53 -07:00 |
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Alex Forencich
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879b65cc70
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eth: Normalize CRC register naming in 10G RX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-04 15:54:49 -07:00 |
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Alex Forencich
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04df834708
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eth: Optimize frame length enforcement logic in BASE-R MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-03 15:49:51 -07:00 |
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Alex Forencich
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e846e7f0cd
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eth: Add gearbox support to 64-bit 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-13 16:39:55 -07:00 |
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Alex Forencich
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a1e24f2d7f
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lfsr: Add input and output enable parameters to LFSR module to remove dead code
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-10 19:08:55 -07:00 |
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Alex Forencich
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66b53d98a2
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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-18 12:25:59 -07:00 |
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