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75a3909c373e852473b9aa2e8b7963347e96e9a5
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4 Commits

Author SHA1 Message Date
Alex Forencich
7f2ecf9b49 eth: Implement RX sequence error reporting in MAC+PHY module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-22 10:16:32 -08:00
Alex Forencich
422c54229e eth: Split block type checks in MAC+PHY to reduce fanin 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-22 10:02:08 -08:00
Alex Forencich
8f6a99112b eth: Add missing block types to MAC+PHY logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-22 09:55:28 -08:00
Alex Forencich
e3f047d735 eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-02-07 16:27:27 -08:00