Commit Graph

5 Commits

Author SHA1 Message Date
Alex Forencich
8046a46680 eth: Add AXI stream 32-bit XGMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-02-07 16:25:06 -08:00
Alex Forencich
3f501aaac9 eth: Add AXI stream GMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-02-07 16:12:58 -08:00
Alex Forencich
584f2a6542 eth: Add MAC pause control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-02-05 21:11:14 -08:00
Alex Forencich
e35d2b2c03 eth: Add 10G PHY module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-02-04 17:10:21 -08:00
Alex Forencich
c6ea4071eb eth: Add XGMII/BASE-R encode/decode modules and testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-02-04 16:14:32 -08:00