Alex Forencich
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879b65cc70
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eth: Normalize CRC register naming in 10G RX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-04 15:54:49 -07:00 |
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Alex Forencich
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04df834708
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eth: Optimize frame length enforcement logic in BASE-R MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-03 15:49:51 -07:00 |
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Alex Forencich
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8257fdf09e
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eth: Remove unused encodings
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-03 13:47:52 -07:00 |
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Alex Forencich
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facdc5fe68
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eth: Remove extraneous constants
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-16 16:01:12 -07:00 |
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Alex Forencich
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a1e24f2d7f
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lfsr: Add input and output enable parameters to LFSR module to remove dead code
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-06-10 19:08:55 -07:00 |
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Alex Forencich
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e4762b7a8c
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eth: Add support for synchronous gearbox to PHY, MAC+PHY, and GT wrappers
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-30 21:14:54 -07:00 |
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Alex Forencich
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66b53d98a2
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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-18 12:25:59 -07:00 |
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