Alex Forencich
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fd3e23ef6e
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stats: Add statistics collector module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-24 23:22:04 -07:00 |
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Alex Forencich
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ee4d0da13e
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example/VCU118: Clarify MDIO prescaler setting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-24 00:04:36 -07:00 |
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Alex Forencich
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c7cf9cc1bf
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example: Clean up and annotate USB UART connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-20 17:32:31 -07:00 |
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Alex Forencich
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315a4715ff
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xfcp: Fix localparam definition
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 16:32:17 -07:00 |
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Alex Forencich
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2fd346269f
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xfcp: Add XFCP I2C master module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 15:56:39 -07:00 |
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Alex Forencich
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b8021192e3
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lss: Clean up I2C testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 14:52:26 -07:00 |
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Alex Forencich
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79e0bf6976
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lss: Remove redundant tristate control outputs on I2C modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 12:41:39 -07:00 |
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Alex Forencich
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fa2385aedb
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lss: Add I2C single register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 12:15:47 -07:00 |
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Alex Forencich
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44c811f82a
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lss: Add I2C master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-19 10:41:16 -07:00 |
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Alex Forencich
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1e3e298d9e
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Add cocotbext-i2c to tox.ini
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 10:18:03 -07:00 |
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Alex Forencich
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a86f858116
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docs: Add readthedocs yaml file
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-18 16:23:30 -07:00 |
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Alex Forencich
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115bacae02
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docs: Add sphinx infrastructure
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-18 16:12:49 -07:00 |
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Alex Forencich
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3624976f0e
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hip: Add support for optional phase shifter clock to fractional MMCM module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-17 21:05:49 -07:00 |
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Alex Forencich
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d7e29a2b5c
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hip: Add support for optional cascaded MMCM for offset clock
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-17 21:04:52 -07:00 |
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Alex Forencich
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b468d92e39
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hip: Report error if fractional MMCM configuration does not work
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-17 21:00:12 -07:00 |
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Alex Forencich
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eacae099bf
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hip: Add fractional MMCM wrapper for generating offset clocks for DDMTD
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-13 21:00:09 -07:00 |
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Alex Forencich
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ebeadee172
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lss: Implement fractional baud rate generation for UART
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-11 23:49:39 -07:00 |
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Alex Forencich
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1c686391ab
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lss: Refactor UART module to split out and share baud rate generation logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-11 23:09:19 -07:00 |
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Alex Forencich
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7df14e54e5
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xfcp: Rename signals based on upstream/downstsream port role and data direction to simplify connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-11 18:33:57 -07:00 |
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Alex Forencich
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8d4ad59727
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 17:04:03 -07:00 |
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Alex Forencich
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15653923fd
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xfcp: Add XFCP switch module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 15:30:59 -07:00 |
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Alex Forencich
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0ee729b744
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xfcp: Add XFCP AXI module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 13:28:05 -07:00 |
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Alex Forencich
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70d77c8a95
|
xfcp: Add XFCP AXI lite module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 13:25:55 -07:00 |
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Alex Forencich
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ed9e8ffab3
|
eth: Use unpacked arrays for multidimensional ports
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-07 11:05:58 -08:00 |
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Alex Forencich
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6e4988f010
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eth: Fix PFC/LFC tests for 10G MAC+PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-07 10:41:49 -08:00 |
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Alex Forencich
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cb04b84e18
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example/VCU118: Add example design for VCU118
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-07 00:29:17 -08:00 |
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Alex Forencich
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024353c68a
|
lss: Add MDIO master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 23:48:57 -08:00 |
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Alex Forencich
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ed325acb1e
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axis: Implement tstrb in pipeline FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 16:18:20 -08:00 |
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Alex Forencich
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e9ac4947ba
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axis: Normalize unpacked dimension
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 16:17:05 -08:00 |
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Alex Forencich
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56215865da
|
axi: Normalize unpacked dimension
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 16:16:29 -08:00 |
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Alex Forencich
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c422297666
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axis: Tie off unused sideband signals in COBS encoder
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 16:11:38 -08:00 |
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Alex Forencich
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194a686bda
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xfcp: Add XFCP UART interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-04 22:05:11 -08:00 |
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Alex Forencich
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98ea651532
|
axis: Use unpacked arrays for unpacking interface signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 23:24:56 -08:00 |
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Alex Forencich
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56a3c9f1ba
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axis: Add AXI stream arbitrated multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 23:24:40 -08:00 |
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Alex Forencich
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46e60d32f2
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prim: Add arbiter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 21:04:49 -08:00 |
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Alex Forencich
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5966d05740
|
prim: Add priority encoder and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 21:04:32 -08:00 |
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Alex Forencich
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a790e270b8
|
axi: Replace reg with logic in AXI lite RAM
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 13:44:18 -08:00 |
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Alex Forencich
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df300b7dad
|
axis: Add AXI stream multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 13:28:02 -08:00 |
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Alex Forencich
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aa9900de94
|
axi: Add STRB parameters to testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 10:06:56 -08:00 |
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Alex Forencich
|
ff2e3c1331
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:59:30 -08:00 |
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Alex Forencich
|
ad3042e090
|
axi: Add AXI lite dual-port RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:58:30 -08:00 |
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Alex Forencich
|
55c097f47d
|
axi: Add AXI RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:27:11 -08:00 |
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Alex Forencich
|
0632b1982e
|
axi: Add AXI lite RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:26:03 -08:00 |
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Alex Forencich
|
c478f187b1
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 21:09:29 -08:00 |
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Alex Forencich
|
ae26b61200
|
axi: Add AXI register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 21:08:39 -08:00 |
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Alex Forencich
|
1075896ecc
|
axi: Add AXI lite register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 21:02:50 -08:00 |
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Alex Forencich
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5e5bce9aa0
|
axi: Add SV interface for AXI
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 20:51:25 -08:00 |
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Alex Forencich
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5f9f71e615
|
axi: Add SV interface for AXI lite
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 20:51:16 -08:00 |
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Alex Forencich
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f419b3167a
|
axis: Switch AXI stream interface license to MIT
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 20:50:40 -08:00 |
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Alex Forencich
|
da3996cf5c
|
example/ADM_PCIE_9V3: Example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 14:16:18 -08:00 |
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