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8c3709d91703683c4bfeaba6ca65b86d2bfb0f45
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3 Commits

Author SHA1 Message Date
Alex Forencich
8c3709d917 axi: Clean up address width handling in interconnect modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-12 22:01:45 -08:00
Alex Forencich
cbbad58efb axi: Fix sideband signal handling in AXI lite crossbar 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-11 17:31:44 -08:00
Alex Forencich
053c9368e9 axi: Add AXI lite crossbar module and testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-11 15:06:32 -08:00